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fuchsia/third_party/amd-gpu/refs/heads/main/./include/asic_reg/gc/gc_10_1_0_sh_mask.h
blob: 6c2a421fe8b7ec841f0937ee89c6ec1a09f2368a [file] [edit]
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _gc_10_1_0_SH_MASK_HEADER
#define _gc_10_1_0_SH_MASK_HEADER
// addressBlock: gc_sdma0_sdma0dec
//SDMA0_DEC_START
#define SDMA0_DEC_START__START__SHIFT 0x0
#define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL
//SDMA0_PG_CNTL
#define SDMA0_PG_CNTL__CMD__SHIFT 0x0
#define SDMA0_PG_CNTL__STATUS__SHIFT 0x10
#define SDMA0_PG_CNTL__CMD_MASK 0x0000000FL
#define SDMA0_PG_CNTL__STATUS_MASK 0x000F0000L
//SDMA0_PG_CTX_LO
#define SDMA0_PG_CTX_LO__ADDR__SHIFT 0x0
#define SDMA0_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PG_CTX_HI
#define SDMA0_PG_CTX_HI__ADDR__SHIFT 0x0
#define SDMA0_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PG_CTX_CNTL
#define SDMA0_PG_CTX_CNTL__VMID__SHIFT 0x0
#define SDMA0_PG_CTX_CNTL__VMID_MASK 0x0000000FL
//SDMA0_POWER_CNTL
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
//SDMA0_CLK_CTRL
#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define SDMA0_CLK_CTRL__RESERVED_MASK 0x007FF000L
#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//SDMA0_CNTL
#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
#define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT 0x7
#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
#define SDMA0_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L
#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
//SDMA0_CHICKEN_BITS
#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15
#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18
#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L
#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L
#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
//SDMA0_GB_ADDR_CONFIG
#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
//SDMA0_GB_ADDR_CONFIG_READ
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
//SDMA0_RB_RPTR_FETCH_HI
#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
//SDMA0_RB_RPTR_FETCH
#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
//SDMA0_IB_OFFSET_FETCH
#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
//SDMA0_PROGRAM
#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
//SDMA0_STATUS_REG
#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
//SDMA0_STATUS1_REG
#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
//SDMA0_RD_BURST_CNTL
#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
//SDMA0_HBM_PAGE_CONFIG
#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
//SDMA0_UCODE_CHECKSUM
#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
//SDMA0_F32_CNTL
#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
#define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8
#define SDMA0_F32_CNTL__RESET__SHIFT 0x9
#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
#define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L
#define SDMA0_F32_CNTL__RESET_MASK 0x00000200L
//SDMA0_FREEZE
#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
#define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT 0x1
#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
#define SDMA0_FREEZE__FORCE_PREEMPT_MASK 0x00000002L
#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
//SDMA0_PHASE0_QUANTUM
#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
//SDMA0_PHASE1_QUANTUM
#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
//SDMA_POWER_GATING
#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
//SDMA_PGFSM_CONFIG
#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
//SDMA_PGFSM_WRITE
#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
//SDMA_PGFSM_READ
#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
//SDMA0_EDC_CONFIG
#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
//SDMA0_BA_THRESHOLD
#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
//SDMA0_ID
#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
//SDMA0_VERSION
#define SDMA0_VERSION__MINVER__SHIFT 0x0
#define SDMA0_VERSION__MAJVER__SHIFT 0x8
#define SDMA0_VERSION__REV__SHIFT 0x10
#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
#define SDMA0_VERSION__REV_MASK 0x003F0000L
//SDMA0_EDC_COUNTER
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
//SDMA0_EDC_COUNTER_CLEAR
#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
//SDMA0_STATUS2_REG
#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
//SDMA0_ATOMIC_CNTL
#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
//SDMA0_ATOMIC_PREOP_LO
#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
//SDMA0_ATOMIC_PREOP_HI
#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
//SDMA0_UTCL1_CNTL
#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6
#define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9
#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe
#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf
#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10
#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL
#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L
#define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L
#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L
#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L
#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L
#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
//SDMA0_UTCL1_WATERMK
#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
//SDMA0_UTCL1_RD_STATUS
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd
#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf
#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10
#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11
#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15
#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18
#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a
#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b
#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c
#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L
#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L
#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L
#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L
#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L
#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L
#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L
#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L
#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L
//SDMA0_UTCL1_WR_STATUS
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd
#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf
#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10
#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11
#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15
#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18
#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a
#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L
#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L
#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L
#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L
#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L
#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L
#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
//SDMA0_UTCL1_INV0
#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1
#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4
#define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5
#define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb
#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc
#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10
#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14
#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18
#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a
#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c
#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L
#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L
#define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L
#define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L
#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L
#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L
#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L
#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L
#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L
#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L
//SDMA0_UTCL1_INV1
#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA0_UTCL1_INV2
#define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0
#define SDMA0_UTCL1_INV2__RESERVED__SHIFT 0x10
#define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL
#define SDMA0_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L
//SDMA0_UTCL1_RD_XNACK0
#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA0_UTCL1_RD_XNACK1
#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
//SDMA0_UTCL1_WR_XNACK0
#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA0_UTCL1_WR_XNACK1
#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
//SDMA0_UTCL1_TIMEOUT
#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
//SDMA0_UTCL1_PAGE
#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
#define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb
#define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc
#define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe
#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10
#define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16
#define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17
#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L
#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L
#define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L
#define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L
#define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L
#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L
#define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L
#define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L
//SDMA0_POWER_CNTL_IDLE
#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
//SDMA0_RELAX_ORDERING_LUT
#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
//SDMA0_CHICKEN_BITS_2
#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4
#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L
//SDMA0_STATUS3_REG
#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15
#define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16
#define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17
#define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18
#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19
#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a
#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L
#define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L
#define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L
#define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L
#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L
#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L
//SDMA0_PHYSICAL_ADDR_LO
#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
//SDMA0_PHYSICAL_ADDR_HI
#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
//SDMA0_PHASE2_QUANTUM
#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
//SDMA0_F32_COUNTER
#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
//SDMA0_PERFMON_CNTL
#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
//SDMA0_PERFCOUNTER0_RESULT
#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//SDMA0_PERFCOUNTER1_RESULT
#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
//SDMA0_CRD_CNTL
#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13
#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19
#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L
#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L
//SDMA0_GPU_IOV_VIOLATION_LOG
//SDMA0_AQL_STATUS
#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0
#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1
#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L
#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L
//SDMA0_EA_DBIT_ADDR_DATA
#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
//SDMA0_EA_DBIT_ADDR_INDEX
#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
//SDMA0_TLBI_GCR_CNTL
#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0
#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4
#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8
#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10
#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18
#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL
#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L
#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L
#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L
#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L
//SDMA0_TILING_CONFIG
#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
//SDMA0_HASH
#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
#define SDMA0_HASH__CHANNEL_BITS_MASK 0x00000007L
#define SDMA0_HASH__BANK_BITS_MASK 0x00000070L
#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L
#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x00007000L
//SDMA0_PERFCOUNTER0_SELECT
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//SDMA0_PERFCOUNTER0_SELECT1
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SDMA0_PERFCOUNTER0_LO
#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SDMA0_PERFCOUNTER0_HI
#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SDMA0_PERFCOUNTER1_SELECT
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//SDMA0_PERFCOUNTER1_SELECT1
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SDMA0_PERFCOUNTER1_LO
#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SDMA0_PERFCOUNTER1_HI
#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SDMA0_INT_STATUS
#define SDMA0_INT_STATUS__DATA__SHIFT 0x0
#define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL
//SDMA0_GPU_IOV_VIOLATION_LOG2
#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
//SDMA0_HOLE_ADDR_LO
#define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0
#define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL
//SDMA0_HOLE_ADDR_HI
#define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0
#define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_CNTL
#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_GFX_RB_BASE
#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_BASE_HI
#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_GFX_RB_RPTR
#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_RPTR_HI
#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR
#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_HI
#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_CNTL
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_GFX_RB_RPTR_ADDR_HI
#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_RPTR_ADDR_LO
#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_GFX_IB_CNTL
#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_GFX_IB_RPTR
#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_GFX_IB_OFFSET
#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_GFX_IB_BASE_LO
#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_GFX_IB_BASE_HI
#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_GFX_IB_SIZE
#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_GFX_SKIP_CNTL
#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_GFX_CONTEXT_STATUS
#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_GFX_DOORBELL
#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_GFX_CONTEXT_CNTL
#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
//SDMA0_GFX_STATUS
#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_GFX_DOORBELL_LOG
//SDMA0_GFX_WATERMARK
#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_GFX_DOORBELL_OFFSET
#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_GFX_CSA_ADDR_LO
#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_GFX_CSA_ADDR_HI
#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_GFX_IB_SUB_REMAIN
#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_GFX_PREEMPT
#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_GFX_DUMMY_REG
#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_GFX_RB_AQL_CNTL
#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_GFX_MINOR_PTR_UPDATE
#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_GFX_MIDCMD_DATA0
#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA1
#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA2
#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA3
#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA4
#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA5
#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA6
#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA7
#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA8
#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_CNTL
#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_PAGE_RB_CNTL
#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_PAGE_RB_BASE
#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_BASE_HI
#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_PAGE_RB_RPTR
#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_RPTR_HI
#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR
#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_HI
#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_CNTL
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_PAGE_RB_RPTR_ADDR_HI
#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_RPTR_ADDR_LO
#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_PAGE_IB_CNTL
#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_PAGE_IB_RPTR
#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_PAGE_IB_OFFSET
#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_PAGE_IB_BASE_LO
#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_PAGE_IB_BASE_HI
#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PAGE_IB_SIZE
#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_PAGE_SKIP_CNTL
#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_PAGE_CONTEXT_STATUS
#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_PAGE_DOORBELL
#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_PAGE_STATUS
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_PAGE_DOORBELL_LOG
//SDMA0_PAGE_WATERMARK
#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_PAGE_DOORBELL_OFFSET
#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_PAGE_CSA_ADDR_LO
#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_PAGE_CSA_ADDR_HI
#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PAGE_IB_SUB_REMAIN
#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_PAGE_PREEMPT
#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_PAGE_DUMMY_REG
#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_PAGE_RB_AQL_CNTL
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_PAGE_MINOR_PTR_UPDATE
#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_PAGE_MIDCMD_DATA0
#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA1
#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA2
#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA3
#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA4
#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA5
#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA6
#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA7
#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA8
#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_CNTL
#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC0_RB_CNTL
#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC0_RB_BASE
#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_BASE_HI
#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC0_RB_RPTR
#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_RPTR_HI
#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR
#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_HI
#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_CNTL
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC0_RB_RPTR_ADDR_HI
#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_RPTR_ADDR_LO
#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC0_IB_CNTL
#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC0_IB_RPTR
#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC0_IB_OFFSET
#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC0_IB_BASE_LO
#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC0_IB_BASE_HI
#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC0_IB_SIZE
#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC0_SKIP_CNTL
#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC0_CONTEXT_STATUS
#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC0_DOORBELL
#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC0_STATUS
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC0_DOORBELL_LOG
//SDMA0_RLC0_WATERMARK
#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC0_DOORBELL_OFFSET
#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC0_CSA_ADDR_LO
#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC0_CSA_ADDR_HI
#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC0_IB_SUB_REMAIN
#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC0_PREEMPT
#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC0_DUMMY_REG
#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC0_RB_AQL_CNTL
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC0_MINOR_PTR_UPDATE
#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC0_MIDCMD_DATA0
#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA1
#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA2
#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA3
#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA4
#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA5
#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA6
#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA7
#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA8
#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_CNTL
#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC1_RB_CNTL
#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC1_RB_BASE
#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_BASE_HI
#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC1_RB_RPTR
#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_RPTR_HI
#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR
#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_HI
#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_CNTL
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC1_RB_RPTR_ADDR_HI
#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_RPTR_ADDR_LO
#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC1_IB_CNTL
#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC1_IB_RPTR
#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC1_IB_OFFSET
#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC1_IB_BASE_LO
#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC1_IB_BASE_HI
#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC1_IB_SIZE
#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC1_SKIP_CNTL
#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC1_CONTEXT_STATUS
#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC1_DOORBELL
#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC1_STATUS
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC1_DOORBELL_LOG
//SDMA0_RLC1_WATERMARK
#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC1_DOORBELL_OFFSET
#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC1_CSA_ADDR_LO
#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC1_CSA_ADDR_HI
#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC1_IB_SUB_REMAIN
#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC1_PREEMPT
#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC1_DUMMY_REG
#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC1_RB_AQL_CNTL
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC1_MINOR_PTR_UPDATE
#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC1_MIDCMD_DATA0
#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA1
#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA2
#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA3
#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA4
#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA5
#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA6
#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA7
#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA8
#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_CNTL
#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC2_RB_CNTL
#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC2_RB_BASE
#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_BASE_HI
#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC2_RB_RPTR
#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_RPTR_HI
#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR
#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_HI
#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_CNTL
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC2_RB_RPTR_ADDR_HI
#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_RPTR_ADDR_LO
#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC2_IB_CNTL
#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC2_IB_RPTR
#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC2_IB_OFFSET
#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC2_IB_BASE_LO
#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC2_IB_BASE_HI
#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC2_IB_SIZE
#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC2_SKIP_CNTL
#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC2_CONTEXT_STATUS
#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC2_DOORBELL
#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC2_STATUS
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC2_DOORBELL_LOG
//SDMA0_RLC2_WATERMARK
#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC2_DOORBELL_OFFSET
#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC2_CSA_ADDR_LO
#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC2_CSA_ADDR_HI
#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC2_IB_SUB_REMAIN
#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC2_PREEMPT
#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC2_DUMMY_REG
#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC2_RB_AQL_CNTL
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC2_MINOR_PTR_UPDATE
#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC2_MIDCMD_DATA0
#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA1
#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA2
#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA3
#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA4
#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA5
#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA6
#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA7
#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA8
#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_CNTL
#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC3_RB_CNTL
#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC3_RB_BASE
#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_BASE_HI
#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC3_RB_RPTR
#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_RPTR_HI
#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR
#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_HI
#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_CNTL
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC3_RB_RPTR_ADDR_HI
#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_RPTR_ADDR_LO
#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC3_IB_CNTL
#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC3_IB_RPTR
#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC3_IB_OFFSET
#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC3_IB_BASE_LO
#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC3_IB_BASE_HI
#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC3_IB_SIZE
#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC3_SKIP_CNTL
#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC3_CONTEXT_STATUS
#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC3_DOORBELL
#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC3_STATUS
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC3_DOORBELL_LOG
//SDMA0_RLC3_WATERMARK
#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC3_DOORBELL_OFFSET
#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC3_CSA_ADDR_LO
#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC3_CSA_ADDR_HI
#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC3_IB_SUB_REMAIN
#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC3_PREEMPT
#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC3_DUMMY_REG
#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC3_RB_AQL_CNTL
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC3_MINOR_PTR_UPDATE
#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC3_MIDCMD_DATA0
#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA1
#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA2
#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA3
#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA4
#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA5
#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA6
#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA7
#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA8
#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_CNTL
#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC4_RB_CNTL
#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC4_RB_BASE
#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_BASE_HI
#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC4_RB_RPTR
#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_RPTR_HI
#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR
#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_HI
#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_CNTL
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC4_RB_RPTR_ADDR_HI
#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_RPTR_ADDR_LO
#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC4_IB_CNTL
#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC4_IB_RPTR
#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC4_IB_OFFSET
#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC4_IB_BASE_LO
#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC4_IB_BASE_HI
#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC4_IB_SIZE
#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC4_SKIP_CNTL
#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC4_CONTEXT_STATUS
#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC4_DOORBELL
#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC4_STATUS
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC4_DOORBELL_LOG
//SDMA0_RLC4_WATERMARK
#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC4_DOORBELL_OFFSET
#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC4_CSA_ADDR_LO
#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC4_CSA_ADDR_HI
#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC4_IB_SUB_REMAIN
#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC4_PREEMPT
#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC4_DUMMY_REG
#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC4_RB_AQL_CNTL
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC4_MINOR_PTR_UPDATE
#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC4_MIDCMD_DATA0
#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA1
#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA2
#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA3
#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA4
#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA5
#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA6
#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA7
#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA8
#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_CNTL
#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC5_RB_CNTL
#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC5_RB_BASE
#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_BASE_HI
#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC5_RB_RPTR
#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_RPTR_HI
#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR
#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_HI
#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_CNTL
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC5_RB_RPTR_ADDR_HI
#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_RPTR_ADDR_LO
#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC5_IB_CNTL
#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC5_IB_RPTR
#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC5_IB_OFFSET
#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC5_IB_BASE_LO
#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC5_IB_BASE_HI
#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC5_IB_SIZE
#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC5_SKIP_CNTL
#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC5_CONTEXT_STATUS
#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC5_DOORBELL
#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC5_STATUS
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC5_DOORBELL_LOG
//SDMA0_RLC5_WATERMARK
#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC5_DOORBELL_OFFSET
#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC5_CSA_ADDR_LO
#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC5_CSA_ADDR_HI
#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC5_IB_SUB_REMAIN
#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC5_PREEMPT
#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC5_DUMMY_REG
#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC5_RB_AQL_CNTL
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC5_MINOR_PTR_UPDATE
#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC5_MIDCMD_DATA0
#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA1
#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA2
#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA3
#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA4
#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA5
#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA6
#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA7
#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA8
#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_CNTL
#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC6_RB_CNTL
#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC6_RB_BASE
#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_BASE_HI
#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC6_RB_RPTR
#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_RPTR_HI
#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR
#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_HI
#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_CNTL
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC6_RB_RPTR_ADDR_HI
#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_RPTR_ADDR_LO
#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC6_IB_CNTL
#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC6_IB_RPTR
#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC6_IB_OFFSET
#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC6_IB_BASE_LO
#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC6_IB_BASE_HI
#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC6_IB_SIZE
#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC6_SKIP_CNTL
#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC6_CONTEXT_STATUS
#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC6_DOORBELL
#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC6_STATUS
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC6_DOORBELL_LOG
//SDMA0_RLC6_WATERMARK
#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC6_DOORBELL_OFFSET
#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC6_CSA_ADDR_LO
#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC6_CSA_ADDR_HI
#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC6_IB_SUB_REMAIN
#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC6_PREEMPT
#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC6_DUMMY_REG
#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC6_RB_AQL_CNTL
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC6_MINOR_PTR_UPDATE
#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC6_MIDCMD_DATA0
#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA1
#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA2
#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA3
#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA4
#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA5
#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA6
#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA7
#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA8
#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_CNTL
#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA0_RLC7_RB_CNTL
#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA0_RLC7_RB_BASE
#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0
#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_BASE_HI
#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA0_RLC7_RB_RPTR
#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_RPTR_HI
#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR
#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_HI
#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_CNTL
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA0_RLC7_RB_RPTR_ADDR_HI
#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_RPTR_ADDR_LO
#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC7_IB_CNTL
#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA0_RLC7_IB_RPTR
#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC7_IB_OFFSET
#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA0_RLC7_IB_BASE_LO
#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA0_RLC7_IB_BASE_HI
#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC7_IB_SIZE
#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA0_RLC7_SKIP_CNTL
#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA0_RLC7_CONTEXT_STATUS
#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA0_RLC7_DOORBELL
#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA0_RLC7_STATUS
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA0_RLC7_DOORBELL_LOG
//SDMA0_RLC7_WATERMARK
#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA0_RLC7_DOORBELL_OFFSET
#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA0_RLC7_CSA_ADDR_LO
#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC7_CSA_ADDR_HI
#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC7_IB_SUB_REMAIN
#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA0_RLC7_PREEMPT
#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA0_RLC7_DUMMY_REG
#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA0_RLC7_RB_AQL_CNTL
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA0_RLC7_MINOR_PTR_UPDATE
#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA0_RLC7_MIDCMD_DATA0
#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA1
#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA2
#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA3
#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA4
#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA5
#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA6
#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA7
#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA8
#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_CNTL
#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
// addressBlock: gc_sdma1_sdma1dec
//SDMA1_DEC_START
#define SDMA1_DEC_START__START__SHIFT 0x0
#define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL
//SDMA1_PG_CNTL
#define SDMA1_PG_CNTL__CMD__SHIFT 0x0
#define SDMA1_PG_CNTL__STATUS__SHIFT 0x10
#define SDMA1_PG_CNTL__CMD_MASK 0x0000000FL
#define SDMA1_PG_CNTL__STATUS_MASK 0x000F0000L
//SDMA1_PG_CTX_LO
#define SDMA1_PG_CTX_LO__ADDR__SHIFT 0x0
#define SDMA1_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PG_CTX_HI
#define SDMA1_PG_CTX_HI__ADDR__SHIFT 0x0
#define SDMA1_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PG_CTX_CNTL
#define SDMA1_PG_CTX_CNTL__VMID__SHIFT 0x4
#define SDMA1_PG_CTX_CNTL__VMID_MASK 0x000000F0L
//SDMA1_POWER_CNTL
#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
//SDMA1_CLK_CTRL
#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
#define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define SDMA1_CLK_CTRL__RESERVED_MASK 0x007FF000L
#define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//SDMA1_CNTL
#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
#define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT 0x7
#define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
#define SDMA1_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L
#define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L
#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
//SDMA1_CHICKEN_BITS
#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13
#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15
#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18
#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L
#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L
#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L
#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
//SDMA1_GB_ADDR_CONFIG
#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
//SDMA1_GB_ADDR_CONFIG_READ
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
//SDMA1_RB_RPTR_FETCH_HI
#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
//SDMA1_RB_RPTR_FETCH
#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
//SDMA1_IB_OFFSET_FETCH
#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
//SDMA1_PROGRAM
#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
//SDMA1_STATUS_REG
#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
//SDMA1_STATUS1_REG
#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
//SDMA1_RD_BURST_CNTL
#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
//SDMA1_HBM_PAGE_CONFIG
#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L
//SDMA1_UCODE_CHECKSUM
#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
//SDMA1_F32_CNTL
#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
#define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8
#define SDMA1_F32_CNTL__RESET__SHIFT 0x9
#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
#define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L
#define SDMA1_F32_CNTL__RESET_MASK 0x00000200L
//SDMA1_FREEZE
#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
#define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT 0x1
#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
#define SDMA1_FREEZE__FORCE_PREEMPT_MASK 0x00000002L
#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
//SDMA1_PHASE0_QUANTUM
#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
//SDMA1_PHASE1_QUANTUM
#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
//SDMA1_EDC_CONFIG
#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
//SDMA1_BA_THRESHOLD
#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
//SDMA1_ID
#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
//SDMA1_VERSION
#define SDMA1_VERSION__MINVER__SHIFT 0x0
#define SDMA1_VERSION__MAJVER__SHIFT 0x8
#define SDMA1_VERSION__REV__SHIFT 0x10
#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
#define SDMA1_VERSION__REV_MASK 0x003F0000L
//SDMA1_EDC_COUNTER
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
//SDMA1_EDC_COUNTER_CLEAR
#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
//SDMA1_STATUS2_REG
#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L
#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
//SDMA1_ATOMIC_CNTL
#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
//SDMA1_ATOMIC_PREOP_LO
#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
//SDMA1_ATOMIC_PREOP_HI
#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
//SDMA1_UTCL1_CNTL
#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6
#define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9
#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe
#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf
#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10
#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL
#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L
#define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L
#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L
#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L
#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L
#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
//SDMA1_UTCL1_WATERMK
#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
//SDMA1_UTCL1_RD_STATUS
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd
#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf
#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10
#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11
#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15
#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18
#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a
#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b
#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c
#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L
#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L
#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L
#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L
#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L
#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L
#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L
#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L
#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L
//SDMA1_UTCL1_WR_STATUS
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd
#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf
#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10
#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11
#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15
#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18
#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a
#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L
#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L
#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L
#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L
#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L
#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L
#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
//SDMA1_UTCL1_INV0
#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1
#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4
#define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5
#define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb
#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc
#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10
#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14
#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18
#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a
#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c
#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L
#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L
#define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L
#define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L
#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L
#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L
#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L
#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L
#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L
#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L
//SDMA1_UTCL1_INV1
#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA1_UTCL1_INV2
#define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0
#define SDMA1_UTCL1_INV2__RESERVED__SHIFT 0x10
#define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL
#define SDMA1_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L
//SDMA1_UTCL1_RD_XNACK0
#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA1_UTCL1_RD_XNACK1
#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
//SDMA1_UTCL1_WR_XNACK0
#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
//SDMA1_UTCL1_WR_XNACK1
#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
//SDMA1_UTCL1_TIMEOUT
#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
//SDMA1_UTCL1_PAGE
#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
#define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb
#define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc
#define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe
#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10
#define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16
#define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17
#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L
#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L
#define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L
#define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L
#define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L
#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L
#define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L
#define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L
//SDMA1_POWER_CNTL_IDLE
#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
//SDMA1_RELAX_ORDERING_LUT
#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
//SDMA1_CHICKEN_BITS_2
#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4
#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L
//SDMA1_STATUS3_REG
#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15
#define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16
#define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17
#define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18
#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19
#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a
#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L
#define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L
#define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L
#define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L
#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L
#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L
//SDMA1_PHYSICAL_ADDR_LO
#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
//SDMA1_PHYSICAL_ADDR_HI
#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
//SDMA1_PHASE2_QUANTUM
#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
//SDMA1_F32_COUNTER
#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
//SDMA1_PERFMON_CNTL
#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
//SDMA1_PERFCOUNTER0_RESULT
#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//SDMA1_PERFCOUNTER1_RESULT
#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
//SDMA1_CRD_CNTL
#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13
#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19
#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L
#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L
//SDMA1_GPU_IOV_VIOLATION_LOG
//SDMA1_AQL_STATUS
#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0
#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1
#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L
#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L
//SDMA1_EA_DBIT_ADDR_DATA
#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
//SDMA1_EA_DBIT_ADDR_INDEX
#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
//SDMA1_TLBI_GCR_CNTL
#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0
#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4
#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8
#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10
#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18
#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL
#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L
#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L
#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L
#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L
//SDMA1_TILING_CONFIG
#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
//SDMA1_HASH
#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
#define SDMA1_HASH__CHANNEL_BITS_MASK 0x00000007L
#define SDMA1_HASH__BANK_BITS_MASK 0x00000070L
#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L
#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x00007000L
//SDMA1_PERFCOUNTER0_SELECT
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//SDMA1_PERFCOUNTER0_SELECT1
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SDMA1_PERFCOUNTER0_LO
#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SDMA1_PERFCOUNTER0_HI
#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SDMA1_PERFCOUNTER1_SELECT
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//SDMA1_PERFCOUNTER1_SELECT1
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SDMA1_PERFCOUNTER1_LO
#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SDMA1_PERFCOUNTER1_HI
#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SDMA1_INT_STATUS
#define SDMA1_INT_STATUS__DATA__SHIFT 0x0
#define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL
//SDMA1_GPU_IOV_VIOLATION_LOG2
#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
//SDMA1_HOLE_ADDR_LO
#define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0
#define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL
//SDMA1_HOLE_ADDR_HI
#define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0
#define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_CNTL
#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_GFX_RB_BASE
#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_BASE_HI
#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_GFX_RB_RPTR
#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_RPTR_HI
#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR
#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_HI
#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_CNTL
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_GFX_RB_RPTR_ADDR_HI
#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_RPTR_ADDR_LO
#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_GFX_IB_CNTL
#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_GFX_IB_RPTR
#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_GFX_IB_OFFSET
#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_GFX_IB_BASE_LO
#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_GFX_IB_BASE_HI
#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_GFX_IB_SIZE
#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_GFX_SKIP_CNTL
#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_GFX_CONTEXT_STATUS
#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_GFX_DOORBELL
#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_GFX_CONTEXT_CNTL
#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
//SDMA1_GFX_STATUS
#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_GFX_DOORBELL_LOG
//SDMA1_GFX_WATERMARK
#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_GFX_DOORBELL_OFFSET
#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_GFX_CSA_ADDR_LO
#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_GFX_CSA_ADDR_HI
#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_GFX_IB_SUB_REMAIN
#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_GFX_PREEMPT
#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_GFX_DUMMY_REG
#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_GFX_RB_AQL_CNTL
#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_GFX_MINOR_PTR_UPDATE
#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_GFX_MIDCMD_DATA0
#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA1
#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA2
#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA3
#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA4
#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA5
#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA6
#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA7
#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA8
#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_CNTL
#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_PAGE_RB_CNTL
#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_PAGE_RB_BASE
#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_BASE_HI
#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_PAGE_RB_RPTR
#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_RPTR_HI
#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR
#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_HI
#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_CNTL
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_PAGE_RB_RPTR_ADDR_HI
#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_RPTR_ADDR_LO
#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_PAGE_IB_CNTL
#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_PAGE_IB_RPTR
#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_PAGE_IB_OFFSET
#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_PAGE_IB_BASE_LO
#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_PAGE_IB_BASE_HI
#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PAGE_IB_SIZE
#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_PAGE_SKIP_CNTL
#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_PAGE_CONTEXT_STATUS
#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_PAGE_DOORBELL
#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_PAGE_STATUS
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_PAGE_DOORBELL_LOG
//SDMA1_PAGE_WATERMARK
#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_PAGE_DOORBELL_OFFSET
#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_PAGE_CSA_ADDR_LO
#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_PAGE_CSA_ADDR_HI
#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PAGE_IB_SUB_REMAIN
#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_PAGE_PREEMPT
#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_PAGE_DUMMY_REG
#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_PAGE_RB_AQL_CNTL
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_PAGE_MINOR_PTR_UPDATE
#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_PAGE_MIDCMD_DATA0
#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA1
#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA2
#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA3
#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA4
#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA5
#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA6
#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA7
#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA8
#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_CNTL
#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC0_RB_CNTL
#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC0_RB_BASE
#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_BASE_HI
#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC0_RB_RPTR
#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_RPTR_HI
#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR
#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_HI
#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_CNTL
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC0_RB_RPTR_ADDR_HI
#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_RPTR_ADDR_LO
#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC0_IB_CNTL
#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC0_IB_RPTR
#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC0_IB_OFFSET
#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC0_IB_BASE_LO
#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC0_IB_BASE_HI
#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC0_IB_SIZE
#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC0_SKIP_CNTL
#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC0_CONTEXT_STATUS
#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC0_DOORBELL
#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC0_STATUS
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC0_DOORBELL_LOG
//SDMA1_RLC0_WATERMARK
#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC0_DOORBELL_OFFSET
#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC0_CSA_ADDR_LO
#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC0_CSA_ADDR_HI
#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC0_IB_SUB_REMAIN
#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC0_PREEMPT
#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC0_DUMMY_REG
#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC0_RB_AQL_CNTL
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC0_MINOR_PTR_UPDATE
#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC0_MIDCMD_DATA0
#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA1
#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA2
#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA3
#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA4
#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA5
#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA6
#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA7
#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA8
#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_CNTL
#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC1_RB_CNTL
#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC1_RB_BASE
#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_BASE_HI
#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC1_RB_RPTR
#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_RPTR_HI
#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR
#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_HI
#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_CNTL
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC1_RB_RPTR_ADDR_HI
#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_RPTR_ADDR_LO
#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC1_IB_CNTL
#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC1_IB_RPTR
#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC1_IB_OFFSET
#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC1_IB_BASE_LO
#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC1_IB_BASE_HI
#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC1_IB_SIZE
#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC1_SKIP_CNTL
#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC1_CONTEXT_STATUS
#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC1_DOORBELL
#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC1_STATUS
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC1_DOORBELL_LOG
//SDMA1_RLC1_WATERMARK
#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC1_DOORBELL_OFFSET
#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC1_CSA_ADDR_LO
#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC1_CSA_ADDR_HI
#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC1_IB_SUB_REMAIN
#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC1_PREEMPT
#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC1_DUMMY_REG
#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC1_RB_AQL_CNTL
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC1_MINOR_PTR_UPDATE
#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC1_MIDCMD_DATA0
#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA1
#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA2
#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA3
#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA4
#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA5
#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA6
#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA7
#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA8
#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_CNTL
#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC2_RB_CNTL
#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC2_RB_BASE
#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_BASE_HI
#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC2_RB_RPTR
#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_RPTR_HI
#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR
#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_HI
#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_CNTL
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC2_RB_RPTR_ADDR_HI
#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_RPTR_ADDR_LO
#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC2_IB_CNTL
#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC2_IB_RPTR
#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC2_IB_OFFSET
#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC2_IB_BASE_LO
#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC2_IB_BASE_HI
#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC2_IB_SIZE
#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC2_SKIP_CNTL
#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC2_CONTEXT_STATUS
#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC2_DOORBELL
#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC2_STATUS
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC2_DOORBELL_LOG
//SDMA1_RLC2_WATERMARK
#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC2_DOORBELL_OFFSET
#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC2_CSA_ADDR_LO
#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC2_CSA_ADDR_HI
#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC2_IB_SUB_REMAIN
#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC2_PREEMPT
#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC2_DUMMY_REG
#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC2_RB_AQL_CNTL
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC2_MINOR_PTR_UPDATE
#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC2_MIDCMD_DATA0
#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA1
#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA2
#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA3
#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA4
#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA5
#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA6
#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA7
#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA8
#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_CNTL
#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC3_RB_CNTL
#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC3_RB_BASE
#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_BASE_HI
#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC3_RB_RPTR
#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_RPTR_HI
#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR
#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_HI
#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_CNTL
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC3_RB_RPTR_ADDR_HI
#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_RPTR_ADDR_LO
#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC3_IB_CNTL
#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC3_IB_RPTR
#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC3_IB_OFFSET
#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC3_IB_BASE_LO
#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC3_IB_BASE_HI
#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC3_IB_SIZE
#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC3_SKIP_CNTL
#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC3_CONTEXT_STATUS
#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC3_DOORBELL
#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC3_STATUS
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC3_DOORBELL_LOG
//SDMA1_RLC3_WATERMARK
#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC3_DOORBELL_OFFSET
#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC3_CSA_ADDR_LO
#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC3_CSA_ADDR_HI
#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC3_IB_SUB_REMAIN
#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC3_PREEMPT
#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC3_DUMMY_REG
#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC3_RB_AQL_CNTL
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC3_MINOR_PTR_UPDATE
#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC3_MIDCMD_DATA0
#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA1
#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA2
#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA3
#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA4
#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA5
#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA6
#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA7
#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA8
#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_CNTL
#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC4_RB_CNTL
#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC4_RB_BASE
#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_BASE_HI
#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC4_RB_RPTR
#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_RPTR_HI
#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR
#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_HI
#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_CNTL
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC4_RB_RPTR_ADDR_HI
#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_RPTR_ADDR_LO
#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC4_IB_CNTL
#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC4_IB_RPTR
#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC4_IB_OFFSET
#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC4_IB_BASE_LO
#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC4_IB_BASE_HI
#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC4_IB_SIZE
#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC4_SKIP_CNTL
#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC4_CONTEXT_STATUS
#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC4_DOORBELL
#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC4_STATUS
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC4_DOORBELL_LOG
//SDMA1_RLC4_WATERMARK
#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC4_DOORBELL_OFFSET
#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC4_CSA_ADDR_LO
#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC4_CSA_ADDR_HI
#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC4_IB_SUB_REMAIN
#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC4_PREEMPT
#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC4_DUMMY_REG
#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC4_RB_AQL_CNTL
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC4_MINOR_PTR_UPDATE
#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC4_MIDCMD_DATA0
#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA1
#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA2
#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA3
#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA4
#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA5
#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA6
#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA7
#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA8
#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_CNTL
#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC5_RB_CNTL
#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC5_RB_BASE
#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_BASE_HI
#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC5_RB_RPTR
#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_RPTR_HI
#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR
#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_HI
#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_CNTL
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC5_RB_RPTR_ADDR_HI
#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_RPTR_ADDR_LO
#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC5_IB_CNTL
#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC5_IB_RPTR
#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC5_IB_OFFSET
#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC5_IB_BASE_LO
#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC5_IB_BASE_HI
#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC5_IB_SIZE
#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC5_SKIP_CNTL
#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC5_CONTEXT_STATUS
#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC5_DOORBELL
#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC5_STATUS
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC5_DOORBELL_LOG
//SDMA1_RLC5_WATERMARK
#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC5_DOORBELL_OFFSET
#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC5_CSA_ADDR_LO
#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC5_CSA_ADDR_HI
#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC5_IB_SUB_REMAIN
#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC5_PREEMPT
#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC5_DUMMY_REG
#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC5_RB_AQL_CNTL
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC5_MINOR_PTR_UPDATE
#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC5_MIDCMD_DATA0
#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA1
#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA2
#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA3
#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA4
#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA5
#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA6
#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA7
#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA8
#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_CNTL
#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC6_RB_CNTL
#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC6_RB_BASE
#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_BASE_HI
#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC6_RB_RPTR
#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_RPTR_HI
#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR
#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_HI
#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_CNTL
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC6_RB_RPTR_ADDR_HI
#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_RPTR_ADDR_LO
#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC6_IB_CNTL
#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC6_IB_RPTR
#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC6_IB_OFFSET
#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC6_IB_BASE_LO
#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC6_IB_BASE_HI
#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC6_IB_SIZE
#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC6_SKIP_CNTL
#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC6_CONTEXT_STATUS
#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC6_DOORBELL
#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC6_STATUS
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC6_DOORBELL_LOG
//SDMA1_RLC6_WATERMARK
#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC6_DOORBELL_OFFSET
#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC6_CSA_ADDR_LO
#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC6_CSA_ADDR_HI
#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC6_IB_SUB_REMAIN
#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC6_PREEMPT
#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC6_DUMMY_REG
#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC6_RB_AQL_CNTL
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC6_MINOR_PTR_UPDATE
#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC6_MIDCMD_DATA0
#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA1
#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA2
#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA3
#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA4
#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA5
#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA6
#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA7
#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA8
#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_CNTL
#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
//SDMA1_RLC7_RB_CNTL
#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
//SDMA1_RLC7_RB_BASE
#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0
#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_BASE_HI
#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
//SDMA1_RLC7_RB_RPTR
#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_RPTR_HI
#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR
#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_HI
#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_CNTL
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//SDMA1_RLC7_RB_RPTR_ADDR_HI
#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_RPTR_ADDR_LO
#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC7_IB_CNTL
#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
//SDMA1_RLC7_IB_RPTR
#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC7_IB_OFFSET
#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
//SDMA1_RLC7_IB_BASE_LO
#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
//SDMA1_RLC7_IB_BASE_HI
#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC7_IB_SIZE
#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0
#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
//SDMA1_RLC7_SKIP_CNTL
#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
//SDMA1_RLC7_CONTEXT_STATUS
#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
//SDMA1_RLC7_DOORBELL
#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
//SDMA1_RLC7_STATUS
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
//SDMA1_RLC7_DOORBELL_LOG
//SDMA1_RLC7_WATERMARK
#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
//SDMA1_RLC7_DOORBELL_OFFSET
#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
//SDMA1_RLC7_CSA_ADDR_LO
#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC7_CSA_ADDR_HI
#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC7_IB_SUB_REMAIN
#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
//SDMA1_RLC7_PREEMPT
#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
//SDMA1_RLC7_DUMMY_REG
#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA1_RLC7_RB_AQL_CNTL
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
//SDMA1_RLC7_MINOR_PTR_UPDATE
#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
//SDMA1_RLC7_MIDCMD_DATA0
#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA1
#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA2
#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA3
#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA4
#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA5
#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA6
#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA7
#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA8
#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_CNTL
#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
// addressBlock: gc_grbmdec
//GRBM_CNTL
#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
//GRBM_SKEW_CNTL
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
//GRBM_STATUS2
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
#define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15
#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16
#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17
#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
#define GRBM_STATUS2__TCP_BUSY__SHIFT 0x19
#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
#define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L
#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L
#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L
#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
#define GRBM_STATUS2__TCP_BUSY_MASK 0x02000000L
#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
//GRBM_PWR_CNTL
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
//GRBM_STATUS
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10
#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
#define GRBM_STATUS__GE_BUSY__SHIFT 0x15
#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L
#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
#define GRBM_STATUS__GE_BUSY_MASK 0x00200000L
#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
//GRBM_STATUS_SE0
#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3
#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4
#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5
#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L
#define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L
#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L
#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
//GRBM_STATUS_SE1
#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3
#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4
#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5
#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L
#define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L
#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L
#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
//GRBM_STATUS3
#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5
#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT 0x6
#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7
#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS3__PH_BUSY__SHIFT 0xd
#define GRBM_STATUS3__CH_BUSY__SHIFT 0xe
#define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf
#define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10
#define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c
#define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d
#define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e
#define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f
#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L
#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK 0x00000040L
#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L
#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK 0x00000400L
#define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK 0x00000800L
#define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L
#define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L
#define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L
#define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L
#define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L
#define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L
#define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L
#define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L
//GRBM_SOFT_RESET
#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18
#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L
//GRBM_GFX_CLKEN_CNTL
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
//GRBM_WAIT_IDLE_CLOCKS
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
//GRBM_STATUS_SE2
#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3
#define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4
#define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5
#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L
#define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L
#define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L
#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
//GRBM_STATUS_SE3
#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT 0x3
#define GRBM_STATUS_SE3__TCP_BUSY__SHIFT 0x4
#define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT 0x5
#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE3__UTCL1_BUSY_MASK 0x00000008L
#define GRBM_STATUS_SE3__TCP_BUSY_MASK 0x00000010L
#define GRBM_STATUS_SE3__GL1CC_BUSY_MASK 0x00000020L
#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
//GRBM_PM_CNTL
#define GRBM_PM_CNTL__PM_READY__SHIFT 0x0
#define GRBM_PM_CNTL__PM_START__SHIFT 0x10
#define GRBM_PM_CNTL__PM_READY_MASK 0x00000001L
#define GRBM_PM_CNTL__PM_START_MASK 0x00010000L
//GRBM_READ_ERROR
#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
//GRBM_READ_ERROR2
#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
//GRBM_INT_CNTL
#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
//GRBM_TRAP_OP
#define GRBM_TRAP_OP__RW__SHIFT 0x0
#define GRBM_TRAP_OP__RW_MASK 0x00000001L
//GRBM_TRAP_ADDR
#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
//GRBM_TRAP_ADDR_MSK
#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
//GRBM_TRAP_WD
#define GRBM_TRAP_WD__DATA__SHIFT 0x0
#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
//GRBM_TRAP_WD_MSK
#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
//GRBM_DSM_BYPASS
#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
//GRBM_WRITE_ERROR
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000007E0L
#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
//GRBM_IOV_ERROR
#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
//GRBM_CHIP_REVISION
#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
//GRBM_GFX_CNTL
#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
//GRBM_IH_CREDIT
#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
//GRBM_PWR_CNTL2
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
//GRBM_UTCL2_INVAL_RANGE_START
#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
//GRBM_UTCL2_INVAL_RANGE_END
#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
//GRBM_IOV_READ_ERROR
#define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT 0x2
#define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT 0x14
#define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT 0x1a
#define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT 0x1b
#define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT 0x1f
#define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK 0x000FFFFCL
#define GRBM_IOV_READ_ERROR__IOV_VFID_MASK 0x03F00000L
#define GRBM_IOV_READ_ERROR__IOV_VF_MASK 0x04000000L
#define GRBM_IOV_READ_ERROR__IOV_OP_MASK 0x08000000L
#define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK 0x80000000L
//GRBM_FENCE_RANGE0
#define GRBM_FENCE_RANGE0__START__SHIFT 0x0
#define GRBM_FENCE_RANGE0__END__SHIFT 0x10
#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL
#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L
//GRBM_FENCE_RANGE1
#define GRBM_FENCE_RANGE1__START__SHIFT 0x0
#define GRBM_FENCE_RANGE1__END__SHIFT 0x10
#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL
#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L
//GRBM_NOWHERE
#define GRBM_NOWHERE__DATA__SHIFT 0x0
#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG1
#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG2
#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG3
#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG4
#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG5
#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG6
#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG7
#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
// addressBlock: gc_cpdec
//CP_CPC_STATUS
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf
#define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10
#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11
#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12
#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
#define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L
#define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L
#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L
#define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L
#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
//CP_CPC_BUSY_STAT
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
//CP_CPC_STALLED_STAT1
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L
//CP_CPF_STATUS
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
#define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12
#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13
#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14
#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15
#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16
#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17
#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
#define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L
#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L
#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L
#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L
#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L
#define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L
#define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
//CP_CPF_BUSY_STAT
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9
#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L
#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
//CP_CPF_STALLED_STAT1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc
#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L
#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L
//CP_CPC_BUSY_STAT2
#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L
#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L
#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L
#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L
#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L
#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L
#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L
#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L
#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L
//CP_CPC_GRBM_FREE_COUNT
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
//CP_MEC_CNTL
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16
#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L
#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
//CP_MEC_ME1_HEADER_DUMP
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_MEC_ME2_HEADER_DUMP
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_CPC_SCRATCH_INDEX
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L
//CP_CPC_SCRATCH_DATA
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
//CP_CPF_GRBM_FREE_COUNT
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
//CP_CPF_BUSY_STAT2
#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L
#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L
//CP_CPC_HALT_HYST_COUNT
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
//CP_CE_COMPARE_COUNT
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
//CP_CE_DE_COUNT
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_DE_CE_COUNT
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_DE_LAST_INVAL_COUNT
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
//CP_DE_DE_COUNT
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_STALLED_STAT3
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L
//CP_STALLED_STAT1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
//CP_STALLED_STAT2
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
//CP_BUSY_STAT
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
//CP_STAT
#define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5
#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6
#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
#define CP_STAT__DC_BUSY__SHIFT 0xd
#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
#define CP_STAT__PFP_BUSY__SHIFT 0xf
#define CP_STAT__MEQ_BUSY__SHIFT 0x10
#define CP_STAT__ME_BUSY__SHIFT 0x11
#define CP_STAT__QUERY_BUSY__SHIFT 0x12
#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
#define CP_STAT__DMA_BUSY__SHIFT 0x16
#define CP_STAT__RCIU_BUSY__SHIFT 0x17
#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
#define CP_STAT__GCRIU_BUSY__SHIFT 0x19
#define CP_STAT__CE_BUSY__SHIFT 0x1a
#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
#define CP_STAT__CP_BUSY__SHIFT 0x1f
#define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L
#define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L
#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
#define CP_STAT__DC_BUSY_MASK 0x00002000L
#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
#define CP_STAT__PFP_BUSY_MASK 0x00008000L
#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
#define CP_STAT__ME_BUSY_MASK 0x00020000L
#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
#define CP_STAT__DMA_BUSY_MASK 0x00400000L
#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
#define CP_STAT__GCRIU_BUSY_MASK 0x02000000L
#define CP_STAT__CE_BUSY_MASK 0x04000000L
#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
#define CP_STAT__CP_BUSY_MASK 0x80000000L
//CP_ME_HEADER_DUMP
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_PFP_HEADER_DUMP
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_GRBM_FREE_COUNT
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
//CP_CE_HEADER_DUMP
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_PFP_INSTR_PNTR
#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_ME_INSTR_PNTR
#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_CE_INSTR_PNTR
#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_MEC1_INSTR_PNTR
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_MEC2_INSTR_PNTR
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_CSF_STAT
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
//CP_ME_CNTL
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
//CP_CNTX_STAT
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
//CP_ME_PREEMPTION
#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
//CP_ROQ_THRESHOLDS
#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
//CP_MEQ_STQ_THRESHOLD
#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
//CP_RB2_RPTR
#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB1_RPTR
#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB0_RPTR
#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB_RPTR
#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB_WPTR_DELAY
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
//CP_RB_WPTR_POLL_CNTL
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//CP_ROQ1_THRESHOLDS
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L
//CP_ROQ2_THRESHOLDS
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L
//CP_STQ_THRESHOLDS
#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
//CP_QUEUE_THRESHOLDS
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
//CP_MEQ_THRESHOLDS
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
//CP_ROQ_AVAIL
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L
//CP_STQ_AVAIL
#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
//CP_ROQ2_AVAIL
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL
#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L
//CP_MEQ_AVAIL
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
//CP_CMD_INDEX
#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
//CP_CMD_DATA
#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
//CP_ROQ_RB_STAT
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L
//CP_ROQ_IB1_STAT
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L
//CP_ROQ_IB2_STAT
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L
//CP_STQ_STAT
#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
//CP_STQ_WR_STAT
#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
//CP_MEQ_STAT
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
//CP_CEQ1_AVAIL
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x00000FFFL
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x0FFF0000L
//CP_CEQ2_AVAIL
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
#define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT 0x10
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x00000FFFL
#define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK 0x0FFF0000L
//CP_CE_ROQ_RB_STAT
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x00000FFFL
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x0FFF0000L
//CP_CE_ROQ_IB1_STAT
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x00000FFFL
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x0FFF0000L
//CP_CE_ROQ_IB2_STAT
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x00000FFFL
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x0FFF0000L
//CP_CE_ROQ_DB_STAT
#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT 0x0
#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT 0x10
#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK 0x00000FFFL
#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK 0x0FFF0000L
//CP_ROQ3_THRESHOLDS
#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0
#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa
#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL
#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L
//CP_ROQ_DB_STAT
#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0
#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10
#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL
#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
// addressBlock: gc_padec
//VGT_VTX_VECT_EJECT_REG
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003FFL
//VGT_DMA_DATA_FIFO_DEPTH
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL
//VGT_DMA_REQ_FIFO_DEPTH
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
//VGT_DRAW_INIT_FIFO_DEPTH
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
//VGT_LAST_COPY_STATE
#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
//VGT_CACHE_INVALIDATION
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
//VGT_ESGS_RING_SIZE
#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
//VGT_GSVS_RING_SIZE
#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
//VGT_FIFO_DEPTHS
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x17
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x00400000L
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x1F800000L
//VGT_GS_VERTEX_REUSE
#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
//VGT_MC_LAT_CNTL
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
//IA_UTCL1_STATUS_2
#define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0
#define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1
#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2
#define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3
#define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4
#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5
#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6
#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7
#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8
#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10
#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18
#define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L
#define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L
#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L
#define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L
#define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L
#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L
#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L
#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L
#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L
#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L
#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L
//VGT_CNTL_STATUS
#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
//WD_CNTL_STATUS
#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
//CC_GC_PRIM_CONFIG
#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
//GC_USER_PRIM_CONFIG
#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
//WD_QOS
#define WD_QOS__DRAW_STALL__SHIFT 0x0
#define WD_QOS__DRAW_STALL_MASK 0x00000001L
//WD_UTCL1_CNTL
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L
//WD_UTCL1_STATUS
#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//GE_PC_CNTL
#define GE_PC_CNTL__PC_SIZE__SHIFT 0x0
#define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC__SHIFT 0x10
#define GE_PC_CNTL__PC_SIZE_MASK 0x0000FFFFL
#define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC_MASK 0x00010000L
//IA_UTCL1_CNTL
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L
//IA_UTCL1_STATUS
#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//GE_FAST_CLKS
#define GE_FAST_CLKS__HYSTERESIS__SHIFT 0x0
#define GE_FAST_CLKS__LOCK__SHIFT 0x1e
#define GE_FAST_CLKS__FORCE_FAST_CLK__SHIFT 0x1f
#define GE_FAST_CLKS__HYSTERESIS_MASK 0x3FFFFFFFL
#define GE_FAST_CLKS__LOCK_MASK 0x40000000L
#define GE_FAST_CLKS__FORCE_FAST_CLK_MASK 0x80000000L
//VGT_TF_RING_SIZE
#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
//VGT_SYS_CONFIG
#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
//GE_PRIV_CONTROL
#define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT 0x0
#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1
#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa
#define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK 0x00000001L
#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL
#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L
//GE_STATUS
#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0
#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1
#define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L
#define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L
//VGT_VS_MAX_WAVE_ID
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
//VGT_GS_MAX_WAVE_ID
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
//CC_GC_SHADER_ARRAY_CONFIG_GEN0
#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT 0x10
#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK 0x03FF0000L
//VGT_HS_OFFCHIP_PARAM
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
//GFX_PIPE_CONTROL
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
//VGT_TF_MEMORY_BASE
#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
//CC_GC_SHADER_ARRAY_CONFIG
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L
//GC_USER_SHADER_ARRAY_CONFIG
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L
//VGT_DMA_PRIMITIVE_TYPE
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
//VGT_DMA_CONTROL
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
//VGT_DMA_LS_HS_CONFIG
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
//VGT_STRMOUT_DELAY
#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
//WD_BUF_RESOURCE_1
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
//WD_BUF_RESOURCE_2
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
//VGT_TF_MEMORY_BASE_HI
#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
//PA_CL_CNTL_STATUS
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L
//PA_CL_ENHANCE
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11
#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12
#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13
#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14
#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15
#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x16
#define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID__SHIFT 0x17
#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L
#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L
#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L
#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L
#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L
#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00400000L
#define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID_MASK 0x00800000L
#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
//PA_SU_CNTL_STATUS
#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
//PA_SC_FIFO_DEPTH_CNTL
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_TRAP_SCREEN_HV_LOCK
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_FORCE_EOV_MAX_CNTS
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
//PA_SC_BINNER_EVENT_CNTL_0
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_1
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_2
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_3
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L
//PA_SC_BINNER_TIMEOUT_COUNTER
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
//PA_SC_BINNER_PERF_CNTL_0
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
//PA_SC_BINNER_PERF_CNTL_1
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
//PA_SC_BINNER_PERF_CNTL_2
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
//PA_SC_BINNER_PERF_CNTL_3
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
//PA_SC_ENHANCE_2
#define PA_SC_ENHANCE_2__ECO_SPARE0__SHIFT 0x0
#define PA_SC_ENHANCE_2__ECO_SPARE1__SHIFT 0x1
#define PA_SC_ENHANCE_2__ECO_SPARE2__SHIFT 0x2
#define PA_SC_ENHANCE_2__ECO_SPARE3__SHIFT 0x3
#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4
#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8
#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9
#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa
#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb
#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc
#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe
#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf
#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10
#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT 0x13
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT 0x14
#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15
#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17
#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT 0x18
#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT 0x19
#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a
#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b
#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1e
#define PA_SC_ENHANCE_2__ECO_SPARE0_MASK 0x00000001L
#define PA_SC_ENHANCE_2__ECO_SPARE1_MASK 0x00000002L
#define PA_SC_ENHANCE_2__ECO_SPARE2_MASK 0x00000004L
#define PA_SC_ENHANCE_2__ECO_SPARE3_MASK 0x00000008L
#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L
#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L
#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L
#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L
#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L
#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L
#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L
#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L
#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L
#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK 0x00080000L
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK 0x00100000L
#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L
#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L
#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK 0x01000000L
#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK 0x02000000L
#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L
#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L
#define PA_SC_ENHANCE_2__RSVD_MASK 0xC0000000L
//PA_SC_ENHANCE_INTERNAL
#define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x0
#define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000001L
//PA_SC_BINNER_CNTL_OVERRIDE
#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0
#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa
#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13
#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b
#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c
#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L
#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L
#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L
#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L
//PA_SC_PBB_OVERRIDE_FLAG
#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0
#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1
#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L
#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L
//PA_PH_INTERFACE_FIFO_SIZE
#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0
#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10
#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL
#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L
//PA_PH_ENHANCE
#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0
#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1
#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2
#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4
#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5
#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7
#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9
#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa
#define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L
#define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L
#define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L
#define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L
#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L
#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L
#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L
#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L
//PA_SC_BC_WAVE_BREAK
#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT 0x10
#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L
//PA_SC_FIFO_SIZE
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
//PA_SC_IF_FIFO_SIZE
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
//PA_SC_PKR_WAVE_TABLE_CNTL
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
//PA_SIDEBAND_REQUEST_DELAYS
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
//PA_SC_ENHANCE
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
//PA_SC_ENHANCE_1
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17
#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19
#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a
#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d
#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L
#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L
#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L
#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L
#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L
//PA_SC_DSM_CNTL
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
//PA_SC_TILE_STEERING_CREST_OVERRIDE
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L
// addressBlock: gc_sqdec
//SQ_CONFIG
#define SQ_CONFIG__UNUSED__SHIFT 0x0
#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
#define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT 0xc
#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT 0xd
#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT 0xf
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT 0x1e
#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
#define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK 0x00001000L
#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK 0x00006000L
#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK 0x00018000L
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK 0xC0000000L
//SQC_CONFIG
#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
//LDS_CONFIG
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
//SQ_RANDOM_WAVE_PRI
#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L
//SQG_STATUS
#define SQG_STATUS__REG_BUSY__SHIFT 0x0
#define SQG_STATUS__REG_BUSY_MASK 0x00000001L
//SQ_FIFO_SIZES
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT 0xc
#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe
#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L
#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK 0x00003000L
#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L
#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
//SQ_DSM_CNTL
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
//SQ_DSM_CNTL2
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
//SQ_RUNTIME_CONFIG
#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0
#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L
//SH_MEM_BASES
#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
//SP_CONFIG
#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0
#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2
#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3
#define SP_CONFIG__TRANS_MGCG_OVERRIDE__SHIFT 0x4
#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x5
#define SP_CONFIG__DPMACC_MGCG_OVERRIDE__SHIFT 0x6
#define SP_CONFIG__SMACC_MGCG_OVERRIDE__SHIFT 0x7
#define SP_CONFIG__UNUSED__SHIFT 0x8
#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L
#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L
#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L
#define SP_CONFIG__TRANS_MGCG_OVERRIDE_MASK 0x00000010L
#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000020L
#define SP_CONFIG__DPMACC_MGCG_OVERRIDE_MASK 0x00000040L
#define SP_CONFIG__SMACC_MGCG_OVERRIDE_MASK 0x00000080L
#define SP_CONFIG__UNUSED_MASK 0x00000100L
//SQ_ARB_CONFIG
#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0
#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4
#define SQ_ARB_CONFIG__DISABLE_SECOND_TRY__SHIFT 0x8
#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L
#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L
#define SQ_ARB_CONFIG__DISABLE_SECOND_TRY_MASK 0x00000100L
//SH_MEM_CONFIG
#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2
#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4
#define SH_MEM_CONFIG__RETRY_MODE__SHIFT 0xc
#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe
#define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE__SHIFT 0x10
#define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE__SHIFT 0x11
#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12
#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL
#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x00000070L
#define SH_MEM_CONFIG__RETRY_MODE_MASK 0x00003000L
#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L
#define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE_MASK 0x00010000L
#define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE_MASK 0x00020000L
#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L
//CC_GC_SHADER_RATE_CONFIG
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
//GC_USER_SHADER_RATE_CONFIG
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
//SQ_INTERRUPT_AUTO_MASK
#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
//SQ_INTERRUPT_MSG_CTRL
#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
//SQG_UTCL0_CNTL1
#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
#define SQG_UTCL0_CNTL1__RESERVED__SHIFT 0x10
#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQG_UTCL0_CNTL1__RESERVED_MASK 0x00010000L
#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQG_UTCL0_CNTL2
#define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0
#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
#define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT 0x19
#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
#define SQG_UTCL0_CNTL2__RESERVED__SHIFT 0x1e
#define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQG_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQG_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK 0x02000000L
#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
#define SQG_UTCL0_CNTL2__RESERVED_MASK 0xC0000000L
//SQG_UTCL0_STATUS
#define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3
#define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8
#define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
#define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L
#define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L
//SQG_CONFIG
#define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT 0x0
#define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT 0x4
#define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK 0x0000000FL
#define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK 0x000007F0L
//SQ_SHADER_TBA_LO
#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQ_SHADER_TBA_HI
#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f
#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
#define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L
//SQ_SHADER_TMA_LO
#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQ_SHADER_TMA_HI
#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
//SQ_WATCH0_ADDR_H
#define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0
#define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
//SQ_WATCH0_ADDR_L
#define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6
#define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//SQ_WATCH0_CNTL
#define SQ_WATCH0_CNTL__MASK__SHIFT 0x0
#define SQ_WATCH0_CNTL__VMID__SHIFT 0x18
#define SQ_WATCH0_CNTL__MODE__SHIFT 0x1d
#define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f
#define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
#define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L
#define SQ_WATCH0_CNTL__MODE_MASK 0x60000000L
#define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L
//SQ_WATCH1_ADDR_H
#define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0
#define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
//SQ_WATCH1_ADDR_L
#define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6
#define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//SQ_WATCH1_CNTL
#define SQ_WATCH1_CNTL__MASK__SHIFT 0x0
#define SQ_WATCH1_CNTL__VMID__SHIFT 0x18
#define SQ_WATCH1_CNTL__MODE__SHIFT 0x1d
#define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f
#define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
#define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L
#define SQ_WATCH1_CNTL__MODE_MASK 0x60000000L
#define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L
//SQ_WATCH2_ADDR_H
#define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0
#define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
//SQ_WATCH2_ADDR_L
#define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6
#define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//SQ_WATCH2_CNTL
#define SQ_WATCH2_CNTL__MASK__SHIFT 0x0
#define SQ_WATCH2_CNTL__VMID__SHIFT 0x18
#define SQ_WATCH2_CNTL__MODE__SHIFT 0x1d
#define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f
#define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
#define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L
#define SQ_WATCH2_CNTL__MODE_MASK 0x60000000L
#define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L
//SQ_WATCH3_ADDR_H
#define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0
#define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
//SQ_WATCH3_ADDR_L
#define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6
#define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//SQ_WATCH3_CNTL
#define SQ_WATCH3_CNTL__MASK__SHIFT 0x0
#define SQ_WATCH3_CNTL__VMID__SHIFT 0x18
#define SQ_WATCH3_CNTL__MODE__SHIFT 0x1d
#define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f
#define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
#define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L
#define SQ_WATCH3_CNTL__MODE_MASK 0x60000000L
#define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L
//SQ_THREAD_TRACE_BUF0_BASE
#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0
#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_BUF0_SIZE
#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8
#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL
#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L
//SQ_THREAD_TRACE_BUF1_BASE
#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0
#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_BUF1_SIZE
#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8
#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL
#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L
//SQ_THREAD_TRACE_WPTR
#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0
#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f
#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL
#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L
//SQ_THREAD_TRACE_MASK
#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4
#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9
#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa
#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L
#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L
#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L
#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L
//SQ_THREAD_TRACE_TOKEN_MASK
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10
#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x00000FFFL
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L
#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L
//SQ_THREAD_TRACE_CTRL
#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0
#define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2
#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT 0x3
#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4
#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5
#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6
#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT 0x9
#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xa
#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xb
#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT 0xc
#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd
#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe
#define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13
#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT 0x1e
#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f
#define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L
#define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L
#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK 0x00000008L
#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L
#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L
#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L
#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK 0x00000200L
#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000400L
#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00000800L
#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK 0x00001000L
#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L
#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L
#define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L
#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK 0x40000000L
#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L
//SQ_THREAD_TRACE_STATUS
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc
#define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT 0x18
#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT 0x1a
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT 0x1b
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L
#define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK 0x01000000L
#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK 0x04000000L
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK 0x08000000L
//SQ_THREAD_TRACE_DROPPED_CNTR
#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_GFX_DRAW_CNTR
#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_GFX_MARKER_CNTR
#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_HP3D_DRAW_CNTR
#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_HP3D_MARKER_CNTR
#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_IND_INDEX
#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
#define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5
#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb
#define SQ_IND_INDEX__INDEX__SHIFT 0x10
#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL
#define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L
#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L
#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
//SQ_IND_DATA
#define SQ_IND_DATA__DATA__SHIFT 0x0
#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
//SQ_CMD
#define SQ_CMD__CMD__SHIFT 0x0
#define SQ_CMD__MODE__SHIFT 0x4
#define SQ_CMD__CHECK_VMID__SHIFT 0x7
#define SQ_CMD__DATA__SHIFT 0x8
#define SQ_CMD__WAVE_ID__SHIFT 0x10
#define SQ_CMD__QUEUE_ID__SHIFT 0x18
#define SQ_CMD__VM_ID__SHIFT 0x1c
#define SQ_CMD__CMD_MASK 0x0000000FL
#define SQ_CMD__MODE_MASK 0x00000070L
#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
#define SQ_CMD__DATA_MASK 0x00000F00L
#define SQ_CMD__WAVE_ID_MASK 0x001F0000L
#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
#define SQ_CMD__VM_ID_MASK 0xF0000000L
//SQ_TIME_HI
#define SQ_TIME_HI__TIME__SHIFT 0x0
#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
//SQ_TIME_LO
#define SQ_TIME_LO__TIME__SHIFT 0x0
#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
//SQ_LB_CTR_CTRL
#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
//SQ_LB_DATA0
#define SQ_LB_DATA0__DATA__SHIFT 0x0
#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA1
#define SQ_LB_DATA1__DATA__SHIFT 0x0
#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA2
#define SQ_LB_DATA2__DATA__SHIFT 0x0
#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA3
#define SQ_LB_DATA3__DATA__SHIFT 0x0
#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
//SQ_LB_CTR_SEL0
#define SQ_LB_CTR_SEL0__SEL0__SHIFT 0x0
#define SQ_LB_CTR_SEL0__DIV0__SHIFT 0xf
#define SQ_LB_CTR_SEL0__SEL1__SHIFT 0x10
#define SQ_LB_CTR_SEL0__DIV1__SHIFT 0x1f
#define SQ_LB_CTR_SEL0__SEL0_MASK 0x000000FFL
#define SQ_LB_CTR_SEL0__DIV0_MASK 0x00008000L
#define SQ_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L
#define SQ_LB_CTR_SEL0__DIV1_MASK 0x80000000L
//SQ_LB_CTR_SEL1
#define SQ_LB_CTR_SEL1__SEL2__SHIFT 0x0
#define SQ_LB_CTR_SEL1__DIV2__SHIFT 0xf
#define SQ_LB_CTR_SEL1__SEL3__SHIFT 0x10
#define SQ_LB_CTR_SEL1__DIV3__SHIFT 0x1f
#define SQ_LB_CTR_SEL1__SEL2_MASK 0x000000FFL
#define SQ_LB_CTR_SEL1__DIV2_MASK 0x00008000L
#define SQ_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L
#define SQ_LB_CTR_SEL1__DIV3_MASK 0x80000000L
//SQ_EDC_CNT
#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
//SQ_EDC_FUE_CNTL
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
//SQ_WREXEC_EXEC_HI
#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
//SQ_WREXEC_EXEC_LO
#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQC_ICACHE_UTCL0_CNTL1
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQC_ICACHE_UTCL0_CNTL2
#define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0
#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
#define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
//SQC_DCACHE_UTCL0_CNTL1
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQC_DCACHE_UTCL0_CNTL2
#define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0
#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
#define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
//SQC_ICACHE_UTCL0_STATUS
#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
//SQC_DCACHE_UTCL0_STATUS
#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
//SQC_MISC_CONFIG
#define SQC_MISC_CONFIG__PERFTOKEN_DELAY__SHIFT 0x0
#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5
#define SQC_MISC_CONFIG__PERFTOKEN_DELAY_MASK 0x0000001FL
#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L
// addressBlock: gc_shsdec
//SX_DEBUG_1
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd
#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe
#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf
#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10
#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11
#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x12
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L
#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L
#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L
#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L
#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L
#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFC0000L
//SPI_PS_MAX_WAVE_ID
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
//SPI_START_PHASE
#define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT 0x0
#define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT 0x2
#define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT 0x4
#define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT 0x6
#define SPI_START_PHASE__PC_X_PHASE_SE0_MASK 0x00000003L
#define SPI_START_PHASE__PC_X_PHASE_SE1_MASK 0x0000000CL
#define SPI_START_PHASE__PC_X_PHASE_SE2_MASK 0x00000030L
#define SPI_START_PHASE__PC_X_PHASE_SE3_MASK 0x000000C0L
//SPI_GFX_CNTL
#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
//SPI_USER_ACCUM_VMID_CNTL
#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0
#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL
//SPI_CONFIG_CNTL
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
//SPI_DSM_CNTL
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
//SPI_DSM_CNTL2
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L
//SPI_EDC_CNT
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
//SPI_WAVE_LIMIT_CNTL
#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0
#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2
#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4
#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6
#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L
#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL
#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L
#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L
//SPI_CONFIG_CNTL_2
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
//SPI_CONFIG_CNTL_1
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10
#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15
#define SPI_CONFIG_CNTL_1__RESERVED__SHIFT 0x16
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L
#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L
#define SPI_CONFIG_CNTL_1__RESERVED_MASK 0xFFC00000L
//SPI_WF_LIFETIME_CNTL
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
//SPI_WF_LIFETIME_LIMIT_0
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_1
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_2
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_3
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_4
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_5
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_6
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_7
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_8
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_9
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_0
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_1
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_2
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_3
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_4
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_5
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_6
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_7
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_8
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_9
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_10
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_11
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_12
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_13
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_14
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_15
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_16
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_17
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_18
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_19
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_20
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
//SPI_LB_CTR_CTRL
#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
//SPI_LB_WGP_MASK
#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0
#define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL
//SPI_LB_DATA_REG
#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
//SPI_PG_ENABLE_STATIC_WGP_MASK
#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0
#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL
//SPI_GDS_CREDITS
#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
//SPI_SX_EXPORT_BUFFER_SIZES
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
//SPI_SX_SCOREBOARD_BUFFER_SIZES
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
//SPI_CSQ_WF_ACTIVE_STATUS
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
//SPI_CSQ_WF_ACTIVE_COUNT_0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_1
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_2
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_3
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_4
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_5
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_6
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_7
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
//SPI_LB_DATA_WAVES
#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_HSGS
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_VSPS
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT 0x0
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT 0x10
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK 0x0000FFFFL
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK 0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_CS
#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0
#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0xFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_LO
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_HI
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
//SPI_P0_TRAP_SCREEN_PSMA_LO
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSMA_HI
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
//SPI_P0_TRAP_SCREEN_GPR_MIN
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
//SPI_P1_TRAP_SCREEN_PSBA_LO
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSBA_HI
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
//SPI_P1_TRAP_SCREEN_PSMA_LO
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSMA_HI
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
//SPI_P1_TRAP_SCREEN_GPR_MIN
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
// addressBlock: gc_tpdec
//TD_CNTL
#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
#define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP__SHIFT 0x3
#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
#define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP__SHIFT 0x6
#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16
#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
#define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19
#define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a
#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
#define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP_MASK 0x00000008L
#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
#define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP_MASK 0x00000040L
#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L
#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
#define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L
#define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0x7C000000L
//TD_STATUS
#define TD_STATUS__BUSY__SHIFT 0x1f
#define TD_STATUS__BUSY_MASK 0x80000000L
//TD_POWER_CNTL
#define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE__SHIFT 0x0
#define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE__SHIFT 0x1
#define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x2
#define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY__SHIFT 0x5
#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x8
#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x9
#define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE_MASK 0x00000001L
#define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE_MASK 0x00000002L
#define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x0000001CL
#define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY_MASK 0x000000E0L
#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000100L
#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000200L
//TD_DSM_CNTL
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
//TD_DSM_CNTL2
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
//TD_SCRATCH
#define TD_SCRATCH__SCRATCH__SHIFT 0x0
#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
//TA_POWER_CNTL
#define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x0
#define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE__SHIFT 0x3
#define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY__SHIFT 0x10
#define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE__SHIFT 0x13
#define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x00000007L
#define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE_MASK 0x00000008L
#define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY_MASK 0x00070000L
#define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE_MASK 0x00080000L
//TA_CNTL
#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
//TA_CNTL_AUX
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
#define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4
#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8
#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9
#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
#define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L
#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L
#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L
#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
//TA_RESERVED_010C
#define TA_RESERVED_010C__Unused__SHIFT 0x0
#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
//TA_STATUS
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
#define TA_STATUS__IN_BUSY__SHIFT 0x18
#define TA_STATUS__FG_BUSY__SHIFT 0x19
#define TA_STATUS__LA_BUSY__SHIFT 0x1a
#define TA_STATUS__FL_BUSY__SHIFT 0x1b
#define TA_STATUS__TA_BUSY__SHIFT 0x1c
#define TA_STATUS__FA_BUSY__SHIFT 0x1d
#define TA_STATUS__AL_BUSY__SHIFT 0x1e
#define TA_STATUS__BUSY__SHIFT 0x1f
#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
#define TA_STATUS__IN_BUSY_MASK 0x01000000L
#define TA_STATUS__FG_BUSY_MASK 0x02000000L
#define TA_STATUS__LA_BUSY_MASK 0x04000000L
#define TA_STATUS__FL_BUSY_MASK 0x08000000L
#define TA_STATUS__TA_BUSY_MASK 0x10000000L
#define TA_STATUS__FA_BUSY_MASK 0x20000000L
#define TA_STATUS__AL_BUSY_MASK 0x40000000L
#define TA_STATUS__BUSY_MASK 0x80000000L
//TA_SCRATCH
#define TA_SCRATCH__SCRATCH__SHIFT 0x0
#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
// addressBlock: gc_gdsdec
//GDS_CONFIG
#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
#define GDS_CONFIG__UNUSED__SHIFT 0x9
#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
#define GDS_CONFIG__UNUSED_MASK 0xFFFFFE00L
//GDS_CNTL_STATUS
#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
#define GDS_CNTL_STATUS__UNUSED__SHIFT 0xf
#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
#define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFF8000L
//GDS_ENHANCE
#define GDS_ENHANCE__MISC__SHIFT 0x0
#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
#define GDS_ENHANCE__UNUSED__SHIFT 0x12
#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
#define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L
//GDS_PROTECTION_FAULT
#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
//GDS_VM_PROTECTION_FAULT
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
#define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6
#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
#define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc
#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
#define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L
#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
#define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L
#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
//GDS_EDC_CNT
#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
//GDS_EDC_GRBM_CNT
#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
//GDS_EDC_OA_DED
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
//GDS_DSM_CNTL
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
//GDS_EDC_OA_PHY_CNT
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
//GDS_EDC_OA_PIPE_CNT
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
//GDS_DSM_CNTL2
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
//GDS_WD_GDS_CSB
#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
// addressBlock: gc_rbdec
//DB_DEBUG
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
//DB_DEBUG2
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT 0x14
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT 0x16
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT 0x17
#define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18
#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a
#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK 0x00300000L
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK 0x00400000L
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK 0x00800000L
#define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L
#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L
#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
//DB_DEBUG3
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1
#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
#define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e
#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L
#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
#define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L
#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L
//DB_DEBUG4
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0x5
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf
#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT 0x11
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12
#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13
#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT 0x14
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT 0x17
#define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b
#define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT 0x1d
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e
#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT 0x1f
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00000020L
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L
#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK 0x00020000L
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L
#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L
#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK 0x00100000L
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK 0x00800000L
#define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L
#define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK 0x20000000L
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L
#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK 0x80000000L
//DB_ETILE_STUTTER_CONTROL
#define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
#define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
#define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
#define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
//DB_LTILE_STUTTER_CONTROL
#define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
#define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
#define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
#define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
//DB_EQUAD_STUTTER_CONTROL
#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
//DB_LQUAD_STUTTER_CONTROL
#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
//DB_CREDIT_LIMIT
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
//DB_WATERMARKS
#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8
#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18
#define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL
#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L
#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L
//DB_SUBTILE_CONTROL
#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
//DB_FREE_CACHELINES
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8
#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L
#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L
//DB_FIFO_DEPTH1
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8
#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10
#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L
#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L
#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L
//DB_FIFO_DEPTH2
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
//DB_LAST_OF_BURST_CONFIG
#define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0
#define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb
#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x12
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x13
#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x14
#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x15
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x16
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT 0x17
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT 0x18
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN__SHIFT 0x19
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x1a
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1b
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT 0x1c
#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1d
#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e
#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f
#define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL
#define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0003F800L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00040000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00080000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00100000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00200000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00400000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK 0x00800000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK 0x01000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN_MASK 0x02000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x04000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x08000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK 0x10000000L
#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x20000000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L
#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L
//DB_RING_CONTROL
#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
//DB_MEM_ARB_WATERMARKS
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
//DB_FIFO_DEPTH3
#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18
#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL
#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L
//DB_RMI_BC_GL2_CACHE_CONTROL
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4
#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14
#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT 0x1f
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L
#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK 0x80000000L
//DB_EXCEPTION_CONTROL
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4
#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A__SHIFT 0x5
#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8
#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B__SHIFT 0xc
#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L
#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A_MASK 0x000000E0L
#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L
#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B_MASK 0x00FFF000L
#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L
//DB_DFSM_CONFIG
#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
#define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT 0x4
#define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT 0x10
#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT 0x18
#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
#define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK 0x00003FF0L
#define DB_DFSM_CONFIG__CAM_WATERMARK_MASK 0x00FF0000L
#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK 0xFF000000L
//DB_DFSM_TILES_IN_FLIGHT
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
//DB_DFSM_PRIMS_IN_FLIGHT
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
//DB_DFSM_WATCHDOG
#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
//DB_DFSM_FLUSH_ENABLE
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000007FFL
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
//DB_DFSM_FLUSH_AUX_EVENT
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
//DB_FGCG_SRAMS_CLK_CTRL
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L
//DB_FGCG_INTERFACES_CLK_CTRL
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT 0x1
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT 0x2
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK 0x00000002L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK 0x00000004L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L
//CC_RB_REDUNDANCY
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
//CC_RB_BACKEND_DISABLE
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
//GB_ADDR_CONFIG
#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
//GB_BACKEND_MAP
#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
//GB_GPU_ID
#define GB_GPU_ID__GPU_ID__SHIFT 0x0
#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
//CC_RB_DAISY_CHAIN
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
//GB_ADDR_CONFIG_READ
#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
//GB_TILE_MODE0
#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE1
#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE2
#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE3
#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE4
#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE5
#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE6
#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE7
#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE8
#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE9
#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE10
#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE11
#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE12
#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE13
#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE14
#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE15
#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE16
#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE17
#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE18
#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE19
#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE20
#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE21
#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE22
#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE23
#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE24
#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE25
#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE26
#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE27
#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE28
#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE29
#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE30
#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE31
#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
//GB_MACROTILE_MODE0
#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE1
#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE2
#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE3
#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE4
#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE5
#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE6
#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE7
#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE8
#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE9
#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE10
#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE11
#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE12
#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE13
#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE14
#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE15
#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
//CB_HW_CONTROL_4
#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x0
#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x3
#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT 0x5
#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT 0x6
#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT 0x7
#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT 0x8
#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT 0x9
#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT 0xa
#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT 0xb
#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT 0xc
#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT 0xd
#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT 0xe
#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0xf
#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT 0x10
#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT 0x11
#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT 0x16
#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT 0x17
#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT 0x18
#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000007L
#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000018L
#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK 0x00000020L
#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK 0x00000040L
#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK 0x00000080L
#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK 0x00000100L
#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK 0x00000200L
#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK 0x00000400L
#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK 0x00000800L
#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK 0x00001000L
#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK 0x00002000L
#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK 0x00004000L
#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00008000L
#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK 0x00010000L
#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK 0x003E0000L
#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK 0x00400000L
#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK 0x00800000L
#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK 0xFF000000L
//CB_HW_CONTROL_3
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x1e
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT 0x1f
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK 0x40000000L
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK 0x80000000L
//CB_HW_CONTROL
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
//CB_HW_CONTROL_1
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
//CB_HW_CONTROL_2
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1e
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x3F000000L
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xC0000000L
//CB_DCC_CONFIG
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1a
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFC000000L
//CB_HW_MEM_ARBITER_RD
#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
//CB_HW_MEM_ARBITER_WR
#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
//CB_RMI_BC_GL2_CACHE_CONTROL
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16
#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT 0x1f
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK 0x80000000L
//CB_STUTTER_CONTROL_CMASK_RDLAT
#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT 0x0
#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT 0x8
#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK 0x000000FFL
#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L
//CB_STUTTER_CONTROL_FMASK_RDLAT
#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT 0x0
#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT 0x8
#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK 0x000000FFL
#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L
//CB_STUTTER_CONTROL_COLOR_RDLAT
#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT 0x0
#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT 0x8
#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK 0x000000FFL
#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK 0x0000FF00L
//CB_CACHE_EVICT_POINTS
#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT 0x8
#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10
#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18
#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK 0x000000FFL
#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK 0x0000FF00L
#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L
#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L
//GC_USER_RB_REDUNDANCY
#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
//GC_USER_RB_BACKEND_DISABLE
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
// addressBlock: gc_gceadec2
//GCEA_SDP_VCD_RESERVE1
#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
//GCEA_SDP_REQ_CNTL
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
//GCEA_MISC
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
//GCEA_LATENCY_SAMPLING
#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
//GCEA_PERFCOUNTER_LO
#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
//GCEA_PERFCOUNTER_HI
#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
//GCEA_PERFCOUNTER0_CFG
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//GCEA_PERFCOUNTER1_CFG
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//GCEA_PERFCOUNTER_RSLT_CNTL
#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
//GCEA_EDC_CNT
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
//GCEA_EDC_CNT2
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
//GCEA_DSM_CNTL
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
//GCEA_DSM_CNTLA
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
//GCEA_DSM_CNTLB
//GCEA_DSM_CNTL2
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
//GCEA_DSM_CNTL2A
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
//GCEA_DSM_CNTL2B
//GCEA_GL2C_XBR_CREDITS
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
//GCEA_GL2C_XBR_MAXBURST
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
#define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
#define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
#define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
#define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L
//GCEA_PROBE_CNTL
#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
//GCEA_PROBE_MAP
#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0
#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1
#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2
#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3
#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4
#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5
#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6
#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7
#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8
#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9
#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa
#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb
#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc
#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd
#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe
#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf
#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L
#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L
#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L
#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L
#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L
#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L
#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L
#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L
#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L
#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L
#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L
#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L
#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L
#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L
#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L
#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L
#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
//GCEA_ERR_STATUS
#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd
#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
//GCEA_MISC2
#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
// addressBlock: gc_spipdec2
//SPI_PQEV_CTRL
#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0
#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa
#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10
#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL
#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L
#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L
//SPI_SYS_COMPUTE
#define SPI_SYS_COMPUTE__PIPE__SHIFT 0x0
#define SPI_SYS_COMPUTE__PIPE_MASK 0x000000FFL
//SPI_SYS_WIF_CNTL
#define SPI_SYS_WIF_CNTL__THRESHOLD__SHIFT 0x0
#define SPI_SYS_WIF_CNTL__THRESHOLD_MASK 0x000000FFL
// addressBlock: gc_gceadec3
//GCEA_DRAM_BANK_ARB
#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x8
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xe
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE__SHIFT 0xf
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE__SHIFT 0x11
#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000000FEL
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00003F00L
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00004000L
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE_MASK 0x00018000L
#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE_MASK 0x00060000L
//GCEA_DRAM_BANK_ARB_RFSH
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL__SHIFT 0x0
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE__SHIFT 0xc
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE__SHIFT 0x15
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB__SHIFT 0x16
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL_MASK 0x00000FFFL
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE_MASK 0x001FF000L
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE_MASK 0x00200000L
#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB_MASK 0x00400000L
//GCEA_SDP_BACKDOOR_CMDCREDITS0
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
//GCEA_SDP_BACKDOOR_CMDCREDITS1
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
//GCEA_SDP_BACKDOOR_DATACREDITS0
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
//GCEA_SDP_BACKDOOR_DATACREDITS1
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
//GCEA_SDP_BACKDOOR_MISCCREDITS
#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17
#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
//GCEA_ADDRDECDRAM_ADDR_HASH_PACH
#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE__SHIFT 0x0
#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR__SHIFT 0x1
#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE_MASK 0x00000001L
#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR_MASK 0xFFFFFFFEL
//GCEA_RRET_MEM_RESERVE
#define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0
#define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4
#define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8
#define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc
#define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10
#define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14
#define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18
#define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c
#define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL
#define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L
#define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L
#define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L
#define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L
#define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L
#define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L
#define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L
//GCEA_ADDRDEC_SELECT
#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
#define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14
#define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15
#define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16
#define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17
#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
#define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L
#define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L
#define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L
#define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L
//GCEA_SDP_ENABLE
#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
// addressBlock: gc_rmi_rmidec
//RMI_GENERAL_CNTL
#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
//RMI_GENERAL_CNTL1
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xc
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xd
#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe
#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00002000L
#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L
#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L
//RMI_GENERAL_STATUS
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
//RMI_SUBBLOCK_STATUS0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
//RMI_SUBBLOCK_STATUS1
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
//RMI_SUBBLOCK_STATUS2
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
//RMI_SUBBLOCK_STATUS3
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
//RMI_XBAR_CONFIG
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
//RMI_PROBE_POP_LOGIC_CNTL
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
//RMI_UTC_XNACK_N_MISC_CNTL
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
//RMI_DEMUX_CNTL
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
//RMI_UTCL1_CNTL1
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//RMI_UTCL1_CNTL2
#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d
#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L
//RMI_TCIW_FORMATTER0_CNTL
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
//RMI_TCIW_FORMATTER1_CNTL
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
//RMI_SCOREBOARD_CNTL
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
//RMI_SCOREBOARD_STATUS0
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L
//RMI_SCOREBOARD_STATUS1
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
//RMI_SCOREBOARD_STATUS2
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
//RMI_XBAR_ARBITER_CONFIG
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
//RMI_XBAR_ARBITER_CONFIG_1
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
//RMI_CLOCK_CNTRL
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
//RMI_UTCL1_STATUS
#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
//RMI_RB_GLX_CID_MAP
#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0
#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4
#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8
#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc
#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10
#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14
#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18
#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c
#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL
#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L
#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L
#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L
#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L
#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L
#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L
#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L
//RMI_SPARE
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1
#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2
#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3
#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4
#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5
#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8
#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9
#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa
#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb
#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc
#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd
#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe
#define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf
#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L
#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L
#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L
#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L
#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L
#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L
#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L
#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L
#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L
#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L
#define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L
#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L
#define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L
#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L
//RMI_SPARE_1
#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8
#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L
#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
//RMI_SPARE_2
#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
//CC_RMI_REDUNDANCY
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2
#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3
#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L
#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L
#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L
//GC_USER_RMI_REDUNDANCY
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2
#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3
#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L
#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L
#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L
// addressBlock: gc_pmmdec
//PMM_GENERAL_CNTL
#define PMM_GENERAL_CNTL__PMM_MODE__SHIFT 0x0
#define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT 0x1
#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT 0x2
#define PMM_GENERAL_CNTL__PMM_MODE_MASK 0x00000001L
#define PMM_GENERAL_CNTL__PMM_DISABLE_MASK 0x00000002L
#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK 0x00000004L
//GCR_PIO_CNTL
#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0
#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2
#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3
#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10
#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e
#define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f
#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L
#define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L
#define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L
#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L
#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L
#define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L
//GCR_PIO_DATA
#define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0
#define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL
//GCR_GENERAL_CNTL
#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0
#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1
#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2
#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3
#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4
#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6
#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7
#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8
#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9
#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa
#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd
#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe
#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf
#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14
#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L
#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L
#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L
#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L
#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L
#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L
#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L
#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L
#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L
#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L
#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L
#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L
#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L
#define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L
//GCR_TARGET_DISABLE
#define GCR_TARGET_DISABLE__DISABLE_SA0_PHY__SHIFT 0x0
#define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT__SHIFT 0x1
#define GCR_TARGET_DISABLE__DISABLE_SA1_PHY__SHIFT 0x2
#define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT__SHIFT 0x3
#define GCR_TARGET_DISABLE__DISABLE_SA2_PHY__SHIFT 0x4
#define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT__SHIFT 0x5
#define GCR_TARGET_DISABLE__DISABLE_SA3_PHY__SHIFT 0x6
#define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT__SHIFT 0x7
#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x8
#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x9
#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa
#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0xb
#define GCR_TARGET_DISABLE__DISABLE_SA0_PHY_MASK 0x00000001L
#define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT_MASK 0x00000002L
#define GCR_TARGET_DISABLE__DISABLE_SA1_PHY_MASK 0x00000004L
#define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT_MASK 0x00000008L
#define GCR_TARGET_DISABLE__DISABLE_SA2_PHY_MASK 0x00000010L
#define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT_MASK 0x00000020L
#define GCR_TARGET_DISABLE__DISABLE_SA3_PHY_MASK 0x00000040L
#define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT_MASK 0x00000080L
#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000100L
#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000200L
#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000400L
#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000800L
//GCR_CMD_STATUS
#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0
#define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x14
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18
#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c
#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e
#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f
#define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL
#define GCR_CMD_STATUS__GCR_SRC_MASK 0x00700000L
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L
#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L
#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L
#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L
//GCR_SPARE
#define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1
#define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2
#define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3
#define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4
#define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5
#define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6
#define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7
#define GCR_SPARE__SPARE_BIT_8_0__SHIFT 0x8
#define GCR_SPARE__SPARE_BIT_31_16__SHIFT 0x10
#define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L
#define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L
#define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L
#define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L
#define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L
#define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L
#define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L
#define GCR_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
#define GCR_SPARE__SPARE_BIT_31_16_MASK 0xFFFF0000L
// addressBlock: gc_utcl1dec
//UTCL1_CTRL
#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT 0x0
#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT 0x1
#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x2
#define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT 0x3
#define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT 0x4
#define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT 0x5
#define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT 0x6
#define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT 0x7
#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT 0x8
#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x9
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT 0xa
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0xb
#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xc
#define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT 0xd
#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0xe
#define UTCL1_CTRL__RESERVED__SHIFT 0xf
#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT 0x12
#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT 0x13
#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT 0x14
#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x15
#define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x16
#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x17
#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT 0x18
#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1a
#define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE__SHIFT 0x1c
#define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE__SHIFT 0x1e
#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK 0x00000001L
#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK 0x00000002L
#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000004L
#define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK 0x00000008L
#define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK 0x00000010L
#define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK 0x00000020L
#define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK 0x00000040L
#define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK 0x00000080L
#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK 0x00000100L
#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000200L
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK 0x00000400L
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000800L
#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00001000L
#define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK 0x00002000L
#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00004000L
#define UTCL1_CTRL__RESERVED_MASK 0x00038000L
#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK 0x00040000L
#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK 0x00080000L
#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK 0x00100000L
#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00200000L
#define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00400000L
#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x00800000L
#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK 0x03000000L
#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK 0x0C000000L
#define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE_MASK 0x30000000L
#define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE_MASK 0xC0000000L
//UTCL1_ALOG
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3
#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4
#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6
#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa
#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc
#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf
#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10
#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L
#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L
#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L
#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L
#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L
#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L
#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L
#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L
//UTCL1_UTCL0_INVREQ_DISABLE
#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0
#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0x01FFFFFFL
//GCRD_SA_TARGETS_DISABLE
#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT 0x0
#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK 0x0007FFFFL
// addressBlock: gc_gcatcl2dec
//GC_ATC_L2_CNTL
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
#define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
#define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
//GC_ATC_L2_CNTL2
#define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
#define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
//GC_ATC_L2_CACHE_DATA0
#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
#define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18
#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL
#define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L
//GC_ATC_L2_CACHE_DATA1
#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
//GC_ATC_L2_CACHE_DATA2
#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
//GC_ATC_L2_CNTL3
#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9
#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0xc
#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L
#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x00001000L
//GC_ATC_L2_STATUS
#define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0
#define GC_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
#define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L
#define GC_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
//GC_ATC_L2_STATUS2
#define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
#define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
#define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
#define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
//GC_ATC_L2_MISC_CG
#define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
#define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
#define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
#define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
//GC_ATC_L2_MEM_POWER_LS
#define GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
#define GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
#define GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
#define GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
//GC_ATC_L2_CGTT_CLK_CTRL
#define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
#define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
//GC_ATC_L2_SDPPORT_CTRL
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L
#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L
// addressBlock: gc_gcvml2pfdec
//GCVM_L2_CNTL
#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
//GCVM_L2_CNTL2
#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
//GCVM_L2_CNTL3
#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
#define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
//GCVM_L2_STATUS
#define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0
#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
#define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L
#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
//GCVM_DUMMY_PAGE_FAULT_CNTL
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32
#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32
#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
//GCVM_INVALIDATE_CNTL
#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0
#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8
#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL
#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L
//GCVM_L2_PROTECTION_FAULT_CNTL
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
//GCVM_L2_PROTECTION_FAULT_CNTL2
#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
//GCVM_L2_PROTECTION_FAULT_MM_CNTL3
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_MM_CNTL4
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_STATUS
#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
#define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
#define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
#define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
#define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
#define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L
//GCVM_L2_PROTECTION_FAULT_ADDR_LO32
#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_ADDR_HI32
#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
//GCVM_L2_CNTL4
#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
//GCVM_L2_MM_GROUP_RT_CLASSES
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
//GCVM_L2_BANK_SELECT_RESERVED_CID
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
//GCVM_L2_BANK_SELECT_RESERVED_CID2
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
//GCVM_L2_CACHE_PARITY_CNTL
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
//GCVM_L2_CGTT_CLK_CTRL
#define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
#define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
#define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
#define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
//GCVM_L2_CNTL5
#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5
#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L
//GCVM_L2_GCR_CNTL
#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0
#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1
#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L
#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL
//GCVML2_WALKER_MACRO_THROTTLE_TIME
#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0
#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT
#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
//GCVML2_WALKER_MICRO_THROTTLE_TIME
#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0
#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT
#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
// addressBlock: gc_gcvml2vcdec
//GCVM_CONTEXT0_CNTL
#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT1_CNTL
#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT2_CNTL
#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT3_CNTL
#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT4_CNTL
#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT5_CNTL
#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT6_CNTL
#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT7_CNTL
#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT8_CNTL
#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT9_CNTL
#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT10_CNTL
#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT11_CNTL
#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT12_CNTL
#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT13_CNTL
#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT14_CNTL
#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXT15_CNTL
#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//GCVM_CONTEXTS_DISABLE
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
//GCVM_INVALIDATE_ENG0_SEM
#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG1_SEM
#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG2_SEM
#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG3_SEM
#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG4_SEM
#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG5_SEM
#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG6_SEM
#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG7_SEM
#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG8_SEM
#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG9_SEM
#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG10_SEM
#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG11_SEM
#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG12_SEM
#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG13_SEM
#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG14_SEM
#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG15_SEM
#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG16_SEM
#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG17_SEM
#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
//GCVM_INVALIDATE_ENG0_REQ
#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG1_REQ
#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG2_REQ
#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG3_REQ
#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG4_REQ
#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG5_REQ
#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG6_REQ
#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG7_REQ
#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG8_REQ
#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG9_REQ
#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG10_REQ
#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG11_REQ
#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG12_REQ
#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG13_REQ
#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG14_REQ
#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG15_REQ
#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG16_REQ
#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG17_REQ
#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
//GCVM_INVALIDATE_ENG0_ACK
#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG1_ACK
#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG2_ACK
#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG3_ACK
#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG4_ACK
#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG5_ACK
#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG6_ACK
#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG7_ACK
#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG8_ACK
#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG9_ACK
#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG10_ACK
#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG11_ACK
#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG12_ACK
#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG13_ACK
#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG14_ACK
#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG15_ACK
#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG16_ACK
#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG17_ACK
#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
// addressBlock: gc_gcvmsharedpfdec
//GCMC_VM_NB_MMIOBASE
#define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
#define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
//GCMC_VM_NB_MMIOLIMIT
#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
//GCMC_VM_NB_PCI_CTRL
#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
//GCMC_VM_NB_PCI_ARB
#define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
#define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
//GCMC_VM_NB_TOP_OF_DRAM_SLOT1
#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
//GCMC_VM_NB_LOWER_TOP_OF_DRAM2
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
//GCMC_VM_NB_UPPER_TOP_OF_DRAM2
#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
//GCMC_VM_FB_OFFSET
#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
//GCMC_VM_STEERING
#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
//GCMC_SHARED_VIRT_RESET_REQ
#define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
#define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
#define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
#define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
//GCMC_MEM_POWER_LS
#define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
#define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
#define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
#define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
//GCMC_VM_APT_CNTL
#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
//GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
//GCMC_VM_LOCAL_HBM_ADDRESS_START
#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
//GCMC_VM_LOCAL_HBM_ADDRESS_END
#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
//GCMC_SHARED_VIRT_RESET_REQ2
#define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0
#define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L
// addressBlock: gc_gcvmsharedvcdec
//GCMC_VM_FB_LOCATION_BASE
#define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
#define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
//GCMC_VM_FB_LOCATION_TOP
#define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
#define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
//GCMC_VM_AGP_TOP
#define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
#define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
//GCMC_VM_AGP_BOT
#define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
#define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
//GCMC_VM_AGP_BASE
#define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
#define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
//GCMC_VM_MX_L1_TLB_CNTL
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L
// addressBlock: gc_gceadec
//GCEA_DRAM_RD_CLI2GRP_MAP0
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
//GCEA_DRAM_RD_CLI2GRP_MAP1
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
//GCEA_DRAM_WR_CLI2GRP_MAP0
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
//GCEA_DRAM_WR_CLI2GRP_MAP1
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
//GCEA_DRAM_RD_GRP2VC_MAP
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
//GCEA_DRAM_WR_GRP2VC_MAP
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
//GCEA_DRAM_RD_LAZY
#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
//GCEA_DRAM_WR_LAZY
#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
//GCEA_DRAM_RD_CAM_CNTL
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
//GCEA_DRAM_WR_CAM_CNTL
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
//GCEA_DRAM_PAGE_BURST
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
//GCEA_DRAM_RD_PRI_AGE
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
//GCEA_DRAM_WR_PRI_AGE
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
//GCEA_DRAM_RD_PRI_QUEUING
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
//GCEA_DRAM_WR_PRI_QUEUING
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
//GCEA_DRAM_RD_PRI_FIXED
#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
//GCEA_DRAM_WR_PRI_FIXED
#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
//GCEA_DRAM_RD_PRI_URGENCY
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
//GCEA_DRAM_WR_PRI_URGENCY
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
//GCEA_DRAM_RD_PRI_QUANT_PRI1
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_DRAM_RD_PRI_QUANT_PRI2
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_DRAM_RD_PRI_QUANT_PRI3
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI1
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI2
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI3
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
//GCEA_ADDRNORM_BASE_ADDR0
#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
//GCEA_ADDRNORM_LIMIT_ADDR0
#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
//GCEA_ADDRNORM_BASE_ADDR1
#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
//GCEA_ADDRNORM_LIMIT_ADDR1
#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
//GCEA_ADDRNORM_OFFSET_ADDR1
#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14