commit 4df3562a710e2b155309ce701c55af3ead77866d
author Braden Kell <bradenkell@google.com> Wed Jan 05 21:13:03 2022 +0000
committer Braden Kell <bradenkell@google.com> Mon Jan 10 22:29:12 2022 +0000
tree aa929570ef78e2c68e949ac5ca1efcebe00b1dfb
parent e200aa78442c4e2982bd4024f7940fc21448b236

[sherlock][spi] Switch to 666 MHz core clock/1.3 MHz bus clock

Also use the enhanced clock mode, and set the divider accordingly.

Test: ot driver tests pass
Change-Id: Ibbd4999b6136d577478eb0fcf128b9d295ed10db

src/devices/board/drivers/sherlock/sherlock-spi.cc

diff --git a/src/devices/board/drivers/sherlock/sherlock-spi.cc b/src/devices/board/drivers/sherlock/sherlock-spi.cc
index 69e9ac2..d1fde9f 100644
--- a/src/devices/board/drivers/sherlock/sherlock-spi.cc
+++ b/src/devices/board/drivers/sherlock/sherlock-spi.cc
@@ -18,7 +18,7 @@
 #include "src/devices/lib/fidl-metadata/spi.h"
 
 #define HHI_SPICC_CLK_CNTL (0xf7 * 4)
-#define spicc_0_clk_sel_fclk_div5 (5 << 7)
+#define spicc_0_clk_sel_fclk_div3 (3 << 7)
 #define spicc_0_clk_en (1 << 6)
 #define spicc_0_clk_div(x) ((x)-1)
 
@@ -55,9 +55,9 @@
     .period = 0,
     .bus_id = SHERLOCK_SPICC0,
     .cs_count = 1,
-    .cs = {0},                          // index into fragments list
-    .clock_divider_register_value = 0,  // SCLK = core clock / 4 = 10 MHz
-    .use_enhanced_clock_mode = false,
+    .cs = {0},                                       // index into fragments list
+    .clock_divider_register_value = (512 >> 1) - 1,  // SCLK = core clock / 512 = ~1.3 MHz
+    .use_enhanced_clock_mode = true,
 };
 
 static pbus_dev_t spi_dev = []() {
@@ -142,8 +142,8 @@
       return status;
     }
 
-    // SPICC0 clock enable
-    buf->Write32(spicc_0_clk_sel_fclk_div5 | spicc_0_clk_en | spicc_0_clk_div(10),
+    // SPICC0 clock enable (666 MHz)
+    buf->Write32(spicc_0_clk_sel_fclk_div3 | spicc_0_clk_en | spicc_0_clk_div(1),
                  HHI_SPICC_CLK_CNTL);
   }