| commit | 324ba5d008cf01030643dedfbb76e34d1e9cb409 | [log] [tgz] |
|---|---|---|
| author | Travis Geiselbrecht <travisg@google.com> | Tue Apr 04 09:33:10 2023 +0000 |
| committer | CQ Bot <fuchsia-internal-scoped@luci-project-accounts.iam.gserviceaccount.com> | Tue Apr 04 09:33:10 2023 +0000 |
| tree | 44152d141dc82d888ee324d467c3f419353994f0 | |
| parent | d07b6758eb8f4816da279cbd9a5b7e4967bcc1df [diff] |
[kernel][riscv] fixups to the riscv MMU code RISC-V kernel fixup patch 2/12 Add logic after the initial port: -Add ActiveSinceLastCheck logic (copied from arm64 code) -Add todos for DisableUpdates and checking logic Bug: 122873 Change-Id: I17183be3db2a426ffe9ee69aaeed9a3cb12429f1 Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/822189 Reviewed-by: Roland McGrath <mcgrathr@google.com> Commit-Queue: Auto-Submit <auto-submit@fuchsia-infra.iam.gserviceaccount.com> Fuchsia-Auto-Submit: Travis Geiselbrecht <travisg@google.com>
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