| /****************************************************************************** |
| * |
| * Copyright(c) 2013 - 2015 Intel Corporation. All rights reserved. |
| * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
| * Copyright (C) 2018 Intel Corporation |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in |
| * the documentation and/or other materials provided with the |
| * distribution. |
| * * Neither the name Intel Corporation nor the names of its |
| * contributors may be used to endorse or promote products derived |
| * from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| *****************************************************************************/ |
| #ifndef SRC_CONNECTIVITY_WLAN_DRIVERS_THIRD_PARTY_INTEL_IWLWIFI_IWL_DBG_CFG_H_ |
| #define SRC_CONNECTIVITY_WLAN_DRIVERS_THIRD_PARTY_INTEL_IWLWIFI_IWL_DBG_CFG_H_ |
| |
| /* |
| * with DBG_CFG_REINCLUDE set this file should contain nothing |
| * but IWL_DBG_CFG() macro invocations so it can be used in |
| * the C file to generate more code (e.g. for debugfs and the |
| * struct initialization with default values) |
| */ |
| #ifndef DBG_CFG_REINCLUDE |
| #include <linux/types.h> |
| |
| struct iwl_dbg_cfg_bin { |
| const void* data; |
| unsigned int len; |
| }; |
| |
| struct iwl_dbg_cfg { |
| bool loaded; |
| |
| #define IWL_DBG_CFG(type, name) type name; |
| #define IWL_DBG_CFG_NODEF(type, name) type name; |
| #define IWL_DBG_CFG_BIN(name) struct iwl_dbg_cfg_bin name; |
| #define IWL_DBG_CFG_STR(name) const char* name; |
| #define IWL_DBG_CFG_BINA(name, max) \ |
| struct iwl_dbg_cfg_bin name[max]; \ |
| int n_##name; |
| #define IWL_DBG_CFG_RANGE(type, name, min, max) IWL_DBG_CFG(type, name) |
| #define IWL_MOD_PARAM(type, name) /* do nothing */ |
| #define IWL_MVM_MOD_PARAM(type, name) \ |
| type mvm_##name; \ |
| bool __mvm_mod_param_##name; |
| |
| #endif /* DBG_CFG_REINCLUDE */ |
| #if IS_ENABLED(CPTCFG_IWLXVT) |
| IWL_DBG_CFG(uint32_t, XVT_DEFAULT_DBGM_MEM_POWER) |
| IWL_DBG_CFG(uint32_t, XVT_DEFAULT_DBGM_LMAC_MASK) |
| IWL_DBG_CFG(uint32_t, XVT_DEFAULT_DBGM_PRPH_MASK) |
| IWL_MOD_PARAM(bool, xvt_default_mode) |
| #endif |
| IWL_DBG_CFG_NODEF(bool, disable_52GHz) |
| IWL_DBG_CFG_NODEF(bool, disable_24GHz) |
| #if IS_ENABLED(CPTCFG_IWLMVM) || IS_ENABLED(CPTCFG_IWLFMAC) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_OVERRIDE_CONTROL) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_INIT_FLOW) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_INIT_EVENT) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_D0_FLOW) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_D0_EVENT) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_D3_FLOW) |
| IWL_DBG_CFG_NODEF(uint32_t, MVM_CALIB_D3_EVENT) |
| IWL_DBG_CFG_NODEF(bool, enable_timestamp_marker_cmd) |
| #endif |
| #if IS_ENABLED(CPTCFG_IWLMVM) |
| IWL_DBG_CFG(uint32_t, MVM_DEFAULT_PS_TX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_DEFAULT_PS_RX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_WOWLAN_PS_TX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_WOWLAN_PS_RX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_SHORT_PS_TX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_SHORT_PS_RX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_UAPSD_TX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_UAPSD_RX_DATA_TIMEOUT) |
| IWL_DBG_CFG(uint32_t, MVM_UAPSD_QUEUES) |
| IWL_DBG_CFG_NODEF(bool, MVM_USE_PS_POLL) |
| IWL_DBG_CFG(uint8_t, MVM_PS_HEAVY_TX_THLD_PACKETS) |
| IWL_DBG_CFG(uint8_t, MVM_PS_HEAVY_RX_THLD_PACKETS) |
| IWL_DBG_CFG(uint8_t, MVM_PS_SNOOZE_HEAVY_TX_THLD_PACKETS) |
| IWL_DBG_CFG(uint8_t, MVM_PS_SNOOZE_HEAVY_RX_THLD_PACKETS) |
| IWL_DBG_CFG(uint8_t, MVM_PS_HEAVY_TX_THLD_PERCENT) |
| IWL_DBG_CFG(uint8_t, MVM_PS_HEAVY_RX_THLD_PERCENT) |
| IWL_DBG_CFG(uint16_t, MVM_PS_SNOOZE_INTERVAL) |
| IWL_DBG_CFG(uint16_t, MVM_PS_SNOOZE_WINDOW) |
| IWL_DBG_CFG(uint16_t, MVM_WOWLAN_PS_SNOOZE_WINDOW) |
| IWL_DBG_CFG(uint8_t, MVM_LOWLAT_QUOTA_MIN_PERCENT) |
| IWL_DBG_CFG(uint16_t, MVM_BT_COEX_EN_RED_TXP_THRESH) |
| IWL_DBG_CFG(uint16_t, MVM_BT_COEX_DIS_RED_TXP_THRESH) |
| IWL_DBG_CFG(uint32_t, MVM_BT_COEX_ANTENNA_COUPLING_THRS) |
| IWL_DBG_CFG(uint32_t, MVM_BT_COEX_MPLUT_REG0) |
| IWL_DBG_CFG(uint32_t, MVM_BT_COEX_MPLUT_REG1) |
| IWL_DBG_CFG(bool, MVM_BT_COEX_SYNC2SCO) |
| IWL_DBG_CFG(bool, MVM_BT_COEX_MPLUT) |
| IWL_DBG_CFG(bool, MVM_BT_COEX_TTC) |
| IWL_DBG_CFG(bool, MVM_BT_COEX_RRC) |
| IWL_DBG_CFG(bool, MVM_FW_MCAST_FILTER_PASS_ALL) |
| IWL_DBG_CFG(bool, MVM_FW_BCAST_FILTER_PASS_ALL) |
| IWL_DBG_CFG(bool, MVM_TOF_IS_RESPONDER) |
| IWL_DBG_CFG(bool, MVM_P2P_LOWLATENCY_PS_ENABLE) |
| IWL_DBG_CFG(bool, MVM_SW_TX_CSUM_OFFLOAD) |
| IWL_DBG_CFG(bool, MVM_HW_CSUM_DISABLE) |
| IWL_DBG_CFG(bool, MVM_PARSE_NVM) |
| IWL_DBG_CFG(bool, MVM_ADWELL_ENABLE) |
| IWL_DBG_CFG(uint16_t, MVM_ADWELL_MAX_BUDGET) |
| IWL_DBG_CFG(uint32_t, MVM_TCM_LOAD_MEDIUM_THRESH) |
| IWL_DBG_CFG(uint32_t, MVM_TCM_LOAD_HIGH_THRESH) |
| IWL_DBG_CFG(uint32_t, MVM_TCM_LOWLAT_ENABLE_THRESH) |
| IWL_DBG_CFG(uint32_t, MVM_UAPSD_NONAGG_PERIOD) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_UAPSD_NOAGG_LIST_LEN, 1, IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM) |
| #ifdef CPTCFG_IWLMVM_ADVANCED_QUOTA_MGMT |
| IWL_DBG_CFG(bool, MVM_DYNQUOTA_DISABLED) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_MIN_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_GUARD_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_HIGH_WM_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_LOW_WM_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_START_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_DYNQUOTA_INC_HIGH_PERCENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_LOWLAT_QUOTA_MIN_PCT_P2PCLIENT, 0, 100) |
| IWL_DBG_CFG_RANGE(uint8_t, MVM_LOWLAT_QUOTA_MIN_PCT_P2PGO, 0, 100) |
| #endif /* CPTCFG_IWLMVM_ADVANCED_QUOTA_MGMT */ |
| IWL_DBG_CFG(uint8_t, MVM_QUOTA_THRESHOLD) |
| IWL_DBG_CFG(uint8_t, MVM_RS_RSSI_BASED_INIT_RATE) |
| IWL_DBG_CFG(uint8_t, MVM_RS_80_20_FAR_RANGE_TWEAK) |
| IWL_DBG_CFG(uint8_t, MVM_RS_NUM_TRY_BEFORE_ANT_TOGGLE) |
| IWL_DBG_CFG(uint8_t, MVM_RS_HT_VHT_RETRIES_PER_RATE) |
| IWL_DBG_CFG(uint8_t, MVM_RS_HT_VHT_RETRIES_PER_RATE_TW) |
| IWL_DBG_CFG(uint8_t, MVM_RS_INITIAL_MIMO_NUM_RATES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_INITIAL_SISO_NUM_RATES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_INITIAL_LEGACY_NUM_RATES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_INITIAL_LEGACY_RETRIES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_SECONDARY_LEGACY_RETRIES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_SECONDARY_LEGACY_NUM_RATES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_SECONDARY_SISO_NUM_RATES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_SECONDARY_SISO_RETRIES) |
| IWL_DBG_CFG(uint8_t, MVM_RS_RATE_MIN_FAILURE_TH) |
| IWL_DBG_CFG(uint8_t, MVM_RS_RATE_MIN_SUCCESS_TH) |
| IWL_DBG_CFG(uint8_t, MVM_RS_STAY_IN_COLUMN_TIMEOUT) |
| IWL_DBG_CFG(uint8_t, MVM_RS_IDLE_TIMEOUT) |
| IWL_DBG_CFG(uint8_t, MVM_RS_MISSED_RATE_MAX) |
| IWL_DBG_CFG(uint16_t, MVM_RS_LEGACY_FAILURE_LIMIT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_LEGACY_SUCCESS_LIMIT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_LEGACY_TABLE_COUNT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_NON_LEGACY_FAILURE_LIMIT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_NON_LEGACY_SUCCESS_LIMIT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_NON_LEGACY_TABLE_COUNT) |
| IWL_DBG_CFG(uint16_t, MVM_RS_SR_FORCE_DECREASE) |
| IWL_DBG_CFG(uint16_t, MVM_RS_SR_NO_DECREASE) |
| IWL_DBG_CFG(uint16_t, MVM_RS_AGG_TIME_LIMIT) |
| IWL_DBG_CFG(uint8_t, MVM_RS_AGG_DISABLE_START) |
| IWL_DBG_CFG(uint8_t, MVM_RS_AGG_START_THRESHOLD) |
| IWL_DBG_CFG(uint16_t, MVM_RS_TPC_SR_FORCE_INCREASE) |
| IWL_DBG_CFG(uint16_t, MVM_RS_TPC_SR_NO_INCREASE) |
| IWL_DBG_CFG(uint8_t, MVM_RS_TPC_TX_POWER_STEP) |
| IWL_DBG_CFG(bool, MVM_ENABLE_EBS) |
| IWL_MVM_MOD_PARAM(int, power_scheme) |
| IWL_MVM_MOD_PARAM(bool, init_dbg) |
| IWL_MVM_MOD_PARAM(bool, tfd_q_hang_detect) |
| #endif /* CPTCFG_IWLMVM */ |
| #ifdef CPTCFG_IWLWIFI_FRQ_MGR_TEST |
| IWL_DBG_CFG_NODEF(uint8_t, fm_debug_mode) |
| #endif |
| #if IS_ENABLED(CPTCFG_IWLTEST) |
| IWL_MOD_PARAM(bool, trans_test) |
| #endif |
| #ifdef CPTCFG_IWLWIFI_DEVICE_TESTMODE |
| IWL_DBG_CFG_NODEF(uint32_t, dnt_out_mode) |
| /* XXX: should be dbgm_ or dbg_mon_ for consistency? */ |
| IWL_DBG_CFG_NODEF(uint32_t, dbm_destination_path) |
| /* XXX: should be dbg_mon_ for consistency? */ |
| IWL_DBG_CFG_NODEF(uint32_t, dbgm_enable_mode) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgm_mem_power) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_flags) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_ctl_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_ctl_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_buff_base_addr_reg_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_buff_end_addr_reg_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_data_sel_ctl_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_data_sel_ctl_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_mc_msk_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_mc_msk_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_mask_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_mask_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_start_mask_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_start_mask_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_end_mask_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_end_mask_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_end_threshold_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_end_threshold_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_period_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_sample_period_val) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_wr_ptr_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_cyc_cnt_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_dmarb_rd_ctl_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_dmarb_rd_data_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_marbh_conf_reg) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_marbh_conf_mask) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_marbh_access_type) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_hb_base_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_hb_end_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_dram_wrptr_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_wrap_count_addr) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mipi_conf_reg) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mipi_conf_mask) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_hb_base_val_smem) |
| IWL_DBG_CFG_NODEF(uint32_t, dbgc_hb_end_val_smem) |
| IWL_DBG_CFG_BIN(dbg_conf_monitor_host_command) |
| IWL_DBG_CFG_BIN(log_level_cmd) |
| IWL_DBG_CFG_BINA(ldbg_cmd, 32) |
| IWL_DBG_CFG_NODEF(uint8_t, log_level_cmd_id) |
| IWL_DBG_CFG_NODEF(uint8_t, dbg_conf_monitor_cmd_id) |
| IWL_DBG_CFG_NODEF(uint8_t, ldbg_cmd_nums) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_buff_base_addr_reg_addr_b_step) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_buff_end_addr_reg_addr_b_step) |
| IWL_DBG_CFG_NODEF(uint32_t, dbg_mon_wr_ptr_addr_b_step) |
| #endif /* CPTCFG_IWLWIFI_DEVICE_TESTMODE */ |
| IWL_DBG_CFG_BIN(hw_address) |
| IWL_DBG_CFG_STR(fw_dbg_conf) |
| IWL_DBG_CFG_STR(nvm_file) |
| IWL_DBG_CFG_STR(fw_file_pre) |
| IWL_DBG_CFG_NODEF(uint32_t, d0i3_debug) |
| IWL_DBG_CFG_NODEF(uint32_t, valid_ants) |
| IWL_DBG_CFG_NODEF(uint32_t, no_ack_en) |
| IWL_DBG_CFG_NODEF(bool, no_ldpc) |
| IWL_DBG_CFG_NODEF(uint16_t, rx_mcs_80) |
| IWL_DBG_CFG_NODEF(uint16_t, tx_mcs_80) |
| IWL_DBG_CFG_NODEF(uint16_t, rx_mcs_160) |
| IWL_DBG_CFG_NODEF(uint16_t, tx_mcs_160) |
| IWL_DBG_CFG_NODEF(uint32_t, secure_boot_cfg) |
| IWL_MOD_PARAM(uint32_t, uapsd_disable) |
| IWL_MOD_PARAM(bool, d0i3_disable) |
| IWL_MOD_PARAM(bool, lar_disable) |
| IWL_MOD_PARAM(bool, fw_monitor) |
| IWL_MOD_PARAM(bool, fw_restart) |
| IWL_MOD_PARAM(bool, power_save) |
| IWL_MOD_PARAM(bool, bt_coex_active) |
| IWL_MOD_PARAM(int, antenna_coupling) |
| IWL_MOD_PARAM(int, power_level) |
| IWL_MOD_PARAM(int, led_mode) |
| IWL_MOD_PARAM(int, amsdu_size) |
| IWL_MOD_PARAM(int, swcrypto) |
| IWL_MOD_PARAM(uint, disable_11n) |
| IWL_MOD_PARAM(uint, d0i3_timeout) |
| IWL_DBG_CFG_BIN(he_ppe_thres) |
| IWL_DBG_CFG_NODEF(uint8_t, he_chan_width_dis) |
| IWL_DBG_CFG_NODEF(uint32_t, vht_cap_flip) |
| #ifdef CPTCFG_IWLWIFI_DEBUG |
| IWL_MOD_PARAM(uint32_t, debug_level) |
| #endif /* CPTCFG_IWLWIFI_DEBUG */ |
| #ifdef CPTCFG_IWLWIFI_DISALLOW_OLDER_FW |
| IWL_DBG_CFG_NODEF(bool, load_old_fw) |
| #endif /* CPTCFG_IWLWIFI_DISALLOW_OLDER_FW */ |
| #if IS_ENABLED(CPTCFG_IWLFMAC) |
| IWL_DBG_CFG_NODEF(bool, intcmd_dbg) |
| #endif /* CPTCFG_IWLFMAC */ |
| #undef IWL_DBG_CFG |
| #undef IWL_DBG_CFG_STR |
| #undef IWL_DBG_CFG_NODEF |
| #undef IWL_DBG_CFG_BIN |
| #undef IWL_DBG_CFG_BINA |
| #undef IWL_DBG_CFG_RANGE |
| #undef IWL_MOD_PARAM |
| #undef IWL_MVM_MOD_PARAM |
| #ifndef DBG_CFG_REINCLUDE |
| }; |
| |
| extern struct iwl_dbg_cfg current_dbg_config; |
| void iwl_dbg_cfg_free(struct iwl_dbg_cfg* dbgcfg); |
| void iwl_dbg_cfg_load_ini(struct device* dev, struct iwl_dbg_cfg* dbgcfg); |
| #endif /* DBG_CFG_REINCLUDE */ |
| |
| #endif // SRC_CONNECTIVITY_WLAN_DRIVERS_THIRD_PARTY_INTEL_IWLWIFI_IWL_DBG_CFG_H_ |
