commit 8e63419cdf5e5aebf407ca2bd148944694e2dffc
author Brian Swetland <swetland@google.com> Sun Jan 07 15:12:03 2018 -0800
committer Petr Hosek <phosek@google.com> Sun Jan 20 03:07:04 2019 -0800
tree 193b4710759ac44fa1c7dddc49da2353b6e7a9bf
parent 611356a047efaa05f8499559d9114be21b025c18

nvme: support msi as well as msix

Change-Id: I63880e25ac245f61cb807810453cb7b852be3e87

hw/block/nvme.c

diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 7c8c63e..739f088 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -29,6 +29,7 @@
 #include "qemu/units.h"
 #include "hw/block/block.h"
 #include "hw/hw.h"
+#include "hw/pci/msi.h"
 #include "hw/pci/msix.h"
 #include "hw/pci/pci.h"
 #include "sysemu/sysemu.h"
@@ -109,7 +110,9 @@
 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
 {
     if (cq->irq_enabled) {
-        if (msix_enabled(&(n->parent_obj))) {
+        if (msi_enabled(&(n->parent_obj))) {
+            msi_notify(&(n->parent_obj), cq->vector);
+        } else if (msix_enabled(&(n->parent_obj))) {
             trace_nvme_irq_msix(cq->vector);
             msix_notify(&(n->parent_obj), cq->vector);
         } else {
@@ -1249,6 +1252,7 @@
         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
         &n->iomem);
     msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL);
+    msi_init(&n->parent_obj, 0, n->num_queues, true, false, NULL);
 
     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
@@ -1338,13 +1342,14 @@
         g_free(n->cmbuf);
     }
     msix_uninit_exclusive_bar(pci_dev);
+    msi_uninit(&n->parent_obj);
 }
 
 static Property nvme_props[] = {
     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
     DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0),
-    DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64),
+    DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 32),
     DEFINE_PROP_END_OF_LIST(),
 };