Fix bugs with tbnz/tbz instructions.
sim/aarch64
* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index d8eb000..2eca54d 100644
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-03 Jim Wilson <jim.wilson@linaro.org>
+
+ * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
+ (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
+
2016-12-01 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (fsturs): Switch use of rn and st variables.
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 4fa5dc1..34fd17d 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -13353,7 +13353,7 @@
unsigned rt = INSTR (4, 0);
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
- if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos))
+ if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos))
aarch64_set_next_PC_by_offset (cpu, offset);
}
@@ -13364,7 +13364,7 @@
unsigned rt = INSTR (4, 0);
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
- if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos)))
+ if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos)))
aarch64_set_next_PC_by_offset (cpu, offset);
}
@@ -13407,7 +13407,7 @@
instr[18,5] = simm14 : signed offset counted in words
instr[4,0] = uimm5 */
- uint32_t pos = ((INSTR (31, 31) << 4) | INSTR (23, 19));
+ uint32_t pos = ((INSTR (31, 31) << 5) | INSTR (23, 19));
int32_t offset = simm32 (aarch64_get_instr (cpu), 18, 5) << 2;
NYI_assert (30, 25, 0x1b);
