| /* Copyright (c) 2013, Linaro Limited |
| All rights reserved. |
| |
| Redistribution and use in source and binary forms, with or without |
| modification, are permitted provided that the following conditions are met: |
| * Redistributions of source code must retain the above copyright |
| notice, this list of conditions and the following disclaimer. |
| * Redistributions in binary form must reproduce the above copyright |
| notice, this list of conditions and the following disclaimer in the |
| documentation and/or other materials provided with the distribution. |
| * Neither the name of the Linaro nor the |
| names of its contributors may be used to endorse or promote products |
| derived from this software without specific prior written permission. |
| |
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| |
| /* |
| * Copyright (c) 2015 ARM Ltd |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * 1. Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * 3. The name of the company may not be used to endorse or promote |
| * products derived from this software without specific prior written |
| * permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
| * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| /* Assumptions: |
| * |
| * ARMv8-a, AArch64, unaligned accesses |
| */ |
| |
| .macro def_fn f p2align=0 |
| .text |
| .p2align \p2align |
| .global \f |
| .type \f, %function |
| \f: |
| .endm |
| |
| /* Parameters and result. */ |
| #define dstin x0 |
| #define src x1 |
| #define count x2 |
| #define srcend x3 |
| #define dstend x4 |
| #define tmp1 x5 |
| #define A_l x6 |
| #define A_h x7 |
| #define B_l x8 |
| #define B_h x9 |
| #define C_l x10 |
| #define C_h x11 |
| #define D_l x12 |
| #define D_h x13 |
| #define E_l count |
| #define E_h tmp1 |
| |
| /* All memmoves up to 96 bytes are done by memcpy as it supports overlaps. |
| Larger backwards copies are also handled by memcpy. The only remaining |
| case is forward large copies. The destination is aligned, and an |
| unrolled loop processes 64 bytes per iteration. |
| */ |
| |
| def_fn memmove, 6 |
| sub tmp1, dstin, src |
| cmp count, 96 |
| ccmp tmp1, count, 2, hi |
| b.hs memcpy |
| |
| cbz tmp1, 3f |
| add dstend, dstin, count |
| add srcend, src, count |
| |
| /* Align dstend to 16 byte alignment so that we don't cross cache line |
| boundaries on both loads and stores. There are at least 96 bytes |
| to copy, so copy 16 bytes unaligned and then align. The loop |
| copies 64 bytes per iteration and prefetches one iteration ahead. */ |
| |
| and tmp1, dstend, 15 |
| ldp D_l, D_h, [srcend, -16] |
| sub srcend, srcend, tmp1 |
| sub count, count, tmp1 |
| ldp A_l, A_h, [srcend, -16] |
| stp D_l, D_h, [dstend, -16] |
| ldp B_l, B_h, [srcend, -32] |
| ldp C_l, C_h, [srcend, -48] |
| ldp D_l, D_h, [srcend, -64]! |
| sub dstend, dstend, tmp1 |
| subs count, count, 128 |
| b.ls 2f |
| nop |
| 1: |
| stp A_l, A_h, [dstend, -16] |
| ldp A_l, A_h, [srcend, -16] |
| stp B_l, B_h, [dstend, -32] |
| ldp B_l, B_h, [srcend, -32] |
| stp C_l, C_h, [dstend, -48] |
| ldp C_l, C_h, [srcend, -48] |
| stp D_l, D_h, [dstend, -64]! |
| ldp D_l, D_h, [srcend, -64]! |
| subs count, count, 64 |
| b.hi 1b |
| |
| /* Write the last full set of 64 bytes. The remainder is at most 64 |
| bytes, so it is safe to always copy 64 bytes from the start even if |
| there is just 1 byte left. */ |
| 2: |
| ldp E_l, E_h, [src, 48] |
| stp A_l, A_h, [dstend, -16] |
| ldp A_l, A_h, [src, 32] |
| stp B_l, B_h, [dstend, -32] |
| ldp B_l, B_h, [src, 16] |
| stp C_l, C_h, [dstend, -48] |
| ldp C_l, C_h, [src] |
| stp D_l, D_h, [dstend, -64] |
| stp E_l, E_h, [dstin, 48] |
| stp A_l, A_h, [dstin, 32] |
| stp B_l, B_h, [dstin, 16] |
| stp C_l, C_h, [dstin] |
| 3: ret |
| |
| .size memmove, . - memmove |