| // Copyright 2018 The Fuchsia Authors. All rights reserved. |
| // Use of this source code is governed by a BSD-style license that can be |
| // found in the LICENSE file. |
| |
| #pragma once |
| |
| /* HHI */ |
| #define HHI_MEM_PD_REG0 (0x40 << 2) |
| #define HHI_VPU_MEM_PD_REG0 (0x41 << 2) |
| #define HHI_VPU_MEM_PD_REG1 (0x42 << 2) |
| #define HHI_AUD_DAC_CTRL (0x44 << 2) |
| #define HHI_VIID_CLK_DIV (0x4a << 2) |
| #define HHI_GCLK_MPEG0 (0x50 << 2) |
| #define HHI_GCLK_MPEG1 (0x51 << 2) |
| #define HHI_GCLK_MPEG2 (0x52 << 2) |
| #define HHI_GCLK_OTHER (0x54 << 2) |
| #define HHI_GCLK_AO (0x55 << 2) |
| #define HHI_SYS_OSCIN_CNTL (0x56 << 2) |
| #define HHI_SYS_CPU_CLK_CNTL1 (0x57 << 2) |
| #define HHI_SYS_CPU_RESET_CNTL (0x58 << 2) |
| #define HHI_VID_CLK_DIV (0x59 << 2) |
| #define HHI_MPEG_CLK_CNTL (0x5d << 2) |
| #define HHI_AUD_CLK_CNTL (0x5e << 2) |
| #define HHI_VID_CLK_CNTL (0x5f << 2) |
| #define HHI_WIFI_CLK_CNTL (0x60 << 2) |
| #define HHI_WIFI_PLL_CNTL (0x61 << 2) |
| #define HHI_WIFI_PLL_CNTL2 (0x62 << 2) |
| #define HHI_WIFI_PLL_CNTL3 (0x63 << 2) |
| #define HHI_AUD_CLK_CNTL2 (0x64 << 2) |
| #define HHI_VID_CLK_CNTL2 (0x65 << 2) |
| #define HHI_VID_DIVIDER_CNTL (0x66 << 2) |
| #define HHI_SYS_CPU_CLK_CNTL (0x67 << 2) |
| #define HHI_VID_PLL_CLK_DIV (0x68 << 2) |
| #define HHI_AUD_CLK_CNTL3 (0x69 << 2) |
| #define HHI_MALI_CLK_CNTL (0x6c << 2) |
| #define HHI_MIPI_PHY_CLK_CNTL (0x6e << 2) |
| #define HHI_VPU_CLK_CNTL (0x6f << 2) |
| #define HHI_OTHER_PLL_CNTL (0x70 << 2) |
| #define HHI_OTHER_PLL_CNTL2 (0x71 << 2) |
| #define HHI_OTHER_PLL_CNTL3 (0x72 << 2) |
| #define HHI_HDMI_CLK_CNTL (0x73 << 2) |
| #define HHI_DEMOD_CLK_CNTL (0x74 << 2) |
| #define HHI_SATA_CLK_CNTL (0x75 << 2) |
| #define HHI_ETH_CLK_CNTL (0x76 << 2) |
| #define HHI_CLK_DOUBLE_CNTL (0x77 << 2) |
| #define HHI_VDEC_CLK_CNTL (0x78 << 2) |
| #define HHI_VDEC2_CLK_CNTL (0x79 << 2) |
| #define HHI_VDEC3_CLK_CNTL (0x7a << 2) |
| #define HHI_VDEC4_CLK_CNTL (0x7b << 2) |
| #define HHI_HDCP22_CLK_CNTL (0x7c << 2) |
| #define HHI_VAPBCLK_CNTL (0x7d << 2) |
| #define HHI_VP9DEC_CLK_CNTL (0x7e << 2) |
| #define HHI_HDMI_AFC_CNTL (0x7f << 2) |
| #define HHI_HDMIRX_CLK_CNTL (0x80 << 2) |
| #define HHI_HDMIRX_AUD_CLK_CNTL (0x81 << 2) |
| #define HHI_EDP_APB_CLK_CNTL (0x82 << 2) |
| #define HHI_VPU_CLKB_CNTL (0x83 << 2) |
| #define HHI_VID_PLL_MOD_CNTL0 (0x84 << 2) |
| #define HHI_VID_PLL_MOD_LOW_TCNT (0x85 << 2) |
| #define HHI_VID_PLL_MOD_HIGH_TCNT (0x86 << 2) |
| #define HHI_VID_PLL_MOD_NOM_TCNT (0x87 << 2) |
| #define HHI_USB_CLK_CNTL (0x88 << 2) |
| #define HHI_32K_CLK_CNTL (0x89 << 2) |
| #define HHI_GEN_CLK_CNTL (0x8a << 2) |
| #define HHI_GEN_CLK_CNTL2 (0x8b << 2) |
| #define HHI_JTAG_CONFIG (0x8e << 2) |
| #define HHI_VAFE_CLKXTALIN_CNTL (0x8f << 2) |
| #define HHI_VAFE_CLKOSCIN_CNTL (0x90 << 2) |
| #define HHI_VAFE_CLKIN_CNTL (0x91 << 2) |
| #define HHI_TVFE_AUTOMODE_CLK_CNTL (0x92 << 2) |
| #define HHI_VAFE_CLKPI_CNTL (0x93 << 2) |
| #define HHI_VDIN_MEAS_CLK_CNTL (0x94 << 2) |
| #define HHI_PCM_CLK_CNTL (0x96 << 2) |
| #define HHI_NAND_CLK_CNTL (0x97 << 2) |
| #define HHI_ISP_LED_CLK_CNTL (0x98 << 2) |
| #define HHI_SD_EMMC_CLK_CNTL (0x99 << 2) |
| #define HHI_EDP_TX_PHY_CNTL0 (0x9c << 2) |
| #define HHI_EDP_TX_PHY_CNTL1 (0x9d << 2) |
| #define HHI_MPLL_CNTL (0xa0 << 2) |
| #define HHI_MPLL_CNTL2 (0xa1 << 2) |
| #define HHI_MPLL_CNTL3 (0xa2 << 2) |
| #define HHI_MPLL_CNTL4 (0xa3 << 2) |
| #define HHI_MPLL_CNTL5 (0xa4 << 2) |
| #define HHI_MPLL_CNTL6 (0xa5 << 2) |
| #define HHI_MPLL_CNTL7 (0xa6 << 2) |
| #define HHI_MPLL_CNTL8 (0xa7 << 2) |
| #define HHI_MPLL_CNTL9 (0xa8 << 2) |
| #define HHI_MPLL_CNTL10 (0xa9 << 2) |
| #define HHI_ADC_PLL_CNTL (0xaa << 2) |
| #define HHI_ADC_PLL_CNTL2 (0xab << 2) |
| #define HHI_ADC_PLL_CNTL3 (0xac << 2) |
| #define HHI_ADC_PLL_CNTL4 (0xad << 2) |
| #define HHI_ADC_PLL_CNTL_I (0xae << 2) |
| #define HHI_AUDCLK_PLL_CNTL (0xb0 << 2) |
| #define HHI_AUDCLK_PLL_CNTL2 (0xb1 << 2) |
| #define HHI_AUDCLK_PLL_CNTL3 (0xb2 << 2) |
| #define HHI_AUDCLK_PLL_CNTL4 (0xb3 << 2) |
| #define HHI_AUDCLK_PLL_CNTL5 (0xb4 << 2) |
| #define HHI_AUDCLK_PLL_CNTL6 (0xb5 << 2) |
| #define HHI_L2_DDR_CLK_CNTL (0xb6 << 2) |
| #define HHI_MPLL3_CNTL0 (0xb8 << 2) |
| #define HHI_MPLL3_CNTL1 (0xb9 << 2) |
| #define HHI_VDAC_CNTL0 (0xbd << 2) |
| #define HHI_VDAC_CNTL1 (0xbe << 2) |
| #define HHI_SYS_PLL_CNTL (0xc0 << 2) |
| #define HHI_SYS_PLL_CNTL2 (0xc1 << 2) |
| #define HHI_SYS_PLL_CNTL3 (0xc2 << 2) |
| #define HHI_SYS_PLL_CNTL4 (0xc3 << 2) |
| #define HHI_SYS_PLL_CNTL5 (0xc4 << 2) |
| #define HHI_DPLL_TOP_I (0xc6 << 2) |
| #define HHI_DPLL_TOP2_I (0xc7 << 2) |
| |
| #define HHI_HDMI_PLL_CNTL (0xc8 << 2) |
| #define PLL_CNTL_LOCK (1 << 31) |
| #define PLL_CNTL_ENABLE (1 << 30) |
| #define PLL_CNTL_RESET (1 << 28) |
| #define PLL_CNTL_N(x) (x << 9) |
| #define PLL_CNTL_M_START (0) |
| #define PLL_CNTL_M_BITS (9) |
| |
| #define HHI_HDMI_PLL_CNTL1 (0xc9 << 2) |
| #define PLL_CNTL1_DIV_FRAC_START (0) |
| #define PLL_CNTL1_DIV_FRAC_BITS (12) |
| |
| #define HHI_HDMI_PLL_CNTL2 (0xca << 2) |
| #define HHI_HDMI_PLL_CNTL3 (0xcb << 2) |
| #define HHI_HDMI_PLL_CNTL4 (0xcc << 2) |
| #define HHI_HDMI_PLL_CNTL5 (0xcd << 2) |
| #define HHI_HDMI_PLL_STS (0xce << 2) |
| #define HHI_DSI_LVDS_EDP_CNTL0 (0xd1 << 2) |
| #define HHI_DSI_LVDS_EDP_CNTL1 (0xd2 << 2) |
| #define HHI_CSI_PHY_CNTL0 (0xd3 << 2) |
| #define HHI_CSI_PHY_CNTL1 (0xd4 << 2) |
| #define HHI_CSI_PHY_CNTL2 (0xd5 << 2) |
| #define HHI_CSI_PHY_CNTL3 (0xd6 << 2) |
| #define HHI_CSI_PHY_CNTL4 (0xd7 << 2) |
| #define HHI_DIF_CSI_PHY_CNTL0 (0xd8 << 2) |
| #define HHI_DIF_CSI_PHY_CNTL1 (0xd9 << 2) |
| #define HHI_DIF_CSI_PHY_CNTL2 (0xda << 2) |
| #define HHI_DIF_CSI_PHY_CNTL3 (0xdb << 2) |
| #define HHI_DIF_CSI_PHY_CNTL4 (0xdc << 2) |
| #define HHI_DIF_CSI_PHY_CNTL5 (0xdd << 2) |
| #define HHI_LVDS_TX_PHY_CNTL0 (0xde << 2) |
| #define HHI_LVDS_TX_PHY_CNTL1 (0xdf << 2) |
| #define HHI_VID2_PLL_CNTL (0xe0 << 2) |
| #define HHI_VID2_PLL_CNTL2 (0xe1 << 2) |
| #define HHI_VID2_PLL_CNTL3 (0xe2 << 2) |
| #define HHI_VID2_PLL_CNTL4 (0xe3 << 2) |
| #define HHI_VID2_PLL_CNTL5 (0xe4 << 2) |
| #define HHI_VID2_PLL_CNTL_I (0xe5 << 2) |
| #define HHI_HDMI_PHY_CNTL0 (0xe8 << 2) |
| #define HHI_HDMI_PHY_CNTL1 (0xe9 << 2) |
| #define HHI_HDMI_PHY_CNTL2 (0xea << 2) |
| #define HHI_HDMI_PHY_CNTL3 (0xeb << 2) |
| #define HHI_VID_LOCK_CLK_CNTL (0xf2 << 2) |
| #define HHI_ATV_DMD_SYS_CLK_CNTL (0xf3 << 2) |
| #define HHI_BT656_CLK_CNTL (0xf5 << 2) |
| #define HHI_SAR_CLK_CNTL (0xf6 << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL (0xf8 << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL2 (0xf9 << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL3 (0xfa << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL4 (0xfb << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL5 (0xfc << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL6 (0xfd << 2) |
| #define HHI_HDMIRX_AUD_PLL_CNTL_I (0xfe << 2) |
| |
| /* viu */ |
| #define VPU_VIU_ADDR_START (0x1a00 << 2) |
| #define VPU_VIU_ADDR_END (0x1aff << 2) |
| #define VPU_VIU_SW_RESET (0x1a01 << 2) |
| #define VPU_VIU_MISC_CTRL0 (0x1a06 << 2) |
| #define VPU_D2D3_INTF_LENGTH (0x1a08 << 2) |
| #define VPU_D2D3_INTF_CTRL0 (0x1a09 << 2) |
| #define VPU_VIU_OSD1_CTRL_STAT (0x1a10 << 2) |
| #define VPU_VIU_OSD1_CTRL_STAT2 (0x1a2d << 2) |
| #define VPU_VIU_OSD1_COLOR_ADDR (0x1a11 << 2) |
| #define VPU_VIU_OSD1_COLOR (0x1a12 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG0 (0x1a17 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG1 (0x1a18 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG2 (0x1a19 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG3 (0x1a1a << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W0 (0x1a1b << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W0 (0x1a1f << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W0 (0x1a23 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W0 (0x1a27 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W1 (0x1a1c << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W1 (0x1a20 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W1 (0x1a24 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W1 (0x1a28 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W2 (0x1a1d << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W2 (0x1a21 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W2 (0x1a25 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W2 (0x1a29 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W3 (0x1a1e << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W3 (0x1a22 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W3 (0x1a26 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W3 (0x1a2a << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W4 (0x1a13 << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W4 (0x1a14 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W4 (0x1a15 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W4 (0x1a16 << 2) |
| #define VPU_VIU_OSD1_FIFO_CTRL_STAT (0x1a2b << 2) |
| #define VPU_VIU_OSD1_TEST_RDDATA (0x1a2c << 2) |
| #define VPU_VIU_OSD1_PROT_CTRL (0x1a2e << 2) |
| #define VPU_VIU_OSD2_CTRL_STAT (0x1a30 << 2) |
| #define VPU_VIU_OSD2_CTRL_STAT2 (0x1a4d << 2) |
| #define VPU_VIU_OSD2_COLOR_ADDR (0x1a31 << 2) |
| #define VPU_VIU_OSD2_COLOR (0x1a32 << 2) |
| #define VPU_VIU_OSD2_HL1_H_START_END (0x1a33 << 2) |
| #define VPU_VIU_OSD2_HL1_V_START_END (0x1a34 << 2) |
| #define VPU_VIU_OSD2_HL2_H_START_END (0x1a35 << 2) |
| #define VPU_VIU_OSD2_HL2_V_START_END (0x1a36 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG0 (0x1a37 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG1 (0x1a38 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG2 (0x1a39 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG3 (0x1a3a << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W0 (0x1a3b << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W0 (0x1a3f << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W0 (0x1a43 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W0 (0x1a47 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W1 (0x1a3c << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W1 (0x1a40 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W1 (0x1a44 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W1 (0x1a48 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W2 (0x1a3d << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W2 (0x1a41 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W2 (0x1a45 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W2 (0x1a49 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W3 (0x1a3e << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W3 (0x1a42 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W3 (0x1a46 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W3 (0x1a4a << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W4 (0x1a64 << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W4 (0x1a65 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W4 (0x1a66 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W4 (0x1a67 << 2) |
| #define VPU_VIU_OSD2_FIFO_CTRL_STAT (0x1a4b << 2) |
| #define VPU_VIU_OSD2_TEST_RDDATA (0x1a4c << 2) |
| #define VPU_VIU_OSD2_PROT_CTRL (0x1a4e << 2) |
| #define VPU_VPP_OSD_SCO_H_START_END (0x1dca << 2) |
| #define VPU_VPP_OSD_SCO_V_START_END (0x1dcb << 2) |
| #define VPU_VPP_POSTBLEND_H_SIZE (0x1d21 << 2) |
| #define VPU_VPP_OSD_SCI_WH_M1 (0x1dc9 << 2) |
| #define VPU_ENCP_VIDEO_EN (0x1b80 << 2) |
| #define VPU_ENCI_VIDEO_EN (0x1b57 << 2) |
| #define VPU_ENCP_VIDEO_FILT_CTRL (0x1bb8 << 2) |
| #define VPU_VENC_DVI_SETTING (0x1b62 << 2) |
| #define VPU_ENCP_VIDEO_MODE (0x1b8d << 2) |
| #define VPU_ENCP_VIDEO_MODE_ADV (0x1b8e << 2) |
| #define VPU_VENC_VIDEO_TST_Y (0x1b72 << 2) |
| #define VPU_VENC_VIDEO_TST_CB (0x1b73 << 2) |
| #define VPU_VENC_VIDEO_TST_CR (0x1b74 << 2) |
| #define VPU_VENC_VIDEO_TST_CLRBAR_STRT (0x1b75 << 2) |
| #define VPU_VENC_VIDEO_TST_CLRBAR_WIDTH (0x1b76 << 2) |
| #define VPU_ENCP_VIDEO_YFP1_HTIME (0x1b94 << 2) |
| #define VPU_ENCP_VIDEO_YFP2_HTIME (0x1b95 << 2) |
| #define VPU_ENCP_VIDEO_MAX_PXCNT (0x1b97 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_BEGIN (0x1b98 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_END (0x1b99 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_SWITCH (0x1b9a << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_BEGIN (0x1b9b << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_END (0x1b9c << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_BLINE (0x1b9d << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_ELINE (0x1b9e << 2) |
| #define VPU_ENCP_VIDEO_HAVON_END (0x1ba3 << 2) |
| #define VPU_ENCP_VIDEO_HAVON_BEGIN (0x1ba4 << 2) |
| #define VPU_ENCP_VIDEO_VAVON_ELINE (0x1baf << 2) |
| #define VPU_ENCP_VIDEO_VAVON_BLINE (0x1ba6 << 2) |
| #define VPU_ENCP_VIDEO_HSO_BEGIN (0x1ba7 << 2) |
| #define VPU_ENCP_VIDEO_HSO_END (0x1ba8 << 2) |
| #define VPU_ENCP_VIDEO_VSO_BEGIN (0x1ba9 << 2) |
| #define VPU_ENCP_VIDEO_VSO_END (0x1baa << 2) |
| #define VPU_ENCP_VIDEO_VSO_BLINE (0x1bab << 2) |
| #define VPU_ENCP_VIDEO_VSO_ELINE (0x1bac << 2) |
| #define VPU_ENCP_VIDEO_SYNC_WAVE_CURVE (0x1bad << 2) |
| #define VPU_ENCP_VIDEO_MAX_LNCNT (0x1bae << 2) |
| #define VPU_ENCP_VIDEO_EN (0x1b80 << 2) |
| #define VPU_ENCP_VIDEO_SYNC_MODE (0x1b81 << 2) |
| #define VPU_ENCP_MACV_EN (0x1b82 << 2) |
| #define VPU_ENCP_VIDEO_Y_SCL (0x1b83 << 2) |
| #define VPU_ENCP_VIDEO_PB_SCL (0x1b84 << 2) |
| #define VPU_ENCP_VIDEO_PR_SCL (0x1b85 << 2) |
| #define VPU_ENCP_VIDEO_SYNC_SCL (0x1b86 << 2) |
| #define VPU_ENCP_VIDEO_MACV_SCL (0x1b87 << 2) |
| #define VPU_ENCP_VIDEO_Y_OFFST (0x1b88 << 2) |
| #define VPU_ENCP_VIDEO_PB_OFFST (0x1b89 << 2) |
| #define VPU_ENCP_VIDEO_PR_OFFST (0x1b8a << 2) |
| #define VPU_ENCP_VIDEO_SYNC_OFFST (0x1b8b << 2) |
| #define VPU_ENCP_VIDEO_MACV_OFFST (0x1b8c << 2) |
| #define VPU_ENCP_VIDEO_SY_VAL (0x1bb0 << 2) |
| #define VPU_ENCP_VIDEO_SY2_VAL (0x1bb1 << 2) |
| #define VPU_ENCP_VIDEO_BLANKY_VAL (0x1bb2 << 2) |
| #define VPU_ENCP_VIDEO_BLANKPB_VAL (0x1bb3 << 2) |
| #define VPU_ENCP_VIDEO_BLANKPR_VAL (0x1bb4 << 2) |
| |
| #define VPU_VD1_IF0_GEN_REG (0x1a50 << 2) |
| #define VPU_VD1_IF0_CANVAS0 (0x1a51 << 2) |
| #define VPU_VD1_IF0_CANVAS1 (0x1a52 << 2) |
| #define VPU_VD1_IF0_LUMA_X0 (0x1a53 << 2) |
| #define VPU_VD1_IF0_LUMA_Y0 (0x1a54 << 2) |
| #define VPU_VD1_IF0_CHROMA_X0 (0x1a55 << 2) |
| #define VPU_VD1_IF0_CHROMA_Y0 (0x1a56 << 2) |
| #define VPU_VD1_IF0_LUMA_X1 (0x1a57 << 2) |
| #define VPU_VD1_IF0_LUMA_Y1 (0x1a58 << 2) |
| #define VPU_VD1_IF0_CHROMA_X1 (0x1a59 << 2) |
| #define VPU_VD1_IF0_CHROMA_Y1 (0x1a5a << 2) |
| #define VPU_VD1_IF0_RPT_LOOP (0x1a5b << 2) |
| #define VPU_VD1_IF0_LUMA0_RPT_PAT (0x1a5c << 2) |
| #define VPU_VD1_IF0_CHROMA0_RPT_PAT (0x1a5d << 2) |
| #define VPU_VD1_IF0_LUMA1_RPT_PAT (0x1a5e << 2) |
| #define VPU_VD1_IF0_CHROMA1_RPT_PAT (0x1a5f << 2) |
| #define VPU_VD1_IF0_LUMA_PSEL (0x1a60 << 2) |
| #define VPU_VD1_IF0_CHROMA_PSEL (0x1a61 << 2) |
| #define VPU_VD1_IF0_DUMMY_PIXEL (0x1a62 << 2) |
| #define VPU_VD1_IF0_LUMA_FIFO_SIZE (0x1a63 << 2) |
| #define VPU_VD1_IF0_RANGE_MAP_Y (0x1a6a << 2) |
| #define VPU_VD1_IF0_RANGE_MAP_CB (0x1a6b << 2) |
| #define VPU_VD1_IF0_RANGE_MAP_CR (0x1a6c << 2) |
| #define VPU_VD1_IF0_GEN_REG2 (0x1a6d << 2) |
| #define VPU_VD1_IF0_PROT_CNTL (0x1a6e << 2) |
| #define VPU_VIU_VD1_FMT_CTRL (0x1a68 << 2) |
| #define VPU_VIU_VD1_FMT_W (0x1a69 << 2) |
| #define VPU_VD2_IF0_GEN_REG (0x1a70 << 2) |
| #define VPU_VD2_IF0_CANVAS0 (0x1a71 << 2) |
| #define VPU_VD2_IF0_CANVAS1 (0x1a72 << 2) |
| #define VPU_VD2_IF0_LUMA_X0 (0x1a73 << 2) |
| #define VPU_VD2_IF0_LUMA_Y0 (0x1a74 << 2) |
| #define VPU_VD2_IF0_CHROMA_X0 (0x1a75 << 2) |
| #define VPU_VD2_IF0_CHROMA_Y0 (0x1a76 << 2) |
| #define VPU_VD2_IF0_LUMA_X1 (0x1a77 << 2) |
| #define VPU_VD2_IF0_LUMA_Y1 (0x1a78 << 2) |
| #define VPU_VD2_IF0_CHROMA_X1 (0x1a79 << 2) |
| #define VPU_VD2_IF0_CHROMA_Y1 (0x1a7a << 2) |
| #define VPU_VD2_IF0_RPT_LOOP (0x1a7b << 2) |
| #define VPU_VD2_IF0_LUMA0_RPT_PAT (0x1a7c << 2) |
| #define VPU_VD2_IF0_CHROMA0_RPT_PAT (0x1a7d << 2) |
| #define VPU_VD2_IF0_LUMA1_RPT_PAT (0x1a7e << 2) |
| #define VPU_VD2_IF0_CHROMA1_RPT_PAT (0x1a7f << 2) |
| #define VPU_VD2_IF0_LUMA_PSEL (0x1a80 << 2) |
| #define VPU_VD2_IF0_CHROMA_PSEL (0x1a81 << 2) |
| #define VPU_VD2_IF0_DUMMY_PIXEL (0x1a82 << 2) |
| #define VPU_VD2_IF0_LUMA_FIFO_SIZE (0x1a83 << 2) |
| #define VPU_VD2_IF0_RANGE_MAP_Y (0x1a8a << 2) |
| #define VPU_VD2_IF0_RANGE_MAP_CB (0x1a8b << 2) |
| #define VPU_VD2_IF0_RANGE_MAP_CR (0x1a8c << 2) |
| #define VPU_VD2_IF0_GEN_REG2 (0x1a8d << 2) |
| #define VPU_VD2_IF0_PROT_CNTL (0x1a8e << 2) |
| #define VPU_VIU_VD2_FMT_CTRL (0x1a88 << 2) |
| #define VPU_VIU_VD2_FMT_W (0x1a89 << 2) |
| |
| #define VPU_VPU_VIU_VENC_MUX_CTRL (0x271a << 2) |
| #define VIU_VENC_MUX_CTRL_VIU2(x) (x << 2) |
| #define VIU_VENC_MUX_CTRL_VIU1(x) (x << 0) |
| |
| #define VPU_VENC_VIDEO_PROG_MODE (0x1b68 << 2) |
| #define VPU_ENCP_DE_H_BEGIN (0x1c3a << 2) |
| #define VPU_ENCP_DE_H_END (0x1c3b << 2) |
| #define VPU_ENCP_DE_V_BEGIN_EVEN (0x1c3c << 2) |
| #define VPU_ENCP_DE_V_END_EVEN (0x1c3d << 2) |
| #define VPU_ENCP_DVI_HSO_BEGIN (0x1c30 << 2) |
| #define VPU_ENCP_DVI_HSO_END (0x1c31 << 2) |
| #define VPU_ENCP_DVI_VSO_BLINE_EVN (0x1c32 << 2) |
| #define VPU_ENCP_DVI_VSO_ELINE_EVN (0x1c34 << 2) |
| #define VPU_ENCP_DVI_VSO_BEGIN_EVN (0x1c36 << 2) |
| #define VPU_ENCP_DVI_VSO_END_EVN (0x1c38 << 2) |
| #define VPU_HDMI_SETTING (0x271b << 2) |
| #define VPU_HDMI_FMT_CTRL (0x2743 << 2) |
| #define VPU_HDMI_DITH_CNTL (0x27fc << 2) |
| #define VPU_VENC_VIDEO_TST_EN (0x1b70 << 2) |
| #define VPU_VENC_VIDEO_TST_MDSEL (0x1b71 << 2) |
| |
| #define VPU_VPP_DUMMY_DATA (0x1d00 << 2) |
| #define VPU_VPP_LINE_IN_LENGTH (0x1d01 << 2) |
| #define VPU_VPP_PIC_IN_HEIGHT (0x1d02 << 2) |
| #define VPU_VPP_SCALE_COEF_IDX (0x1d03 << 2) |
| #define VPU_VPP_SCALE_COEF (0x1d04 << 2) |
| #define VPU_VPP_VSC_REGION12_STARTP (0x1d05 << 2) |
| #define VPU_VPP_VSC_REGION34_STARTP (0x1d06 << 2) |
| #define VPU_VPP_VSC_REGION4_ENDP (0x1d07 << 2) |
| #define VPU_VPP_VSC_START_PHASE_STEP (0x1d08 << 2) |
| #define VPU_VPP_VSC_REGION0_PHASE_SLOPE (0x1d09 << 2) |
| #define VPU_VPP_VSC_REGION1_PHASE_SLOPE (0x1d0a << 2) |
| #define VPU_VPP_VSC_REGION3_PHASE_SLOPE (0x1d0b << 2) |
| #define VPU_VPP_VSC_REGION4_PHASE_SLOPE (0x1d0c << 2) |
| #define VPU_VPP_VSC_PHASE_CTRL (0x1d0d << 2) |
| #define VPU_VPP_VSC_INI_PHASE (0x1d0e << 2) |
| #define VPU_VPP_HSC_REGION12_STARTP (0x1d10 << 2) |
| #define VPU_VPP_HSC_REGION34_STARTP (0x1d11 << 2) |
| #define VPU_VPP_HSC_REGION4_ENDP (0x1d12 << 2) |
| #define VPU_VPP_HSC_START_PHASE_STEP (0x1d13 << 2) |
| #define VPU_VPP_HSC_REGION0_PHASE_SLOPE (0x1d14 << 2) |
| #define VPU_VPP_HSC_REGION1_PHASE_SLOPE (0x1d15 << 2) |
| #define VPU_VPP_HSC_REGION3_PHASE_SLOPE (0x1d16 << 2) |
| #define VPU_VPP_HSC_REGION4_PHASE_SLOPE (0x1d17 << 2) |
| #define VPU_VPP_HSC_PHASE_CTRL (0x1d18 << 2) |
| #define VPU_VPP_SC_MISC (0x1d19 << 2) |
| #define VPU_VPP_PREBLEND_VD1_H_START_END (0x1d1a << 2) |
| #define VPU_VPP_PREBLEND_VD1_V_START_END (0x1d1b << 2) |
| #define VPU_VPP_POSTBLEND_VD1_H_START_END (0x1d1c << 2) |
| #define VPU_VPP_POSTBLEND_VD1_V_START_END (0x1d1d << 2) |
| #define VPU_VPP_BLEND_VD2_H_START_END (0x1d1e << 2) |
| #define VPU_VPP_BLEND_VD2_V_START_END (0x1d1f << 2) |
| #define VPU_VPP_PREBLEND_H_SIZE (0x1d20 << 2) |
| #define VPU_VPP_POSTBLEND_H_SIZE (0x1d21 << 2) |
| #define VPU_VPP_HOLD_LINES (0x1d22 << 2) |
| #define VPU_VPP_BLEND_ONECOLOR_CTRL (0x1d23 << 2) |
| #define VPU_VPP_PREBLEND_CURRENT_XY (0x1d24 << 2) |
| #define VPU_VPP_POSTBLEND_CURRENT_XY (0x1d25 << 2) |
| #define VPU_VPP_MISC (0x1d26 << 2) |
| #define VPU_VPP_OFIFO_SIZE (0x1d27 << 2) |
| #define VPU_VPP_FIFO_STATUS (0x1d28 << 2) |
| #define VPU_VPP_SMOKE_CTRL (0x1d29 << 2) |
| #define VPU_VPP_SMOKE1_VAL (0x1d2a << 2) |
| #define VPU_VPP_SMOKE2_VAL (0x1d2b << 2) |
| #define VPU_VPP_SMOKE3_VAL (0x1d2c << 2) |
| #define VPU_VPP_SMOKE1_H_START_END (0x1d2d << 2) |
| #define VPU_VPP_SMOKE1_V_START_END (0x1d2e << 2) |
| #define VPU_VPP_SMOKE2_H_START_END (0x1d2f << 2) |
| #define VPU_VPP_SMOKE2_V_START_END (0x1d30 << 2) |
| #define VPU_VPP_SMOKE3_H_START_END (0x1d31 << 2) |
| #define VPU_VPP_SMOKE3_V_START_END (0x1d32 << 2) |
| #define VPU_VPP_SCO_FIFO_CTRL (0x1d33 << 2) |
| #define VPU_VPP_HSC_PHASE_CTRL1 (0x1d34 << 2) |
| #define VPU_VPP_HSC_INI_PAT_CTRL (0x1d35 << 2) |
| #define VPU_VPP_VADJ_CTRL (0x1d40 << 2) |
| #define VPU_VPP_VADJ1_Y (0x1d41 << 2) |
| #define VPU_VPP_VADJ1_MA_MB (0x1d42 << 2) |
| #define VPU_VPP_VADJ1_MC_MD (0x1d43 << 2) |
| #define VPU_VPP_VADJ2_Y (0x1d44 << 2) |
| #define VPU_VPP_VADJ2_MA_MB (0x1d45 << 2) |
| #define VPU_VPP_VADJ2_MC_MD (0x1d46 << 2) |
| #define VPU_VPP_HSHARP_CTRL (0x1d50 << 2) |
| #define VPU_VPP_HSHARP_LUMA_THRESH01 (0x1d51 << 2) |
| #define VPU_VPP_HSHARP_LUMA_THRESH23 (0x1d52 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_THRESH01 (0x1d53 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_THRESH23 (0x1d54 << 2) |
| #define VPU_VPP_HSHARP_LUMA_GAIN (0x1d55 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_GAIN (0x1d56 << 2) |
| #define VPU_VPP_MATRIX_PROBE_COLOR (0x1d5c << 2) |
| #define VPU_VPP_MATRIX_HL_COLOR (0x1d5d << 2) |
| #define VPU_VPP_MATRIX_PROBE_POS (0x1d5e << 2) |
| #define VPU_VPP_MATRIX_CTRL (0x1d5f << 2) |
| #define VPU_VPP_MATRIX_COEF00_01 (0x1d60 << 2) |
| #define VPU_VPP_MATRIX_COEF02_10 (0x1d61 << 2) |
| #define VPU_VPP_MATRIX_COEF11_12 (0x1d62 << 2) |
| #define VPU_VPP_MATRIX_COEF20_21 (0x1d63 << 2) |
| #define VPU_VPP_MATRIX_COEF22 (0x1d64 << 2) |
| #define VPU_VPP_MATRIX_OFFSET0_1 (0x1d65 << 2) |
| #define VPU_VPP_MATRIX_OFFSET2 (0x1d66 << 2) |
| #define VPU_VPP_MATRIX_PRE_OFFSET0_1 (0x1d67 << 2) |
| #define VPU_VPP_MATRIX_PRE_OFFSET2 (0x1d68 << 2) |
| #define VPU_VPP_DUMMY_DATA1 (0x1d69 << 2) |
| #define VPU_VPP_GAINOFF_CTRL0 (0x1d6a << 2) |
| #define VPU_VPP_GAINOFF_CTRL1 (0x1d6b << 2) |
| #define VPU_VPP_GAINOFF_CTRL2 (0x1d6c << 2) |
| #define VPU_VPP_GAINOFF_CTRL3 (0x1d6d << 2) |
| #define VPU_VPP_GAINOFF_CTRL4 (0x1d6e << 2) |
| #define VPU_VPP_CHROMA_ADDR_PORT (0x1d70 << 2) |
| #define VPU_VPP_CHROMA_DATA_PORT (0x1d71 << 2) |
| #define VPU_VPP_GCLK_CTRL0 (0x1d72 << 2) |
| #define VPU_VPP_GCLK_CTRL1 (0x1d73 << 2) |
| #define VPU_VPP_SC_GCLK_CTRL (0x1d74 << 2) |
| #define VPU_VPP_MISC1 (0x1d76 << 2) |
| #define VPU_VPP_BLACKEXT_CTRL (0x1d80 << 2) |
| #define VPU_VPP_DNLP_CTRL_00 (0x1d81 << 2) |
| #define VPU_VPP_DNLP_CTRL_01 (0x1d82 << 2) |
| #define VPU_VPP_DNLP_CTRL_02 (0x1d83 << 2) |
| #define VPU_VPP_DNLP_CTRL_03 (0x1d84 << 2) |
| #define VPU_VPP_DNLP_CTRL_04 (0x1d85 << 2) |
| #define VPU_VPP_DNLP_CTRL_05 (0x1d86 << 2) |
| #define VPU_VPP_DNLP_CTRL_06 (0x1d87 << 2) |
| #define VPU_VPP_DNLP_CTRL_07 (0x1d88 << 2) |
| #define VPU_VPP_DNLP_CTRL_08 (0x1d89 << 2) |
| #define VPU_VPP_DNLP_CTRL_09 (0x1d8a << 2) |
| #define VPU_VPP_DNLP_CTRL_10 (0x1d8b << 2) |
| #define VPU_VPP_DNLP_CTRL_11 (0x1d8c << 2) |
| #define VPU_VPP_DNLP_CTRL_12 (0x1d8d << 2) |
| #define VPU_VPP_DNLP_CTRL_13 (0x1d8e << 2) |
| #define VPU_VPP_DNLP_CTRL_14 (0x1d8f << 2) |
| #define VPU_VPP_DNLP_CTRL_15 (0x1d90 << 2) |
| #define VPU_VPP_PEAKING_HGAIN (0x1d91 << 2) |
| #define VPU_VPP_PEAKING_VGAIN (0x1d92 << 2) |
| #define VPU_VPP_PEAKING_NLP_1 (0x1d93 << 2) |
| #define VPU_VPP_PEAKING_NLP_2 (0x1d94 << 2) |
| #define VPU_VPP_PEAKING_NLP_3 (0x1d95 << 2) |
| #define VPU_VPP_PEAKING_NLP_4 (0x1d96 << 2) |
| #define VPU_VPP_PEAKING_NLP_5 (0x1d97 << 2) |
| #define VPU_VPP_SHARP_LIMIT (0x1d98 << 2) |
| #define VPU_VPP_VLTI_CTRL (0x1d99 << 2) |
| #define VPU_VPP_HLTI_CTRL (0x1d9a << 2) |
| #define VPU_VPP_CTI_CTRL (0x1d9b << 2) |
| #define VPU_VPP_BLUE_STRETCH_1 (0x1d9c << 2) |
| #define VPU_VPP_BLUE_STRETCH_2 (0x1d9d << 2) |
| #define VPU_VPP_BLUE_STRETCH_3 (0x1d9e << 2) |
| #define VPU_VPP_CCORING_CTRL (0x1da0 << 2) |
| #define VPU_VPP_VE_ENABLE_CTRL (0x1da1 << 2) |
| #define VPU_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x1da2 << 2) |
| #define VPU_VPP_VE_DEMO_CENTER_BAR (0x1da3 << 2) |
| #define VPU_VPP_VE_H_V_SIZE (0x1da4 << 2) |
| #define VPU_VPP_VDO_MEAS_CTRL (0x1da8 << 2) |
| #define VPU_VPP_VDO_MEAS_VS_COUNT_HI (0x1da9 << 2) |
| #define VPU_VPP_VDO_MEAS_VS_COUNT_LO (0x1daa << 2) |
| #define VPU_VPP_INPUT_CTRL (0x1dab << 2) |
| #define VPU_VPP_CTI_CTRL2 (0x1dac << 2) |
| #define VPU_VPP_PEAKING_SAT_THD1 (0x1dad << 2) |
| #define VPU_VPP_PEAKING_SAT_THD2 (0x1dae << 2) |
| #define VPU_VPP_PEAKING_SAT_THD3 (0x1daf << 2) |
| #define VPU_VPP_PEAKING_SAT_THD4 (0x1db0 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD5 (0x1db1 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD6 (0x1db2 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD7 (0x1db3 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD8 (0x1db4 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD9 (0x1db5 << 2) |
| #define VPU_VPP_PEAKING_GAIN_ADD1 (0x1db6 << 2) |
| #define VPU_VPP_PEAKING_GAIN_ADD2 (0x1db7 << 2) |
| #define VPU_VPP_PEAKING_DNLP (0x1db8 << 2) |
| #define VPU_VPP_SHARP_DEMO_WIN_CTRL1 (0x1db9 << 2) |
| #define VPU_VPP_SHARP_DEMO_WIN_CTRL2 (0x1dba << 2) |
| #define VPU_VPP_FRONT_HLTI_CTRL (0x1dbb << 2) |
| #define VPU_VPP_FRONT_CTI_CTRL (0x1dbc << 2) |
| #define VPU_VPP_FRONT_CTI_CTRL2 (0x1dbd << 2) |
| #define VPU_VPP_OSD_VSC_PHASE_STEP (0x1dc0 << 2) |
| #define VPU_VPP_OSD_VSC_INI_PHASE (0x1dc1 << 2) |
| #define VPU_VPP_OSD_VSC_CTRL0 (0x1dc2 << 2) |
| #define VPU_VPP_OSD_HSC_PHASE_STEP (0x1dc3 << 2) |
| #define VPU_VPP_OSD_HSC_INI_PHASE (0x1dc4 << 2) |
| #define VPU_VPP_OSD_HSC_CTRL0 (0x1dc5 << 2) |
| #define VPU_VPP_OSD_HSC_INI_PAT_CTRL (0x1dc6 << 2) |
| #define VPU_VPP_OSD_SC_DUMMY_DATA (0x1dc7 << 2) |
| #define VPU_VPP_OSD_SC_CTRL0 (0x1dc8 << 2) |
| #define VPU_VPP_OSD_SCI_WH_M1 (0x1dc9 << 2) |
| #define VPU_VPP_OSD_SCO_H_START_END (0x1dca << 2) |
| #define VPU_VPP_OSD_SCO_V_START_END (0x1dcb << 2) |
| #define VPU_VPP_OSD_SCALE_COEF_IDX (0x1dcc << 2) |
| #define VPU_VPP_OSD_SCALE_COEF (0x1dcd << 2) |
| #define VPU_VPP_INT_LINE_NUM (0x1dce << 2) |
| |
| /// RDMA Related Registers |
| #define VPU_RDMA_AHB_START_ADDR_MAN (0x1100 << 2) |
| #define VPU_RDMA_AHB_END_ADDR_MAN (0x1101 << 2) |
| #define VPU_RDMA_AHB_START_ADDR_1 (0x1102 << 2) |
| #define VPU_RDMA_AHB_END_ADDR_1 (0x1103 << 2) |
| #define VPU_RDMA_AHB_START_ADDR_2 (0x1104 << 2) |
| #define VPU_RDMA_AHB_END_ADDR_2 (0x1105 << 2) |
| #define VPU_RDMA_AHB_START_ADDR_3 (0x1106 << 2) |
| #define VPU_RDMA_AHB_END_ADDR_3 (0x1107 << 2) |
| #define VPU_RDMA_AHB_START_ADDR_4 (0x1108 << 2) |
| #define VPU_RDMA_AHB_END_ADDR_4 (0x1109 << 2) |
| #define VPU_RDMA_AHB_START_ADDR_5 (0x110a << 2) |
| #define VPU_RDMA_AHB_END_ADDR_5 (0x110b << 2) |
| #define VPU_RDMA_AHB_START_ADDR_6 (0x110c << 2) |
| #define VPU_RDMA_AHB_END_ADDR_6 (0x110d << 2) |
| #define VPU_RDMA_AHB_START_ADDR_7 (0x110e << 2) |
| #define VPU_RDMA_AHB_END_ADDR_7 (0x110f << 2) |
| #define VPU_RDMA_AHB_START_ADDR(x) (VPU_RDMA_AHB_START_ADDR_MAN + ((x + 1) << 3)) |
| #define VPU_RDMA_AHB_END_ADDR(x) (VPU_RDMA_AHB_END_ADDR_MAN + ((x + 1) << 3)) |
| #define VPU_RDMA_ACCESS_AUTO (0x1110 << 2) |
| #define VPU_RDMA_ACCESS_AUTO2 (0x1111 << 2) |
| #define VPU_RDMA_ACCESS_AUTO3 (0x1112 << 2) |
| #define VPU_RDMA_ACCESS_MAN (0x1113 << 2) |
| #define VPU_RDMA_CTRL (0x1114 << 2) |
| #define VPU_RDMA_STATUS (0x1115 << 2) |
| #define VPU_RDMA_STATUS2 (0x1116 << 2) |
| #define VPU_RDMA_STATUS3 (0x1117 << 2) |
| |
| // VPU_RDMA_ACCESS_AUTO Bit Definition |
| #define RDMA_ACCESS_AUTO_INT_EN_ALL (0xFF << 8) |
| #define RDMA_ACCESS_AUTO_INT_EN(channel) (1 << ((channel + 1) << 3)) |
| #define RDMA_ACCESS_AUTO_WRITE(channel) (1 << ((channel + 1) + 4)) |
| #define RDMA_ACCESS_AUTO_INCREMENT(channel) (1 << (channel + 1)) |
| |
| // VPU_RDMA_CTRL Bit Definition |
| #define RMA_CTR_ALL_INT_DONE (0xFF << 24) |
| #define RDMA_CTRL_INT_DONE(channel) (1 << (24 + (channel + 1))) |
| #define RDMA_CTRL_WRITE_URGENT (1 << 7) |
| #define RDMA_CTRL_READ_URGENT (1 << 6) |
| #define RDMA_CTRL_WRITE_BURST_SIZE_4x16B (0 << 4) |
| #define RDMA_CTRL_WRITE_BURST_SIZE_8x16B (1 << 4) |
| #define RDMA_CTRL_WRITE_BURST_SIZE_12x16B (2 << 4) |
| #define RDMA_CTRL_WRITE_BURST_SIZE_16x16B (3 << 4) |
| #define RDMA_CTRL_READ_BURST_SIZE_4x16B (0 << 4) |
| #define RDMA_CTRL_READ_BURST_SIZE_8x16B (1 << 4) |
| #define RDMA_CTRL_READ_BURST_SIZE_12x16B (2 << 4) |
| #define RDMA_CTRL_READ_BURST_SIZE_16x16B (3 << 4) |
| #define RDMA_CTRL_RESET (1 << 1) |
| #define RDMA_CTRL_CLK_GATE_EN (1 << 0) |
| |
| // VPU_RDMA_STATUS Bit Definition |
| #define RDMA_STATUS_BUSY (0x0003C0FF) |
| #define RDMA_STATUS_DONE(channel) (1 << (24 + (channel + 1))) |
| |
| __BEGIN_CDECLS |
| |
| // RDMA Channel used by OSD/VD. |
| constexpr uint8_t kMaxRetries = 100; |
| constexpr uint8_t kMaxRdmaChannels = 3; |
| // spread channels 512B apart (make sure it's greater than a cache line size) |
| constexpr size_t kChannelBaseOffset = 512; |
| |
| struct RdmaTable { |
| uint32_t reg; |
| uint32_t val; |
| }; |
| |
| struct RdmaChannelContainer { |
| zx_paddr_t phys_offset; // offset into physical address |
| uint8_t* virt_offset; // offset into virtual address (vmar buf) |
| bool active; // indicated whether channel is being used or not |
| }; |
| |
| struct RdmaContainer { |
| zx_handle_t rdma_vmo; |
| zx_paddr_t rdma_phys; |
| uint8_t* rdma_vbuf; |
| zx_handle_t rdma_pmt; |
| // container that holds channel specific properties |
| RdmaChannelContainer rdma_chnl_container[kMaxRdmaChannels]; |
| }; |
| |
| __END_CDECLS |
| |
