system/banjo/ddk-protocol-pciroot/pciroot.banjo

// Copyright 2018 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

library ddk.protocol.pciroot;
// hopefully this includes ddk
using zircon.hw.pci;
using zx;

// These may need to remain entirely in the kernel since platform_ctx
// is an exposed pointer, and we will need a kernel shim for IRQ processing
// anyway.
struct MsiBlock {
    uint64 reserved;
};

/// This structure is the primary means of passing PCI platform information from
/// the platform bus implementation to the PCI bus driver. If an ecam is found
/// for this segment group then a handle to a VMO for it will be provided via
/// |ecam_vmo|. The VMO's start address will correspond to the base address of
/// the bus number specified by |start_bus_num|.
struct PciPlatformInfo {
    string:32 name;
    uint8 start_bus_num;
    uint8 end_bus_num;
    uint16 segment_group;
    handle<vmo> ecam_vmo;
};

/// TODO(cja): Fill this in for IRQ metadata
struct PciIrqInfo {
    uint64 reserved;
};

/// TODO(cja): possibly necessary now that IO config access is proxied to pciroot.
enum PciAddressSpace : uint8 {
    MMIO = 0;
    IO = 0x1;
};

[Layout = "ddk-protocol"]
interface Pciroot {
    /// Legacy methods
    GetAuxdata(string args) -> (zx.status s, vector<voidptr> data);
    GetBti(uint32 bdf, uint32 index) -> (zx.status s, handle<bti> bti);
    /// Get the platform information structure from the pciroot protocol to be used for bus init.
    GetPciPlatformInfo() -> (zx.status s, PciPlatformInfo info);
    /// Get IRQ information, including the swizzle table.
    GetPciIrqInfo() -> (zx.status s, PciIrqInfo info);
    /// Returns true if the bus driver should proxy all device config access to pciroot. This is
    /// necessary in cases of IO config on x86, or for controllers that require configuration to
    /// map in device config headers.
    DriverShouldProxyConfig() -> (bool use_proxy);
    /// Read 8 bytes from config space for device at bdf address |address|, offset |offset|.
    ConfigRead8(zircon.hw.pci.PciBdf address, uint16 offset) -> (zx.status s, uint8 value);
    /// Read 16 bytes from config space for device at bdf address |address|, offset |offset|.
    ConfigRead16(zircon.hw.pci.PciBdf address, uint16 offset) -> (zx.status s, uint16 value);
    /// Read 32 bytes from config space for device at bdf address |address|, offset |offset|.
    ConfigRead32(zircon.hw.pci.PciBdf address, uint16 offset) -> (zx.status s, uint32 value);
    /// Write 8 bytes to config space for device at bdf |address| offset |offset|.
    ConfigWrite8(zircon.hw.pci.PciBdf address, uint16 offset, uint8 value) -> (zx.status s);
    /// Write 16 bytes to config space for device at bdf |address| offset |offset|.
    ConfigWrite16(zircon.hw.pci.PciBdf address, uint16 offset, uint16 value) -> (zx.status s);
    /// Write 32 bytes to config space for device at bdf |address| offset |offset|.
    ConfigWrite32(zircon.hw.pci.PciBdf address, uint16 offset, uint32 value) -> (zx.status s);
    /// Placeholder methods for MSI configuration. May be removed.
    MsiAllocBlock(uint64 requested_irqs, bool can_target_64bit) -> (zx.status s, MsiBlock block);
    MsiFreeBlock(MsiBlock block) -> (zx.status s);
    MsiMaskUnmask(uint64 msi_id, bool mask) -> (zx.status s);
    /// Request address space reservations from platform bus to use for mapping bars / bridges
    /// TODO(cja): parameters/return are not finalized.
    GetAddressSpace(usize len, PciAddressSpace type, bool low) -> (zx.status s, zx.paddr base);
    /// Free address space reserved via GetAddressSpace from platform bus to use for mapping bars / bridges
    /// TODO(cja): parameters/return are not finalized.
    FreeAddressSpace(zx.paddr base, usize len, PciAddressSpace type) -> (zx.status s);
};