commit eeccab3395d5ded3659d236d539bf24de5e89889
author Yvonne Yip <yky@google.com> Wed Aug 15 13:40:29 2018 -0700
committer Yvonne Yip <yky@google.com> Wed Aug 15 13:40:29 2018 -0700
tree 9b4d3e79cf9f52e5b3d15b6b19170b93587c4381
parent f813a098affe323fb5c0ff28ff855fcff41c3bda

do not check in

Change-Id: I634fb8cd2c6689a5473e20fd4786472cd11904b9

system/dev/codec/alc5514/alc5514.cpp

diff --git a/system/dev/codec/alc5514/alc5514.cpp b/system/dev/codec/alc5514/alc5514.cpp
index 4744089..3a2f0bf 100644
--- a/system/dev/codec/alc5514/alc5514.cpp
+++ b/system/dev/codec/alc5514/alc5514.cpp
@@ -184,6 +184,61 @@
     UpdateReg(DOWNFILTER1_CTRL2, DOWNFILTER_CTRL_AD_AD_GAIN_MASK, 0x6E);
 
     // Power up
+    UpdateReg(PWR_ANA1,
+                        PWR_ANA1_POW_CKDET |
+                        PWR_ANA1_POW_LDO18_IN |
+                        PWR_ANA1_POW_LDO18_ADC |
+                        PWR_ANA1_POW_LDO21 |
+                        PWR_ANA1_POW_BG_LDO18 |
+                        PWR_ANA1_POW_BG_LDO21,
+                        PWR_ANA1_POW_CKDET |
+                        PWR_ANA1_POW_LDO18_IN |
+                        PWR_ANA1_POW_LDO18_ADC |
+                        PWR_ANA1_POW_LDO21 |
+                        PWR_ANA1_POW_BG_LDO18 |
+                        PWR_ANA1_POW_BG_LDO21);
+    UpdateReg(PWR_ANA2,
+                       PWR_ANA2_POW_PLL2 |
+                       PWR_ANA2_POW_PLL2_LDO |
+                       PWR_ANA2_POW_PLL1 |
+                       PWR_ANA2_POW_PLL1_LDO |
+                       PWR_ANA2_POW_BG_MBIAS |
+                       PWR_ANA2_POW_MBIAS |
+                       PWR_ANA2_POW_VREF2 |
+                       PWR_ANA2_POW_VREF1 |
+                       PWR_ANA2_POWR_LDO16 |
+                       PWR_ANA2_POWL_LDO16 |
+                       PWR_ANA2_POW_ADC2 |
+                       PWR_ANA2_POW_INPUT_BUF |
+                       PWR_ANA2_POW_ADC1_R |
+                       PWR_ANA2_POW_ADC1_L |
+                       PWR_ANA2_POW2_BSTR |
+                       PWR_ANA2_POW2_BSTL |
+                       PWR_ANA2_POW_BSTR |
+                       PWR_ANA2_POW_BSTL |
+                       PWR_ANA2_POW_ADCFEDR |
+                       PWR_ANA2_POW_ADCFEDL,
+                       PWR_ANA2_POW_PLL2 |
+                       PWR_ANA2_POW_PLL2_LDO |
+                       PWR_ANA2_POW_PLL1 |
+                       PWR_ANA2_POW_PLL1_LDO |
+                       PWR_ANA2_POW_BG_MBIAS |
+                       PWR_ANA2_POW_MBIAS |
+                       PWR_ANA2_POW_VREF2 |
+                       PWR_ANA2_POW_VREF1 |
+                       PWR_ANA2_POWR_LDO16 |
+                       PWR_ANA2_POWL_LDO16 |
+                       PWR_ANA2_POW_ADC2 |
+                       PWR_ANA2_POW_INPUT_BUF |
+                       PWR_ANA2_POW_ADC1_R |
+                       PWR_ANA2_POW_ADC1_L |
+                       PWR_ANA2_POW2_BSTR |
+                       PWR_ANA2_POW2_BSTL |
+                       PWR_ANA2_POW_BSTR |
+                       PWR_ANA2_POW_BSTL |
+                       PWR_ANA2_POW_ADCFEDR |
+                       PWR_ANA2_POW_ADCFEDL);
+#if 0
     WriteReg(PWR_ANA1, PWR_ANA1_EN_SLEEP_RESET |
                        PWR_ANA1_DMIC_DATA_IN2 |
                        PWR_ANA1_POW_CKDET |
@@ -215,6 +270,7 @@
                        PWR_ANA2_POW_BSTL |
                        PWR_ANA2_POW_ADCFEDR |
                        PWR_ANA2_POW_ADCFEDL);
+#endif
 
     // Enable DMIC1/2, ADC1, DownFilter0/1 clock
     uint32_t clk_enable = CLK_CTRL1_CLK_AD_ANA1_EN |