diff --git a/system/dev/board/imx8mevk/imx8mevk-usb.c b/system/dev/board/imx8mevk/imx8mevk-usb.c
index 1c11a96..8af1074 100644
--- a/system/dev/board/imx8mevk/imx8mevk-usb.c
+++ b/system/dev/board/imx8mevk/imx8mevk-usb.c
@@ -123,20 +123,21 @@
     volatile void* regs = io_buffer_virt(&usb_buf);
     //TODO: More stuff might be needed if we were to boot from our own bootloader.
     reg = readl(regs + USB_PHY_CTRL1);
-    reg &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
-    reg |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+    reg &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+    reg |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
     writel(reg, regs + USB_PHY_CTRL1);
 
     reg = readl(regs + USB_PHY_CTRL0);
-    reg |= PHY_CTRL0_REF_SSP_EN;
+    reg |= USB_PHY_CTRL0_REF_SSP_EN;
     writel(reg, regs + USB_PHY_CTRL0);
 
     reg = readl(regs + USB_PHY_CTRL2);
-    reg |= PHY_CTRL2_TXENABLEN0;
+    reg |= USB_PHY_CTRL2_TXENABLEN0;
     writel(reg, regs + USB_PHY_CTRL2);
 
     reg = readl(regs + USB_PHY_CTRL1);
-    reg &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+    reg &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
     writel(reg, regs + USB_PHY_CTRL1);
 
     io_buffer_release(&usb_buf);
@@ -197,6 +198,7 @@
         zxlogf(ERROR, "imx_usb_init could not add usb2_dev: %d\n", status);
         return status;
     }
+
     return ZX_OK;
 }
 
diff --git a/system/dev/lib/imx8m/include/soc/imx8m/imx8m-hw.h b/system/dev/lib/imx8m/include/soc/imx8m/imx8m-hw.h
index 6d50c6e..61a8ae8a 100644
--- a/system/dev/lib/imx8m/include/soc/imx8m/imx8m-hw.h
+++ b/system/dev/lib/imx8m/include/soc/imx8m/imx8m-hw.h
@@ -258,11 +258,12 @@
 
 /* USB PHY CTRL Registers (undocumented) */
 #define USB_PHY_CTRL0               (0xF0040)
-#define PHY_CTRL0_REF_SSP_EN        (1 << 2)
+#define USB_PHY_CTRL0_REF_SSP_EN    (1 << 2)
 #define USB_PHY_CTRL1               (0xF0044)
-#define PHY_CTRL1_RESET             (1 << 0)
-#define PHY_CTRL1_ATERESET          (1 << 3)
-#define PHY_CTRL1_VDATSRCENB0       (1 << 19)
-#define PHY_CTRL1_VDATDETENB0       (1 << 20)
+#define USB_PHY_CTRL1_RESET         (1 << 0)
+#define USB_PHY_CTRL1_COMMONONN     (1 << 1)
+#define USB_PHY_CTRL1_ATERESET      (1 << 3)
+#define USB_PHY_CTRL1_VDATSRCENB0   (1 << 19)
+#define USB_PHY_CTRL1_VDATDETENB0   (1 << 20)
 #define USB_PHY_CTRL2               (0xF0048)
-#define PHY_CTRL2_TXENABLEN0        (1 << 8)
+#define USB_PHY_CTRL2_TXENABLEN0    (1 << 8)
diff --git a/system/dev/usb/dwc3/dwc3-regs.h b/system/dev/usb/dwc3/dwc3-regs.h
index b75c9d1..1530126 100644
--- a/system/dev/usb/dwc3/dwc3-regs.h
+++ b/system/dev/usb/dwc3/dwc3-regs.h
@@ -222,7 +222,7 @@
 #define GUSB2PHYACC_ULPI(n) (0xc280 + 4 * (n))  // Global USB 2.0 UTMI PHY Vendor Control Register
 
 #define GUSB3PIPECTL(n)     (0xc2c0 + 4 * (n))      // Global USB 3.1 PIPE Control Register
-#define GUSB3PIPECTL_PHY_SOFT_RST               (1 << 31)   // USB3 PHY Soft Reset
+#define GUSB3PIPECTL_PHYSOFTRST                 (1 << 31)   // USB3 PHY Soft Reset
 #define GUSB3PIPECTL_HST_PRT_CMPL               (1 << 30)
 #define GUSB3PIPECTL_DIS_RX_DET_P3              (1 << 28)
 #define GUSB3PIPECTL_UX_EXIT_IN_PX              (1 << 27)
diff --git a/system/dev/usb/dwc3/dwc3.c b/system/dev/usb/dwc3/dwc3.c
index 1254507..823fb56 100644
--- a/system/dev/usb/dwc3/dwc3.c
+++ b/system/dev/usb/dwc3/dwc3.c
@@ -89,6 +89,39 @@
 
     mtx_lock(&dwc->lock);
 
+    temp = DWC3_READ32(mmio + DCTL);
+    temp |= DCTL_CSFTRST;
+    DWC3_WRITE32(mmio + DCTL, temp);
+    dwc3_wait_bits(mmio + DCTL, DCTL_CSFTRST, 0);
+
+    temp = DWC3_READ32(mmio + GCTL);
+    temp |= GCTL_CORESOFTRESET;
+    DWC3_WRITE32(mmio + GCTL, temp);
+
+    /* Assert USB2 PHY reset */
+    temp = DWC3_READ32(mmio + GUSB2PHYCFG(0));
+    temp |= GUSB2PHYCFG_PHYSOFTRST;
+    DWC3_WRITE32(mmio + GUSB2PHYCFG(0), temp);
+
+    usleep(100 * 1000);
+
+    /* Clear USB3 PHY reset */
+    temp = DWC3_READ32(mmio + GUSB3PIPECTL(0));
+    temp &= ~GUSB3PIPECTL_PHYSOFTRST;
+    DWC3_WRITE32(mmio + GUSB3PIPECTL(0), temp);
+
+    /* Clear USB2 PHY reset */
+    temp = DWC3_READ32(mmio + GUSB2PHYCFG(0));
+    temp &= ~GUSB2PHYCFG_PHYSOFTRST;
+    DWC3_WRITE32(mmio + GUSB2PHYCFG(0), temp);
+
+    usleep(100 * 1000);
+
+    /* After PHYs are stable we can take Core out of reset state */
+    temp = DWC3_READ32(mmio + GCTL);
+    temp &= ~GCTL_CORESOFTRESET;
+    DWC3_WRITE32(mmio + GCTL, temp);
+
     // configure and enable PHYs
     temp = DWC3_READ32(mmio + GUSB2PHYCFG(0));
     temp &= ~(GUSB2PHYCFG_USBTRDTIM_MASK | GUSB2PHYCFG_SUSPENDUSB20);