| commit | 47f693fd89b5d961e7097674c21263060299b10c | [log] [tgz] |
|---|---|---|
| author | Peter Johnson <peter@tortall.net> | Sun Jul 03 01:48:44 2011 -0700 |
| committer | Peter Johnson <peter@tortall.net> | Sun Jul 03 01:48:44 2011 -0700 |
| tree | 7c70ba9389bddbae2605c7ee84a1384e4e90bdc4 | |
| parent | 0614dede9bb5b285804882cf71479f4e9757ec2f [diff] |
Add Intel BMI1, BMI2, INVPCID, LZCNT instructions. Reference: http://www.intel.com/software/avx rev11 spec Also add appropriate CPU bits and directive handling for these. Currently we have no good way of handling an "or" of instruction bits (in this case needed for LZCNT, where it's either AMD or LZCNT). For now, make it LZCNT only. Contributed by: Mark Charney <mark.charney@intel.com> Part of [#227].