hw/ssi/stm32f2xx_spi.c - third_party/qemu - Git at Google

 /*
  * STM32F405 SPI
  *
  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */

 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "hw/ssi/stm32f2xx_spi.h"
 #include "migration/vmstate.h"

 #ifndef STM_SPI_ERR_DEBUG
 #define STM_SPI_ERR_DEBUG 0
 #endif

 #define DB_PRINT_L(lvl, fmt, args...) do { \
     if (STM_SPI_ERR_DEBUG >= lvl) { \
         qemu_log("%s: " fmt, __func__, ## args); \
     } \
 } while (0)

 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)

 static void stm32f2xx_spi_reset(DeviceState *dev)
 {
     STM32F2XXSPIState *s = STM32F2XX_SPI(dev);

     s->spi_cr1 = 0x00000000;
     s->spi_cr2 = 0x00000000;
     s->spi_sr = 0x0000000A;
     s->spi_dr = 0x0000000C;
     s->spi_crcpr = 0x00000007;
     s->spi_rxcrcr = 0x00000000;
     s->spi_txcrcr = 0x00000000;
     s->spi_i2scfgr = 0x00000000;
     s->spi_i2spr = 0x00000002;
 }

 static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s)
 {
     DB_PRINT("Data to send: 0x%x\n", s->spi_dr);

     s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
     s->spi_sr |= STM_SPI_SR_RXNE;

     DB_PRINT("Data received: 0x%x\n", s->spi_dr);
 }

 static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
                                      unsigned int size)
 {
     STM32F2XXSPIState *s = opaque;

     DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);

     switch (addr) {
     case STM_SPI_CR1:
         return s->spi_cr1;
     case STM_SPI_CR2:
         qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
                       __func__);
         return s->spi_cr2;
     case STM_SPI_SR:
         return s->spi_sr;
     case STM_SPI_DR:
         stm32f2xx_spi_transfer(s);
         s->spi_sr &= ~STM_SPI_SR_RXNE;
         return s->spi_dr;
     case STM_SPI_CRCPR:
         qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
                       "are included for compatibility\n", __func__);
         return s->spi_crcpr;
     case STM_SPI_RXCRCR:
         qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
                       "are included for compatibility\n", __func__);
         return s->spi_rxcrcr;
     case STM_SPI_TXCRCR:
         qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
                       "are included for compatibility\n", __func__);
         return s->spi_txcrcr;
     case STM_SPI_I2SCFGR:
         qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
                       "are included for compatibility\n", __func__);
         return s->spi_i2scfgr;
     case STM_SPI_I2SPR:
         qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
                       "are included for compatibility\n", __func__);
         return s->spi_i2spr;
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
                       __func__, addr);
     }

     return 0;
 }

 static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
                                 uint64_t val64, unsigned int size)
 {
     STM32F2XXSPIState *s = opaque;
     uint32_t value = val64;

     DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);

     switch (addr) {
     case STM_SPI_CR1:
         s->spi_cr1 = value;
         return;
     case STM_SPI_CR2:
         qemu_log_mask(LOG_UNIMP, "%s: " \
                       "Interrupts and DMA are not implemented\n", __func__);
         s->spi_cr2 = value;
         return;
     case STM_SPI_SR:
         /* Read only register, except for clearing the CRCERR bit, which
          * is not supported
          */
         return;
     case STM_SPI_DR:
         s->spi_dr = value;
         stm32f2xx_spi_transfer(s);
         return;
     case STM_SPI_CRCPR:
         qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
         return;
     case STM_SPI_RXCRCR:
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
                       "0x%" HWADDR_PRIx "\n", __func__, addr);
         return;
     case STM_SPI_TXCRCR:
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
                       "0x%" HWADDR_PRIx "\n", __func__, addr);
         return;
     case STM_SPI_I2SCFGR:
         qemu_log_mask(LOG_UNIMP, "%s: " \
                       "I2S is not implemented\n", __func__);
         return;
     case STM_SPI_I2SPR:
         qemu_log_mask(LOG_UNIMP, "%s: " \
                       "I2S is not implemented\n", __func__);
         return;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
     }
 }

 static const MemoryRegionOps stm32f2xx_spi_ops = {
     .read = stm32f2xx_spi_read,
     .write = stm32f2xx_spi_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };

 static const VMStateDescription vmstate_stm32f2xx_spi = {
     .name = TYPE_STM32F2XX_SPI,
     .version_id = 1,
     .minimum_version_id = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_sr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_dr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState),
         VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState),
         VMSTATE_END_OF_LIST()
     }
 };

 static void stm32f2xx_spi_init(Object *obj)
 {
     STM32F2XXSPIState *s = STM32F2XX_SPI(obj);
     DeviceState *dev = DEVICE(obj);

     memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
                           TYPE_STM32F2XX_SPI, 0x400);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

     s->ssi = ssi_create_bus(dev, "ssi");
 }

 static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);

     dc->reset = stm32f2xx_spi_reset;
     dc->vmsd = &vmstate_stm32f2xx_spi;
 }

 static const TypeInfo stm32f2xx_spi_info = {
     .name          = TYPE_STM32F2XX_SPI,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(STM32F2XXSPIState),
     .instance_init = stm32f2xx_spi_init,
     .class_init    = stm32f2xx_spi_class_init,
 };

 static void stm32f2xx_spi_register_types(void)
 {
     type_register_static(&stm32f2xx_spi_info);
 }

 type_init(stm32f2xx_spi_register_types)
	/*
	* STM32F405 SPI
	*
	* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
	*
	* Permission is hereby granted, free of charge, to any person obtaining a copy
	* of this software and associated documentation files (the "Software"), to deal
	* in the Software without restriction, including without limitation the rights
	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	* copies of the Software, and to permit persons to whom the Software is
	* furnished to do so, subject to the following conditions:
	*
	* The above copyright notice and this permission notice shall be included in
	* all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	* THE SOFTWARE.
	*/

	#include "qemu/osdep.h"
	#include "qemu/log.h"
	#include "qemu/module.h"
	#include "hw/ssi/stm32f2xx_spi.h"
	#include "migration/vmstate.h"

	#ifndef STM_SPI_ERR_DEBUG
	#define STM_SPI_ERR_DEBUG 0
	#endif

	#define DB_PRINT_L(lvl, fmt, args...) do { \
	if (STM_SPI_ERR_DEBUG >= lvl) { \
	qemu_log("%s: " fmt, __func__, ## args); \
	} \
	} while (0)

	#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)

	static void stm32f2xx_spi_reset(DeviceState *dev)
	{
	STM32F2XXSPIState *s = STM32F2XX_SPI(dev);

	s->spi_cr1 = 0x00000000;
	s->spi_cr2 = 0x00000000;
	s->spi_sr = 0x0000000A;
	s->spi_dr = 0x0000000C;
	s->spi_crcpr = 0x00000007;
	s->spi_rxcrcr = 0x00000000;
	s->spi_txcrcr = 0x00000000;
	s->spi_i2scfgr = 0x00000000;
	s->spi_i2spr = 0x00000002;
	}

	static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s)
	{
	DB_PRINT("Data to send: 0x%x\n", s->spi_dr);

	s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
	s->spi_sr \|= STM_SPI_SR_RXNE;

	DB_PRINT("Data received: 0x%x\n", s->spi_dr);
	}

	static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
	unsigned int size)
	{
	STM32F2XXSPIState *s = opaque;

	DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);

	switch (addr) {
	case STM_SPI_CR1:
	return s->spi_cr1;
	case STM_SPI_CR2:
	qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
	__func__);
	return s->spi_cr2;
	case STM_SPI_SR:
	return s->spi_sr;
	case STM_SPI_DR:
	stm32f2xx_spi_transfer(s);
	s->spi_sr &= ~STM_SPI_SR_RXNE;
	return s->spi_dr;
	case STM_SPI_CRCPR:
	qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
	"are included for compatibility\n", __func__);
	return s->spi_crcpr;
	case STM_SPI_RXCRCR:
	qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
	"are included for compatibility\n", __func__);
	return s->spi_rxcrcr;
	case STM_SPI_TXCRCR:
	qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
	"are included for compatibility\n", __func__);
	return s->spi_txcrcr;
	case STM_SPI_I2SCFGR:
	qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
	"are included for compatibility\n", __func__);
	return s->spi_i2scfgr;
	case STM_SPI_I2SPR:
	qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
	"are included for compatibility\n", __func__);
	return s->spi_i2spr;
	default:
	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
	__func__, addr);
	}

	return 0;
	}

	static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
	uint64_t val64, unsigned int size)
	{
	STM32F2XXSPIState *s = opaque;
	uint32_t value = val64;

	DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);

	switch (addr) {
	case STM_SPI_CR1:
	s->spi_cr1 = value;
	return;
	case STM_SPI_CR2:
	qemu_log_mask(LOG_UNIMP, "%s: " \
	"Interrupts and DMA are not implemented\n", __func__);
	s->spi_cr2 = value;
	return;
	case STM_SPI_SR:
	/* Read only register, except for clearing the CRCERR bit, which
	* is not supported
	*/
	return;
	case STM_SPI_DR:
	s->spi_dr = value;
	stm32f2xx_spi_transfer(s);
	return;
	case STM_SPI_CRCPR:
	qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
	return;
	case STM_SPI_RXCRCR:
	qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
	"0x%" HWADDR_PRIx "\n", __func__, addr);
	return;
	case STM_SPI_TXCRCR:
	qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
	"0x%" HWADDR_PRIx "\n", __func__, addr);
	return;
	case STM_SPI_I2SCFGR:
	qemu_log_mask(LOG_UNIMP, "%s: " \
	"I2S is not implemented\n", __func__);
	return;
	case STM_SPI_I2SPR:
	qemu_log_mask(LOG_UNIMP, "%s: " \
	"I2S is not implemented\n", __func__);
	return;
	default:
	qemu_log_mask(LOG_GUEST_ERROR,
	"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
	}
	}

	static const MemoryRegionOps stm32f2xx_spi_ops = {
	.read = stm32f2xx_spi_read,
	.write = stm32f2xx_spi_write,
	.endianness = DEVICE_NATIVE_ENDIAN,
	};

	static const VMStateDescription vmstate_stm32f2xx_spi = {
	.name = TYPE_STM32F2XX_SPI,
	.version_id = 1,
	.minimum_version_id = 1,
	.fields = (VMStateField[]) {
	VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_sr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_dr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState),
	VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState),
	VMSTATE_END_OF_LIST()
	}
	};

	static void stm32f2xx_spi_init(Object *obj)
	{
	STM32F2XXSPIState *s = STM32F2XX_SPI(obj);
	DeviceState *dev = DEVICE(obj);

	memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
	TYPE_STM32F2XX_SPI, 0x400);
	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

	s->ssi = ssi_create_bus(dev, "ssi");
	}

	static void stm32f2xx_spi_class_init(ObjectClass klass, void data)
	{
	DeviceClass *dc = DEVICE_CLASS(klass);

	dc->reset = stm32f2xx_spi_reset;
	dc->vmsd = &vmstate_stm32f2xx_spi;
	}

	static const TypeInfo stm32f2xx_spi_info = {
	.name = TYPE_STM32F2XX_SPI,
	.parent = TYPE_SYS_BUS_DEVICE,
	.instance_size = sizeof(STM32F2XXSPIState),
	.instance_init = stm32f2xx_spi_init,
	.class_init = stm32f2xx_spi_class_init,
	};

	static void stm32f2xx_spi_register_types(void)
	{
	type_register_static(&stm32f2xx_spi_info);
	}

	type_init(stm32f2xx_spi_register_types)