hw/arm/stm32f205_soc.c - third_party/qemu - Git at Google

 /*
  * STM32F205 SoC
  *
  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */

 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
 #include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/stm32f205_soc.h"
 #include "hw/qdev-properties.h"
 #include "hw/qdev-clock.h"
 #include "sysemu/sysemu.h"

 /* At the moment only Timer 2 to 5 are modelled */
 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
     0x40012200 };
 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
     0x40003C00 };

 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
 #define ADC_IRQ 18
 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};

 static void stm32f205_soc_initfn(Object *obj)
 {
     STM32F205State *s = STM32F205_SOC(obj);
     int i;

     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

     object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);

     for (i = 0; i < STM_NUM_USARTS; i++) {
         object_initialize_child(obj, "usart[*]", &s->usart[i],
                                 TYPE_STM32F2XX_USART);
     }

     for (i = 0; i < STM_NUM_TIMERS; i++) {
         object_initialize_child(obj, "timer[*]", &s->timer[i],
                                 TYPE_STM32F2XX_TIMER);
     }

     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));

     for (i = 0; i < STM_NUM_ADCS; i++) {
         object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
     }

     for (i = 0; i < STM_NUM_SPIS; i++) {
         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
     }

     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
 }

 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     STM32F205State *s = STM32F205_SOC(dev_soc);
     DeviceState *dev, *armv7m;
     SysBusDevice *busdev;
     int i;

     MemoryRegion *system_memory = get_system_memory();

     /*
      * We use s->refclk internally and only define it with qdev_init_clock_in()
      * so it is correctly parented and not leaked on an init/deinit; it is not
      * intended as an externally exposed clock.
      */
     if (clock_has_source(s->refclk)) {
         error_setg(errp, "refclk clock must not be wired up by the board code");
         return;
     }

     if (!clock_has_source(s->sysclk)) {
         error_setg(errp, "sysclk clock must be wired up by the board code");
         return;
     }

     /*
      * TODO: ideally we should model the SoC RCC and its ability to
      * change the sysclk frequency and define different sysclk sources.
      */

     /* The refclk always runs at frequency HCLK / 8 */
     clock_set_mul_div(s->refclk, 8, 1);
     clock_set_source(s->refclk, s->sysclk);

     memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
                            FLASH_SIZE, &error_fatal);
     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
                              "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);

     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
     memory_region_add_subregion(system_memory, 0, &s->flash_alias);

     memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
                            &error_fatal);
     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);

     armv7m = DEVICE(&s->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 96);
     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
     qdev_prop_set_bit(armv7m, "enable-bitband", true);
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
     qdev_connect_clock_in(armv7m, "refclk", s->refclk);
     object_property_set_link(OBJECT(&s->armv7m), "memory",
                              OBJECT(get_system_memory()), &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
         return;
     }

     /* System configuration controller */
     dev = DEVICE(&s->syscfg);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
         return;
     }
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_mmio_map(busdev, 0, 0x40013800);

     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
         dev = DEVICE(&(s->usart[i]));
         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
             return;
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, usart_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
     }

     /* Timer 2 to 5 */
     for (i = 0; i < STM_NUM_TIMERS; i++) {
         dev = DEVICE(&(s->timer[i]));
         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
             return;
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
     }

     /* ADC 1 to 3 */
     object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
                             &error_abort);
     if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) {
         return;
     }
     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
                           qdev_get_gpio_in(armv7m, ADC_IRQ));

     for (i = 0; i < STM_NUM_ADCS; i++) {
         dev = DEVICE(&(s->adc[i]));
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
             return;
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, adc_addr[i]);
         sysbus_connect_irq(busdev, 0,
                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
     }

     /* SPI 1 and 2 */
     for (i = 0; i < STM_NUM_SPIS; i++) {
         dev = DEVICE(&(s->spi[i]));
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
             return;
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, spi_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
     }
 }

 static Property stm32f205_soc_properties[] = {
     DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
     DEFINE_PROP_END_OF_LIST(),
 };

 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);

     dc->realize = stm32f205_soc_realize;
     device_class_set_props(dc, stm32f205_soc_properties);
 }

 static const TypeInfo stm32f205_soc_info = {
     .name          = TYPE_STM32F205_SOC,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(STM32F205State),
     .instance_init = stm32f205_soc_initfn,
     .class_init    = stm32f205_soc_class_init,
 };

 static void stm32f205_soc_types(void)
 {
     type_register_static(&stm32f205_soc_info);
 }

 type_init(stm32f205_soc_types)
	/*
	* STM32F205 SoC
	*
	* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
	*
	* Permission is hereby granted, free of charge, to any person obtaining a copy
	* of this software and associated documentation files (the "Software"), to deal
	* in the Software without restriction, including without limitation the rights
	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	* copies of the Software, and to permit persons to whom the Software is
	* furnished to do so, subject to the following conditions:
	*
	* The above copyright notice and this permission notice shall be included in
	* all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	* THE SOFTWARE.
	*/

	#include "qemu/osdep.h"
	#include "qapi/error.h"
	#include "qemu/module.h"
	#include "hw/arm/boot.h"
	#include "exec/address-spaces.h"
	#include "hw/arm/stm32f205_soc.h"
	#include "hw/qdev-properties.h"
	#include "hw/qdev-clock.h"
	#include "sysemu/sysemu.h"

	/* At the moment only Timer 2 to 5 are modelled */
	static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
	0x40000800, 0x40000C00 };
	static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
	0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
	static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
	0x40012200 };
	static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
	0x40003C00 };

	static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
	static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
	#define ADC_IRQ 18
	static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};

	static void stm32f205_soc_initfn(Object *obj)
	{
	STM32F205State *s = STM32F205_SOC(obj);
	int i;

	object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

	object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);

	for (i = 0; i < STM_NUM_USARTS; i++) {
	object_initialize_child(obj, "usart[*]", &s->usart[i],
	TYPE_STM32F2XX_USART);
	}

	for (i = 0; i < STM_NUM_TIMERS; i++) {
	object_initialize_child(obj, "timer[*]", &s->timer[i],
	TYPE_STM32F2XX_TIMER);
	}

	s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));

	for (i = 0; i < STM_NUM_ADCS; i++) {
	object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
	}

	for (i = 0; i < STM_NUM_SPIS; i++) {
	object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
	}

	s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
	s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
	}

	static void stm32f205_soc_realize(DeviceState dev_soc, Error *errp)
	{
	STM32F205State *s = STM32F205_SOC(dev_soc);
	DeviceState dev, armv7m;
	SysBusDevice *busdev;
	int i;

	MemoryRegion *system_memory = get_system_memory();

	/*
	* We use s->refclk internally and only define it with qdev_init_clock_in()
	* so it is correctly parented and not leaked on an init/deinit; it is not
	* intended as an externally exposed clock.
	*/
	if (clock_has_source(s->refclk)) {
	error_setg(errp, "refclk clock must not be wired up by the board code");
	return;
	}

	if (!clock_has_source(s->sysclk)) {
	error_setg(errp, "sysclk clock must be wired up by the board code");
	return;
	}

	/*
	* TODO: ideally we should model the SoC RCC and its ability to
	* change the sysclk frequency and define different sysclk sources.
	*/

	/* The refclk always runs at frequency HCLK / 8 */
	clock_set_mul_div(s->refclk, 8, 1);
	clock_set_source(s->refclk, s->sysclk);

	memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
	FLASH_SIZE, &error_fatal);
	memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
	"STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);

	memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
	memory_region_add_subregion(system_memory, 0, &s->flash_alias);

	memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
	&error_fatal);
	memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);

	armv7m = DEVICE(&s->armv7m);
	qdev_prop_set_uint32(armv7m, "num-irq", 96);
	qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
	qdev_prop_set_bit(armv7m, "enable-bitband", true);
	qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
	qdev_connect_clock_in(armv7m, "refclk", s->refclk);
	object_property_set_link(OBJECT(&s->armv7m), "memory",
	OBJECT(get_system_memory()), &error_abort);
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
	return;
	}

	/* System configuration controller */
	dev = DEVICE(&s->syscfg);
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
	return;
	}
	busdev = SYS_BUS_DEVICE(dev);
	sysbus_mmio_map(busdev, 0, 0x40013800);

	/* Attach UART (uses USART registers) and USART controllers */
	for (i = 0; i < STM_NUM_USARTS; i++) {
	dev = DEVICE(&(s->usart[i]));
	qdev_prop_set_chr(dev, "chardev", serial_hd(i));
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
	return;
	}
	busdev = SYS_BUS_DEVICE(dev);
	sysbus_mmio_map(busdev, 0, usart_addr[i]);
	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
	}

	/* Timer 2 to 5 */
	for (i = 0; i < STM_NUM_TIMERS; i++) {
	dev = DEVICE(&(s->timer[i]));
	qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
	return;
	}
	busdev = SYS_BUS_DEVICE(dev);
	sysbus_mmio_map(busdev, 0, timer_addr[i]);
	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
	}

	/* ADC 1 to 3 */
	object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
	&error_abort);
	if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) {
	return;
	}
	qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
	qdev_get_gpio_in(armv7m, ADC_IRQ));

	for (i = 0; i < STM_NUM_ADCS; i++) {
	dev = DEVICE(&(s->adc[i]));
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
	return;
	}
	busdev = SYS_BUS_DEVICE(dev);
	sysbus_mmio_map(busdev, 0, adc_addr[i]);
	sysbus_connect_irq(busdev, 0,
	qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
	}

	/* SPI 1 and 2 */
	for (i = 0; i < STM_NUM_SPIS; i++) {
	dev = DEVICE(&(s->spi[i]));
	if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
	return;
	}
	busdev = SYS_BUS_DEVICE(dev);
	sysbus_mmio_map(busdev, 0, spi_addr[i]);
	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
	}
	}

	static Property stm32f205_soc_properties[] = {
	DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
	DEFINE_PROP_END_OF_LIST(),
	};

	static void stm32f205_soc_class_init(ObjectClass klass, void data)
	{
	DeviceClass *dc = DEVICE_CLASS(klass);

	dc->realize = stm32f205_soc_realize;
	device_class_set_props(dc, stm32f205_soc_properties);
	}

	static const TypeInfo stm32f205_soc_info = {
	.name = TYPE_STM32F205_SOC,
	.parent = TYPE_SYS_BUS_DEVICE,
	.instance_size = sizeof(STM32F205State),
	.instance_init = stm32f205_soc_initfn,
	.class_init = stm32f205_soc_class_init,
	};

	static void stm32f205_soc_types(void)
	{
	type_register_static(&stm32f205_soc_info);
	}

	type_init(stm32f205_soc_types)