tree b91dc2511532d82a847f3e1755bfaaf2f9920a8c
parent 202abcd38920ea2025020de9e2c6e28a403c2256
parent e229a179a503f2aee43a76888cf12fbdfe8a3749
author Peter Maydell <peter.maydell@linaro.org> 1627396320 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1627396320 +0100
mergetag object e229a179a503f2aee43a76888cf12fbdfe8a3749
 type commit
 tag pull-target-arm-20210727
 tagger Peter Maydell <peter.maydell@linaro.org> 1627382725 +0100
 
 target-arm queue:
  * hw/arm/smmuv3: Check 31st bit to see if CD is valid
  * qemu-options.hx: Fix formatting of -machine memory-backend option
  * hw: aspeed_gpio: Fix memory size
  * hw/arm/nseries: Display hexadecimal value with '0x' prefix
  * Add sve-default-vector-length cpu property
  * docs: Update path that mentions deprecated.rst
  * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
  * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
  * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
  * target/arm: Report M-profile alignment faults correctly to the guest
  * target/arm: Add missing 'return's after calling v7m_exception_taken()
  * target/arm: Enforce that M-profile SP low 2 bits are always zero
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210727' into staging

target-arm queue:
 * hw/arm/smmuv3: Check 31st bit to see if CD is valid
 * qemu-options.hx: Fix formatting of -machine memory-backend option
 * hw: aspeed_gpio: Fix memory size
 * hw/arm/nseries: Display hexadecimal value with '0x' prefix
 * Add sve-default-vector-length cpu property
 * docs: Update path that mentions deprecated.rst
 * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
 * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
 * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
 * target/arm: Report M-profile alignment faults correctly to the guest
 * target/arm: Add missing 'return's after calling v7m_exception_taken()
 * target/arm: Enforce that M-profile SP low 2 bits are always zero

# gpg: Signature made Tue 27 Jul 2021 11:46:17 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210727:
  hw: aspeed_gpio: Fix memory size
  hw/arm/nseries: Display hexadecimal value with '0x' prefix
  target/arm: Add sve-default-vector-length cpu property
  target/arm: Export aarch64_sve_zcr_get_valid_len
  target/arm: Correctly bound length in sve_zcr_get_valid_len
  docs: Update path that mentions deprecated.rst
  hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
  hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
  hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
  target/arm: Report M-profile alignment faults correctly to the guest
  target/arm: Add missing 'return's after calling v7m_exception_taken()
  target/arm: Enforce that M-profile SP low 2 bits are always zero
  qemu-options.hx: Fix formatting of -machine memory-backend option
  hw/arm/smmuv3: Check 31st bit to see if CD is valid

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>