Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201103' into staging
This series adds support for migration to RISC-V QEMU and expands the
Microchip PFSoC to allow unmodified HSS and Linux boots.
# gpg: Signature made Tue 03 Nov 2020 15:19:45 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20201103:
target/riscv/csr.c : add space before the open parenthesis '('
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
hw/riscv: microchip_pfsoc: Correct DDR memory map
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
hw/riscv: microchip_pfsoc: Connect the SYSREG module
hw/misc: Add Microchip PolarFire SoC SYSREG module support
hw/riscv: microchip_pfsoc: Connect the IOSCB module
hw/misc: Add Microchip PolarFire SoC IOSCB module support
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
target/riscv: Add sifive_plic vmstate
target/riscv: Add V extension state description
target/riscv: Add H extension state description
target/riscv: Add PMP state description
target/riscv: Add basic vmstate description of CPU
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
hw/riscv: virt: Allow passing custom DTB
hw/riscv: sifive_u: Allow passing custom DTB
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
