| # AArch32 Neon instruction descriptions |
| # |
| # Copyright (c) 2020 Linaro, Ltd |
| # |
| # This library is free software; you can redistribute it and/or |
| # modify it under the terms of the GNU Lesser General Public |
| # License as published by the Free Software Foundation; either |
| # version 2.1 of the License, or (at your option) any later version. |
| # |
| # This library is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| # Lesser General Public License for more details. |
| # |
| # You should have received a copy of the GNU Lesser General Public |
| # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| |
| # |
| # This file is processed by scripts/decodetree.py |
| # |
| |
| # Encodings for Neon instructions whose encoding is the same for |
| # both A32 and T32. |
| |
| # More specifically, this covers: |
| # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx |
| # 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx |
| |
| # VFP/Neon register fields; same as vfp.decode |
| %vm_dp 5:1 0:4 |
| %vm_sp 0:4 5:1 |
| %vn_dp 7:1 16:4 |
| %vn_sp 16:4 7:1 |
| %vd_dp 22:1 12:4 |
| %vd_sp 12:4 22:1 |
| |
| # For VCMLA/VCADD insns, convert the single-bit size field |
| # which is 0 for fp16 and 1 for fp32 into a MO_* constant. |
| # (Note that this is the reverse of the sense of the 1-bit size |
| # field in the 3same_fp Neon insns.) |
| %vcadd_size 20:1 !function=plus_1 |
| |
| VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size |
| |
| VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size |
| |
| VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VUSDOT 1111 110 01 . 10 .... .... 1101 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VDOT_b16 1111 110 00 . 00 .... .... 1101 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| |
| # VFM[AS]L |
| VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \ |
| vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0 |
| VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1 |
| |
| VSMMLA 1111 1100 0.10 .... .... 1100 .1.0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VUMMLA 1111 1100 0.10 .... .... 1100 .1.1 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VUSMMLA 1111 1100 1.10 .... .... 1100 .1.0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| VMMLA_b16 1111 1100 0.00 .... .... 1100 .1.0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| |
| VFMA_b16 1111 110 0 0.11 .... .... 1000 . q:1 . 1 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp |
| |
| VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ |
| vn=%vn_dp vd=%vd_dp size=1 |
| VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ |
| vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0 |
| |
| VSDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 0 vm:4 \ |
| vn=%vn_dp vd=%vd_dp |
| VUDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 1 vm:4 \ |
| vn=%vn_dp vd=%vd_dp |
| VUSDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \ |
| vn=%vn_dp vd=%vd_dp |
| VSUDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 1 vm:4 \ |
| vn=%vn_dp vd=%vd_dp |
| VDOT_b16_scal 1111 1110 0 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \ |
| vn=%vn_dp vd=%vd_dp |
| |
| %vfml_scalar_q0_rm 0:3 5:1 |
| %vfml_scalar_q1_index 5:1 3:1 |
| VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \ |
| rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0 |
| VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \ |
| index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1 |
| VFMA_b16_scal 1111 1110 0.11 .... .... 1000 . q:1 . 1 . vm:3 \ |
| index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp |
