| # See docs/devel/tracing.rst for syntax documentation. |
| |
| # allwinner-cpucfg.c |
| allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32 |
| allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| |
| # allwinner-h3-dramc.c |
| allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" |
| allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 |
| allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| |
| # allwinner-sid.c |
| allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| |
| # avr_power.c |
| avr_power_read(uint8_t value) "power_reduc read value:%u" |
| avr_power_write(uint8_t value) "power_reduc write value:%u" |
| |
| # eccmemctl.c |
| ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" |
| ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" |
| ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x" |
| ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x" |
| ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x" |
| ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x" |
| ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x" |
| ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x" |
| ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x" |
| ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x" |
| ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x" |
| ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x" |
| ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x" |
| ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x" |
| ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x" |
| ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x" |
| ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x" |
| ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x" |
| |
| # empty_slot.c |
| empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" |
| |
| # slavio_misc.c |
| slavio_misc_update_irq_raise(void) "Raise IRQ" |
| slavio_misc_update_irq_lower(void) "Lower IRQ" |
| slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" |
| slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x" |
| slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x" |
| slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x" |
| slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x" |
| slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x" |
| slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x" |
| slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x" |
| slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x" |
| slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x" |
| slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x" |
| apc_mem_writeb(uint32_t val) "Write power management 0x%02x" |
| apc_mem_readb(uint32_t ret) "Read power management 0x%02x" |
| slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x" |
| slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x" |
| slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" |
| slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" |
| |
| # aspeed_scu.c |
| aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| |
| # mps2-scc.c |
| mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| mps2_scc_reset(void) "MPS2 SCC: reset" |
| mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 |
| mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 |
| |
| # mps2-fpgaio.c |
| mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" |
| |
| # msf2-sysreg.c |
| msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 |
| msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 |
| msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" |
| |
| # imx7_gpr.c |
| imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 |
| imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 |
| |
| # mos6522.c |
| mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" |
| mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 |
| mos6522_set_sr_int(void) "set sr_int" |
| mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 |
| mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" |
| |
| # npcm7xx_clk.c |
| npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| |
| # npcm7xx_gcr.c |
| npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| |
| # npcm7xx_mft.c |
| npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 |
| npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d" |
| npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 |
| npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d" |
| |
| # npcm7xx_rng.c |
| npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" |
| npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" |
| |
| # npcm7xx_pwm.c |
| npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" |
| npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" |
| |
| # stm32f4xx_syscfg.c |
| stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d" |
| stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" |
| stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
| stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| |
| # stm32f4xx_exti.c |
| stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" |
| stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
| stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| |
| # tz-mpc.c |
| tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" |
| tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |
| tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" |
| tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 |
| |
| # tz-msc.c |
| tz_msc_reset(void) "TZ MSC: reset" |
| tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" |
| tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" |
| tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" |
| tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" |
| tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" |
| |
| # tz-ppc.c |
| tz_ppc_reset(void) "TZ PPC: reset" |
| tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" |
| tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" |
| tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" |
| tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" |
| tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" |
| tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" |
| tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" |
| tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" |
| |
| # iotkit-secctl.c |
| iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| |
| # imx6ul_ccm.c |
| ccm_entry(void) "" |
| ccm_freq(uint32_t freq) "freq = %d" |
| ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" |
| ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| |
| # iotkit-sysinfo.c |
| iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| |
| # iotkit-sysctl.c |
| iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" |
| |
| # armsse-cpu-pwrctrl.c |
| armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| |
| # armsse-cpuid.c |
| armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| |
| # armsse-mhu.c |
| armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| |
| # aspeed_xdma.c |
| aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| |
| # aspeed_i3c.c |
| aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| |
| # aspeed_sdmc.c |
| aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 |
| aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 |
| |
| # aspeed_peci.c |
| aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32 |
| |
| # bcm2835_property.c |
| bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" |
| |
| # bcm2835_mbox.c |
| bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 |
| bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 |
| bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" |
| |
| # mac_via.c |
| via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x" |
| via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x" |
| via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x" |
| via1_rtc_internal_cmd(int cmd) "cmd=0x%02x" |
| via1_rtc_cmd_invalid(int value) "value=0x%02x" |
| via1_rtc_internal_time(uint32_t time) "time=0x%08x" |
| via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x" |
| via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x" |
| via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u" |
| via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x" |
| via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x" |
| via1_rtc_cmd_test_write(int value) "value=0x%02x" |
| via1_rtc_cmd_wprotect_write(int value) "value=0x%02x" |
| via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" |
| via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" |
| via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" |
| via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" |
| via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" |
| via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" |
| via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" |
| via1_auxmode(int mode) "setting auxmode to %d" |
| |
| # grlib_ahb_apb_pnp.c |
| grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" data:0x%08x" |
| grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx64" data:0x%08x" |
| |
| # led.c |
| led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%" |
| led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%" |
| |
| # pca9552.c |
| pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" |
| pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" |
| |
| # bcm2835_cprman.c |
| bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| |
| # virt_ctrl.c |
| virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 |
| virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 |
| virt_ctrl_reset(void *dev) "ctrl: %p" |
| virt_ctrl_realize(void *dev) "ctrl: %p" |
| virt_ctrl_instance_init(void *dev) "ctrl: %p" |
| |
| # lasi.c |
| lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" |
| lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" |
| lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" |
