)]}' { "commit": "247b18c593ec298446645af8d5d28911daf653b1", "tree": "f0579919a0db9c451e945cfdc2cd6744532000df", "parents": [ "2e26f4ab3bf8390a2677d3afd9b1a04f015d7721" ], "author": { "name": "Babu Moger", "email": "babu.moger@amd.com", "time": "Wed Mar 11 17:54:09 2020 -0500" }, "committer": { "name": "Eduardo Habkost", "email": "ehabkost@redhat.com", "time": "Tue Mar 31 19:13:32 2020 -0300" }, "message": "target/i386: Enable new apic id encoding for EPYC based cpus models\n\nThe APIC ID is decoded based on the sequence sockets-\u003edies-\u003ecores-\u003ethreads.\nThis works fine for most standard AMD and other vendors\u0027 configurations,\nbut this decoding sequence does not follow that of AMD\u0027s APIC ID enumeration\nstrictly. In some cases this can cause CPU topology inconsistency.\n\nWhen booting a guest VM, the kernel tries to validate the topology, and finds\nit inconsistent with the enumeration of EPYC cpu models. The more details are\nin the bug https://bugzilla.redhat.com/show_bug.cgi?id\u003d1728166.\n\nTo fix the problem we need to build the topology as per the Processor\nProgramming Reference (PPR) for AMD Family 17h Model 01h, Revision B1\nProcessors. The documentation is available from the bugzilla Link below.\n\nLink: https://bugzilla.kernel.org/show_bug.cgi?id\u003d206537\nIt is also available at\nhttps://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip\n\nHere is the text from the PPR.\nOperating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the\nnumber of least significant bits in the Initial APIC ID that indicate core ID\nwithin a processor, in constructing per-core CPUID masks.\nCore::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores\n(MNC) that the processor could theoretically support, not the actual number of\ncores that are actually implemented or enabled on the processor, as indicated\nby Core::X86::Cpuid::SizeId[NC].\nEach Core::X86::Apic::ApicId[ApicId] register is preset as follows:\n• ApicId[6] \u003d Socket ID.\n• ApicId[5:4] \u003d Node ID.\n• ApicId[3] \u003d Logical CCX L3 complex ID\n• ApicId[2:0]\u003d (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1\u0027b0,LogicalCoreID[1:0]}\n\nThe new apic id encoding is enabled for EPYC and EPYC-Rome models.\n\nSigned-off-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nAcked-by: Igor Mammedov \u003cimammedo@redhat.com\u003e\nMessage-Id: \u003c158396724913.58170.3539083528095710811.stgit@naples-babu.amd.com\u003e\nSigned-off-by: Eduardo Habkost \u003cehabkost@redhat.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "50cd257a7e39b658529b482a7d4ef9ffab28323f", "old_mode": 33188, "old_path": "target/i386/cpu.c", "new_id": "468e03a1537d161b5d7903088d2e5b8b190da049", "new_mode": 33188, "new_path": "target/i386/cpu.c" } ] }