| { |
| "Xe": { |
| "fields": { |
| "HW_OPCODE": [ 6, 0 ], |
| "SWSB": [ 15, 8 ], |
| "EXEC_SIZE": [ 18, 16 ], |
| "CHAN_OFFSET": [ 21, 19 ], |
| "FLAG_SUBNR": [ 22, 22 ], |
| "FLAG_NR": [ 23, 23 ], |
| "PRED_CONTROL": [ 27, 24 ], |
| "PRED_INV": [ 28, 28 ], |
| "DEBUG_CONTROL": [ 30, 30 ], |
| "NO_MASK": [ 31, 31 ], |
| "ATOMIC_CONTROL": [ 32, 32 ], |
| "SATURATE": [ 34, 34 ], |
| "DST_ADDRESS_MODE": [ 35, 35 ], |
| "DST_TYPE": [ 39, 36 ], |
| "SRC0_TYPE": [ 43, 40 ], |
| "SRC0_ABS": [ 44, 44 ], |
| "SRC0_NEGATE": [ 45, 45 ], |
| "SRC0_IS_IMM": [ 46, 46 ], |
| "SRC1_IS_IMM": [ 47, 47 ], |
| "DST_HSTRIDE": [ 49, 48 ], |
| "DST_OPERAND": [ 63, 50 ], |
| "SRC0_HSTRIDE": [ 65, 64 ], |
| "SRC0_OPERAND": [ 79, 66 ], |
| "SRC0_ADDRESS_MODE": [ 80, 80 ], |
| "SRC0_WIDTH": [ 83, 81 ], |
| "SRC0_VSTRIDE": [ 87, 84 ], |
| "SRC1_TYPE": [ 91, 88 ], |
| "COND_MODIFIER": [ 95, 92 ], |
| "SRC1_HSTRIDE": [ 97, 96 ], |
| "SRC1_OPERAND": [ 111, 98 ], |
| "SRC1_ADDRESS_MODE": [ 112, 112 ], |
| "SRC1_WIDTH": [ 115, 113 ], |
| "SRC1_VSTRIDE": [ 119, 116 ], |
| "SRC1_ABS": [ 120, 120 ], |
| "SRC1_NEGATE": [ 121, 121 ], |
| |
| "BRANCH_CONTROL": [ 33, 33 ], |
| "ACC_WR_CONTROL": [ 33, 33 ], |
| |
| "IMM_LO_32": [ 127, 96 ], |
| "IMM_HI_32": [ 95, 64 ], |
| |
| "# EU_INSTRUCTION_BASIC_THREE_SRC":"#", |
| "THREE_SRC0_VSTRIDE_LO": [ 35, 35 ], |
| "THREE_DST_TYPE": [ 38, 36 ], |
| "THREE_EXEC_DATA_TYPE": [ 39, 39 ], |
| "THREE_SRC0_TYPE": [ 42, 40 ], |
| "THREE_SRC0_VSTRIDE_HI": [ 43, 43 ], |
| "THREE_SRC2_IS_IMM": [ 47, 47 ], |
| "THREE_DST_HSTRIDE": [ 48, 48 ], |
| "THREE_DST_OPERAND": [ 63, 50 ], |
| "THREE_SRC0_HSTRIDE": [ 65, 64 ], |
| "THREE_SRC0_OPERAND": [ 79, 66 ], |
| "THREE_SRC2_TYPE": [ 82, 80 ], |
| "THREE_SRC1_VSTRIDE_LO": [ 83, 83 ], |
| "THREE_SRC2_ABS": [ 84, 84 ], |
| "THREE_SRC2_NEGATE": [ 85, 85 ], |
| "THREE_SRC1_ABS": [ 86, 86 ], |
| "THREE_SRC1_NEGATE": [ 87, 87 ], |
| "THREE_SRC1_TYPE": [ 90, 88 ], |
| "THREE_SRC1_VSTRIDE_HI": [ 91, 91 ], |
| "THREE_SRC1_HSTRIDE": [ 97, 96 ], |
| "THREE_SRC1_OPERAND": [ 111, 98 ], |
| "THREE_SRC2_HSTRIDE": [ 113, 112 ], |
| "THREE_SRC2_OPERAND": [ 127, 114 ], |
| |
| "THREE_SRC0_IMM": [ 79, 64 ], |
| "THREE_SRC2_IMM": [ 127, 112 ], |
| |
| "# EU_INSTRUCTION_MATH":"#", |
| "MATH_FC": [ 95, 92 ], |
| |
| "# EU_INSTRUCTION_SYNC":"#", |
| "SYNC_CTRL": [ 95, 92 ], |
| |
| "# EU_INSTRUCTION_BFN":"#", |
| "BFN_COND_MODIFIER": [ 45, 44 ], |
| "BFN_FUNC_CONTROL_HI": [ 95, 92 ], |
| "BFN_FUNC_CONTROL_LO": [ 87, 84 ], |
| |
| "# EU_INSTRUCTION_DPAS_THREE_SRC":"#", |
| "DPAS_RCOUNT": [ 45, 43 ], |
| "DPAS_SDEPTH": [ 49, 48 ], |
| "DPAS_SRC2_SUBBYTE": [ 85, 84 ], |
| "DPAS_SRC1_SUBBYTE": [ 87, 86 ], |
| |
| "# EU_INSTRUCTION_SEND":"#", |
| "SEND_FUSION_CONTROL": [ 33, 33 ], |
| "SEND_EOT": [ 34, 34 ], |
| "SEND_EX_BSO": [ 39, 39 ], |
| "SEND_DESC_IS_REG": [ 48, 48 ], |
| "SEND_EX_DESC_IS_REG": [ 49, 49 ], |
| "SEND_SFID": [ 95, 92 ], |
| |
| "SEND_SRC0_SUB_NR": [ 103, 99 ], |
| "SEND_SRC1_LEN": [ 103, 99 ] |
| }, |
| "sub-fields": { |
| "# Relative to OPERAND sub-structures":"#", |
| "REG_NR": [ 13, 6 ] |
| }, |
| "compact-fields": { |
| "SRC1_REG_NR": [ 63, 56 ], |
| "CMPT_CONTROL": [ 29, 29 ], |
| "DEBUG_CONTROL": [ 7, 7 ], |
| "HW_OPCODE": [ 6, 0 ], |
| "SRC0_REG_NR": [ 47, 40 ], |
| "DST_REG_NR": [ 23, 16 ], |
| "SRC1_INDEX": [ 55, 52 ], |
| "SRC0_INDEX": [ 51, 48 ], |
| "COND_MODIFIER": null, |
| "ACC_WR_CONTROL": null, |
| "SUBREG_INDEX": [ 39, 35 ], |
| "DATATYPE_INDEX": [ 34, 30 ], |
| "CONTROL_INDEX": [ 28, 24 ], |
| "SWSB": [ 15, 8 ], |
| |
| "3SRC_SRC2_REG_NR": [ 55, 48 ], |
| "3SRC_SRC1_REG_NR": [ 63, 56 ], |
| "3SRC_SRC0_REG_NR": [ 47, 40 ], |
| "3SRC_SRC2_SUBREG_NR": null, |
| "3SRC_SRC1_SUBREG_NR": null, |
| "3SRC_SRC0_SUBREG_NR": null, |
| "3SRC_SRC2_REP_CTRL": null, |
| "3SRC_SRC1_REP_CTRL": null, |
| "3SRC_SATURATE": null, |
| "3SRC_DEBUG_CONTROL": [ 7, 7 ], |
| "3SRC_CMPT_CONTROL": [ 29, 29 ], |
| "3SRC_SRC0_REP_CTRL": null, |
| "3SRC_DST_REG_NR": [ 23, 16 ], |
| "3SRC_SOURCE_INDEX": [ 34, 30 ], |
| "3SRC_SUBREG_INDEX": [ 39, 35 ], |
| "3SRC_CONTROL_INDEX": [ 28, 24 ], |
| "3SRC_SWSB": [ 15, 8 ] |
| }, |
| "gen-op-to-brw": { |
| "ILLEGAL": 0, |
| "ADD": 64, |
| "ADD3": 82, |
| "ADDC": 78, |
| "AND": 101, |
| "ASR": 108, |
| "AVG": 66, |
| "BFE": 120, |
| "BFI1": 121, |
| "BFI2": 122, |
| "BFN": 107, |
| "BFREV": 119, |
| "BRC": 35, |
| "BRD": 33, |
| "BREAK": 40, |
| "CALL": 44, |
| "CALLA": 43, |
| "CBIT": 77, |
| "CMP": 112, |
| "CMPN": 113, |
| "CONTINUE": 41, |
| "CSEL": 114, |
| "DP4A": 88, |
| "DPAS": 89, |
| "ELSE": 36, |
| "ENDIF": 37, |
| "FBH": 75, |
| "FBL": 76, |
| "FRC": 67, |
| "GOTO": 46, |
| "HALT": 42, |
| "IF": 34, |
| "JMPI": 32, |
| "JOIN": 47, |
| "LZD": 74, |
| "MAC": 72, |
| "MACH": 73, |
| "MAD": 91, |
| "MADM": 93, |
| "MATH": 56, |
| "MOV": 97, |
| "MOVI": 99, |
| "MUL": 65, |
| "NOP": 96, |
| "NOT": 100, |
| "OR": 102, |
| "RET": 45, |
| "RNDD": 69, |
| "RNDE": 70, |
| "RNDU": 68, |
| "RNDZ": 71, |
| "ROL": 111, |
| "ROR": 110, |
| "SEL": 98, |
| "SEND": 49, |
| "SENDC": 50, |
| "SHL": 105, |
| "SHR": 104, |
| "SMOV": 106, |
| "SUBB": 79, |
| "SYNC": 1, |
| "WAIT": 48, |
| "WHILE": 39, |
| "XOR": 103 |
| } |
| }, |
| "Xe2": { |
| "import": "Xe", |
| "fields": { |
| "SWSB": [ 17, 8 ], |
| "EXEC_SIZE": [ 20, 18 ], |
| |
| "FLAG_SUBNR": [ 21, 21 ], |
| "FLAG_NR": [ 23, 22 ], |
| "CHAN_OFFSET": [ 25, 24 ], |
| "PRED_CONTROL": [ 27, 26 ], |
| |
| "SRC0_VSTRIDE": [ 86, 84 ], |
| "SRC1_VSTRIDE": [ 118, 116 ], |
| |
| "DST_OPERAND_EXTRA": [ 33, 33 ], |
| "SRC0_OPERAND_EXTRA": [ 87, 87 ], |
| |
| "ACC_WR_CONTROL": null, |
| "NIB_CONTROL": null, |
| "SEND_FUSION_CONTROL": null |
| }, |
| "compact-fields": { |
| "DST_REG_NR": [ 39, 32 ], |
| "SRC0_INDEX": [ 25, 23 ], |
| "SUBREG_INDEX": [ 51, 48 ], |
| "DATATYPE_INDEX": null, |
| "DATATYPE_INDEX_LO3": [ 28, 26 ], |
| "DATATYPE_INDEX_HI2": [ 31, 30 ], |
| "CONTROL_INDEX": [ 22, 18 ], |
| "SWSB": [ 17, 8 ], |
| |
| "3SRC_DST_REG_NR": [ 39, 32 ], |
| "3SRC_SOURCE_INDEX": [ 25, 22 ], |
| "3SRC_SUBREG_INDEX": null, |
| "3SRC_SUBREG_INDEX_LO3": [ 28, 26 ], |
| "3SRC_SUBREG_INDEX_HI2": [ 31, 30 ], |
| "3SRC_CONTROL_INDEX": [ 21, 18 ], |
| "3SRC_SWSB": [ 17, 8 ] |
| }, |
| "gen-op-to-brw": { |
| "MACL": 83, |
| "SRND": 84 |
| } |
| } |
| } |
