blob: 08db4d14d9de82dcd1393e801defa408eb686cde [file] [log] [blame]
/*
* Copyright © 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <assert.h>
#include <stdbool.h>
#include "anv_private.h"
#include "anv_measure.h"
#include "vk_format.h"
#include "vk_render_pass.h"
#include "vk_util.h"
#include "util/fast_idiv_by_const.h"
#include "common/intel_aux_map.h"
#include "common/intel_l3_config.h"
#include "genxml/gen_macros.h"
#include "genxml/genX_pack.h"
#include "genxml/gen_rt_pack.h"
#include "common/intel_guardband.h"
#include "compiler/brw_prim.h"
#include "nir/nir_xfb_info.h"
#include "ds/intel_tracepoints.h"
/* We reserve :
* - GPR 14 for secondary command buffer returns
* - GPR 15 for conditional rendering
*/
#define MI_BUILDER_NUM_ALLOC_GPRS 14
#define __gen_get_batch_dwords anv_batch_emit_dwords
#define __gen_address_offset anv_address_add
#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
#include "common/mi_builder.h"
static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
uint32_t pipeline);
static enum anv_pipe_bits
convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
enum anv_pipe_bits bits = 0;
bits |= (pc->DepthCacheFlushEnable) ? ANV_PIPE_DEPTH_CACHE_FLUSH_BIT : 0;
bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
#if GFX_VERx10 >= 125
bits |= (pc->PSSStallSyncEnable) ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0;
#endif
#if GFX_VER >= 12
bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
#endif
bits |= (pc->RenderTargetCacheFlushEnable) ? ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
bits |= (pc->VFCacheInvalidationEnable) ? ANV_PIPE_VF_CACHE_INVALIDATE_BIT : 0;
bits |= (pc->StateCacheInvalidationEnable) ? ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;
bits |= (pc->ConstantCacheInvalidationEnable) ? ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT : 0;
bits |= (pc->TextureCacheInvalidationEnable) ? ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT : 0;
bits |= (pc->InstructionCacheInvalidateEnable) ? ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT : 0;
bits |= (pc->StallAtPixelScoreboard) ? ANV_PIPE_STALL_AT_SCOREBOARD_BIT : 0;
bits |= (pc->DepthStallEnable) ? ANV_PIPE_DEPTH_STALL_BIT : 0;
bits |= (pc->CommandStreamerStallEnable) ? ANV_PIPE_CS_STALL_BIT : 0;
#if GFX_VERx10 == 125
bits |= (pc->UntypedDataPortCacheFlushEnable) ? ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT : 0;
#endif
return bits;
}
#define anv_debug_dump_pc(pc) \
if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) { \
fputs("pc: emit PC=( ", stderr); \
anv_dump_pipe_bits(convert_pc_to_bits(&(pc))); \
fprintf(stderr, ") reason: %s\n", __FUNCTION__); \
}
static bool
is_render_queue_cmd_buffer(const struct anv_cmd_buffer *cmd_buffer)
{
struct anv_queue_family *queue_family = cmd_buffer->queue_family;
return (queue_family->queueFlags & VK_QUEUE_GRAPHICS_BIT) != 0;
}
ALWAYS_INLINE static void
genX(emit_dummy_post_sync_op)(struct anv_cmd_buffer *cmd_buffer,
uint32_t vertex_count)
{
genX(batch_emit_dummy_post_sync_op)(&cmd_buffer->batch, cmd_buffer->device,
cmd_buffer->state.gfx.primitive_topology,
vertex_count);
}
void
genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
uint32_t mocs = isl_mocs(&device->isl_dev, 0, false);
/* If we are emitting a new state base address we probably need to re-emit
* binding tables.
*/
cmd_buffer->state.descriptors_dirty |= ~0;
#if GFX_VERx10 >= 125
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
anv_batch_emit(
&cmd_buffer->batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
btpa.BindingTablePoolBaseAddress =
anv_cmd_buffer_surface_base_address(cmd_buffer);
btpa.BindingTablePoolBufferSize = BINDING_TABLE_POOL_BLOCK_SIZE / 4096;
btpa.MOCS = mocs;
}
#else /* GFX_VERx10 < 125 */
/* Emit a render target cache flush.
*
* This isn't documented anywhere in the PRM. However, it seems to be
* necessary prior to changing the surface state base address. Without
* this, we get GPU hangs when using multi-level command buffers which
* clear depth, reset state base address, and then go render stuff.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
#if GFX_VER >= 12
pc.HDCPipelineFlushEnable = true;
#else
pc.DCFlushEnable = true;
#endif
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
#if GFX_VERx10 == 120
/* Wa_1607854226:
*
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode.
*/
uint32_t gfx12_wa_pipeline = cmd_buffer->state.current_pipeline;
genX(flush_pipeline_select_3d)(cmd_buffer);
#endif
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
sba.GeneralStateMOCS = mocs;
sba.GeneralStateBaseAddressModifyEnable = true;
sba.StatelessDataPortAccessMOCS = mocs;
sba.SurfaceStateBaseAddress =
anv_cmd_buffer_surface_base_address(cmd_buffer);
sba.SurfaceStateMOCS = mocs;
sba.SurfaceStateBaseAddressModifyEnable = true;
sba.DynamicStateBaseAddress =
(struct anv_address) { device->dynamic_state_pool.block_pool.bo, 0 };
sba.DynamicStateMOCS = mocs;
sba.DynamicStateBaseAddressModifyEnable = true;
sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
sba.IndirectObjectMOCS = mocs;
sba.IndirectObjectBaseAddressModifyEnable = true;
sba.InstructionBaseAddress =
(struct anv_address) { device->instruction_state_pool.block_pool.bo, 0 };
sba.InstructionMOCS = mocs;
sba.InstructionBaseAddressModifyEnable = true;
sba.GeneralStateBufferSize = 0xfffff;
sba.IndirectObjectBufferSize = 0xfffff;
sba.DynamicStateBufferSize = DYNAMIC_STATE_POOL_SIZE / 4096;
sba.InstructionBufferSize = INSTRUCTION_STATE_POOL_SIZE / 4096;
sba.GeneralStateBufferSizeModifyEnable = true;
sba.IndirectObjectBufferSizeModifyEnable = true;
sba.DynamicStateBufferSizeModifyEnable = true;
sba.InstructionBuffersizeModifyEnable = true;
sba.BindlessSurfaceStateBaseAddress =
(struct anv_address) { device->bindless_surface_state_pool.block_pool.bo, 0 };
sba.BindlessSurfaceStateSize = (1 << 20) - 1;
sba.BindlessSurfaceStateMOCS = mocs;
sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
#if GFX_VER >= 11
sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
sba.BindlessSamplerStateMOCS = mocs;
sba.BindlessSamplerStateBaseAddressModifyEnable = true;
sba.BindlessSamplerStateBufferSize = 0;
#endif
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
}
#if GFX_VERx10 == 120
/* Wa_1607854226:
*
* Put the pipeline back into its current mode.
*/
if (gfx12_wa_pipeline != UINT32_MAX)
genX(flush_pipeline_select)(cmd_buffer, gfx12_wa_pipeline);
#endif
#endif /* GFX_VERx10 < 125 */
/* After re-setting the surface state base address, we have to do some
* cache flushing so that the sampler engine will pick up the new
* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
* Shared Function > 3D Sampler > State > State Caching (page 96):
*
* Coherency with system memory in the state cache, like the texture
* cache is handled partially by software. It is expected that the
* command stream or shader will issue Cache Flush operation or
* Cache_Flush sampler message to ensure that the L1 cache remains
* coherent with system memory.
*
* [...]
*
* Whenever the value of the Dynamic_State_Base_Addr,
* Surface_State_Base_Addr are altered, the L1 state cache must be
* invalidated to ensure the new surface or sampler state is fetched
* from system memory.
*
* The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
* which, according the PIPE_CONTROL instruction documentation in the
* Broadwell PRM:
*
* Setting this bit is independent of any other bit in this packet.
* This bit controls the invalidation of the L1 and L2 state caches
* at the top of the pipe i.e. at the parsing time.
*
* Unfortunately, experimentation seems to indicate that state cache
* invalidation through a PIPE_CONTROL does nothing whatsoever in
* regards to surface state and binding tables. In stead, it seems that
* invalidating the texture cache is what is actually needed.
*
* XXX: As far as we have been able to determine through
* experimentation, shows that flush the texture cache appears to be
* sufficient. The theory here is that all of the sampling/rendering
* units cache the binding table in the texture cache. However, we have
* yet to be able to actually confirm this.
*
* Wa_14013910100:
*
* "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice
* or program pipe control with Instruction cache invalidate post
* STATE_BASE_ADDRESS command"
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
pc.ConstantCacheInvalidationEnable = true;
pc.StateCacheInvalidationEnable = true;
#if GFX_VERx10 == 125
pc.InstructionCacheInvalidateEnable = true;
#endif
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache Invalidation
* Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
pc.CommandStreamerStallEnable =
cmd_buffer->state.current_pipeline == GPGPU;
#endif
anv_debug_dump_pc(pc);
}
}
static void
add_surface_reloc(struct anv_cmd_buffer *cmd_buffer,
struct anv_state state, struct anv_address addr)
{
VkResult result = anv_reloc_list_add_bo(&cmd_buffer->surface_relocs,
&cmd_buffer->vk.pool->alloc,
addr.bo);
if (unlikely(result != VK_SUCCESS))
anv_batch_set_error(&cmd_buffer->batch, result);
}
static void
add_surface_state_relocs(struct anv_cmd_buffer *cmd_buffer,
struct anv_surface_state state)
{
assert(!anv_address_is_null(state.address));
add_surface_reloc(cmd_buffer, state.state, state.address);
if (!anv_address_is_null(state.aux_address)) {
VkResult result =
anv_reloc_list_add_bo(&cmd_buffer->surface_relocs,
&cmd_buffer->vk.pool->alloc,
state.aux_address.bo);
if (result != VK_SUCCESS)
anv_batch_set_error(&cmd_buffer->batch, result);
}
if (!anv_address_is_null(state.clear_address)) {
VkResult result =
anv_reloc_list_add_bo(&cmd_buffer->surface_relocs,
&cmd_buffer->vk.pool->alloc,
state.clear_address.bo);
if (result != VK_SUCCESS)
anv_batch_set_error(&cmd_buffer->batch, result);
}
}
static bool
isl_color_value_requires_conversion(union isl_color_value color,
const struct isl_surf *surf,
const struct isl_view *view)
{
if (surf->format == view->format && isl_swizzle_is_identity(view->swizzle))
return false;
uint32_t surf_pack[4] = { 0, 0, 0, 0 };
isl_color_value_pack(&color, surf->format, surf_pack);
uint32_t view_pack[4] = { 0, 0, 0, 0 };
union isl_color_value swiz_color =
isl_color_value_swizzle_inv(color, view->swizzle);
isl_color_value_pack(&swiz_color, view->format, view_pack);
return memcmp(surf_pack, view_pack, sizeof(surf_pack)) != 0;
}
static bool
anv_can_fast_clear_color_view(struct anv_device * device,
struct anv_image_view *iview,
VkImageLayout layout,
union isl_color_value clear_color,
uint32_t num_layers,
VkRect2D render_area)
{
if (iview->planes[0].isl.base_array_layer >=
anv_image_aux_layers(iview->image, VK_IMAGE_ASPECT_COLOR_BIT,
iview->planes[0].isl.base_level))
return false;
/* Start by getting the fast clear type. We use the first subpass
* layout here because we don't want to fast-clear if the first subpass
* to use the attachment can't handle fast-clears.
*/
enum anv_fast_clear_type fast_clear_type =
anv_layout_to_fast_clear_type(device->info, iview->image,
VK_IMAGE_ASPECT_COLOR_BIT,
layout);
switch (fast_clear_type) {
case ANV_FAST_CLEAR_NONE:
return false;
case ANV_FAST_CLEAR_DEFAULT_VALUE:
if (!isl_color_value_is_zero(clear_color, iview->planes[0].isl.format))
return false;
break;
case ANV_FAST_CLEAR_ANY:
break;
}
/* Potentially, we could do partial fast-clears but doing so has crazy
* alignment restrictions. It's easier to just restrict to full size
* fast clears for now.
*/
if (render_area.offset.x != 0 ||
render_area.offset.y != 0 ||
render_area.extent.width != iview->vk.extent.width ||
render_area.extent.height != iview->vk.extent.height)
return false;
/* If the clear color is one that would require non-trivial format
* conversion on resolve, we don't bother with the fast clear. This
* shouldn't be common as most clear colors are 0/1 and the most common
* format re-interpretation is for sRGB.
*/
if (isl_color_value_requires_conversion(clear_color,
&iview->image->planes[0].primary_surface.isl,
&iview->planes[0].isl)) {
anv_perf_warn(VK_LOG_OBJS(&iview->vk.base),
"Cannot fast-clear to colors which would require "
"format conversion on resolve");
return false;
}
/* We only allow fast clears to the first slice of an image (level 0,
* layer 0) and only for the entire slice. This guarantees us that, at
* any given time, there is only one clear color on any given image at
* any given time. At the time of our testing (Jan 17, 2018), there
* were no known applications which would benefit from fast-clearing
* more than just the first slice.
*/
if (iview->planes[0].isl.base_level > 0 ||
iview->planes[0].isl.base_array_layer > 0) {
anv_perf_warn(VK_LOG_OBJS(&iview->image->vk.base),
"Rendering with multi-lod or multi-layer framebuffer "
"with LOAD_OP_LOAD and baseMipLevel > 0 or "
"baseArrayLayer > 0. Not fast clearing.");
return false;
}
if (num_layers > 1) {
anv_perf_warn(VK_LOG_OBJS(&iview->image->vk.base),
"Rendering to a multi-layer framebuffer with "
"LOAD_OP_CLEAR. Only fast-clearing the first slice");
}
return true;
}
static bool
anv_can_hiz_clear_ds_view(struct anv_device *device,
const struct anv_image_view *iview,
VkImageLayout layout,
VkImageAspectFlags clear_aspects,
float depth_clear_value,
VkRect2D render_area)
{
/* If we're just clearing stencil, we can always HiZ clear */
if (!(clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
return true;
/* We must have depth in order to have HiZ */
if (!(iview->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
return false;
const enum isl_aux_usage clear_aux_usage =
anv_layout_to_aux_usage(device->info, iview->image,
VK_IMAGE_ASPECT_DEPTH_BIT,
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
layout);
if (!blorp_can_hiz_clear_depth(device->info,
&iview->image->planes[0].primary_surface.isl,
clear_aux_usage,
iview->planes[0].isl.base_level,
iview->planes[0].isl.base_array_layer,
render_area.offset.x,
render_area.offset.y,
render_area.offset.x +
render_area.extent.width,
render_area.offset.y +
render_area.extent.height))
return false;
if (depth_clear_value != ANV_HZ_FC_VAL)
return false;
/* If we got here, then we can fast clear */
return true;
}
#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
#if GFX_VER == 12
static void
anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
uint32_t base_level, uint32_t level_count,
uint32_t base_layer, uint32_t layer_count)
{
const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
const struct anv_surface *surface = &image->planes[plane].primary_surface;
uint64_t base_address =
anv_address_physical(anv_image_address(image, &surface->memory_range));
const struct isl_surf *isl_surf = &image->planes[plane].primary_surface.isl;
uint64_t format_bits = intel_aux_map_format_bits_for_isl_surf(isl_surf);
/* We're about to live-update the AUX-TT. We really don't want anyone else
* trying to read it while we're doing this. We could probably get away
* with not having this stall in some cases if we were really careful but
* it's better to play it safe. Full stall the GPU.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before update AUX-TT");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
struct mi_builder b;
mi_builder_init(&b, cmd_buffer->device->info, &cmd_buffer->batch);
for (uint32_t a = 0; a < layer_count; a++) {
const uint32_t layer = base_layer + a;
uint64_t start_offset_B = UINT64_MAX, end_offset_B = 0;
for (uint32_t l = 0; l < level_count; l++) {
const uint32_t level = base_level + l;
uint32_t logical_array_layer, logical_z_offset_px;
if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
logical_array_layer = 0;
/* If the given miplevel does not have this layer, then any higher
* miplevels won't either because miplevels only get smaller the
* higher the LOD.
*/
assert(layer < image->vk.extent.depth);
if (layer >= anv_minify(image->vk.extent.depth, level))
break;
logical_z_offset_px = layer;
} else {
assert(layer < image->vk.array_layers);
logical_array_layer = layer;
logical_z_offset_px = 0;
}
uint64_t slice_start_offset_B, slice_end_offset_B;
isl_surf_get_image_range_B_tile(isl_surf, level,
logical_array_layer,
logical_z_offset_px,
&slice_start_offset_B,
&slice_end_offset_B);
start_offset_B = MIN2(start_offset_B, slice_start_offset_B);
end_offset_B = MAX2(end_offset_B, slice_end_offset_B);
}
/* Aux operates 64K at a time */
start_offset_B = align_down_u64(start_offset_B, 64 * 1024);
end_offset_B = align_u64(end_offset_B, 64 * 1024);
for (uint64_t offset = start_offset_B;
offset < end_offset_B; offset += 64 * 1024) {
uint64_t address = base_address + offset;
uint64_t aux_entry_addr64, *aux_entry_map;
aux_entry_map = intel_aux_map_get_entry(cmd_buffer->device->aux_map_ctx,
address, &aux_entry_addr64);
struct anv_address aux_entry_address = {
.bo = NULL,
.offset = aux_entry_addr64,
};
const uint64_t old_aux_entry = READ_ONCE(*aux_entry_map);
uint64_t new_aux_entry =
(old_aux_entry & INTEL_AUX_MAP_ADDRESS_MASK) | format_bits;
if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage))
new_aux_entry |= INTEL_AUX_MAP_ENTRY_VALID_BIT;
mi_store(&b, mi_mem64(aux_entry_address), mi_imm(new_aux_entry));
}
}
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_AUX_TABLE_INVALIDATE_BIT,
"after update AUX-TT");
}
#endif /* GFX_VER == 12 */
/* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
* the initial layout is undefined, the HiZ buffer and depth buffer will
* represent the same data at the end of this operation.
*/
static void
transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
uint32_t base_layer, uint32_t layer_count,
VkImageLayout initial_layout,
VkImageLayout final_layout,
bool will_full_fast_clear)
{
const uint32_t depth_plane =
anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_DEPTH_BIT);
if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_NONE)
return;
#if GFX_VER == 12
if ((initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) &&
cmd_buffer->device->physical->has_implicit_ccs &&
cmd_buffer->device->info->has_aux_map) {
anv_image_init_aux_tt(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, 1, base_layer, layer_count);
}
#endif
/* If will_full_fast_clear is set, the caller promises to fast-clear the
* largest portion of the specified range as it can. For depth images,
* that means the entire image because we don't support multi-LOD HiZ.
*/
assert(image->planes[0].primary_surface.isl.levels == 1);
if (will_full_fast_clear)
return;
const enum isl_aux_state initial_state =
anv_layout_to_aux_state(cmd_buffer->device->info, image,
VK_IMAGE_ASPECT_DEPTH_BIT,
initial_layout);
const enum isl_aux_state final_state =
anv_layout_to_aux_state(cmd_buffer->device->info, image,
VK_IMAGE_ASPECT_DEPTH_BIT,
final_layout);
const bool initial_depth_valid =
isl_aux_state_has_valid_primary(initial_state);
const bool initial_hiz_valid =
isl_aux_state_has_valid_aux(initial_state);
const bool final_needs_depth =
isl_aux_state_has_valid_primary(final_state);
const bool final_needs_hiz =
isl_aux_state_has_valid_aux(final_state);
/* Getting into the pass-through state for Depth is tricky and involves
* both a resolve and an ambiguate. We don't handle that state right now
* as anv_layout_to_aux_state never returns it.
*/
assert(final_state != ISL_AUX_STATE_PASS_THROUGH);
if (final_needs_depth && !initial_depth_valid) {
assert(initial_hiz_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_FULL_RESOLVE);
} else if (final_needs_hiz && !initial_hiz_valid) {
assert(initial_depth_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
}
}
/* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
* the initial layout is undefined, the HiZ buffer and depth buffer will
* represent the same data at the end of this operation.
*/
static void
transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
uint32_t base_level, uint32_t level_count,
uint32_t base_layer, uint32_t layer_count,
VkImageLayout initial_layout,
VkImageLayout final_layout,
bool will_full_fast_clear)
{
#if GFX_VER == 12
const uint32_t plane =
anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
return;
if ((initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) &&
cmd_buffer->device->physical->has_implicit_ccs &&
cmd_buffer->device->info->has_aux_map) {
anv_image_init_aux_tt(cmd_buffer, image, VK_IMAGE_ASPECT_STENCIL_BIT,
base_level, level_count, base_layer, layer_count);
/* If will_full_fast_clear is set, the caller promises to fast-clear the
* largest portion of the specified range as it can.
*/
if (will_full_fast_clear)
return;
for (uint32_t l = 0; l < level_count; l++) {
const uint32_t level = base_level + l;
const VkRect2D clear_rect = {
.offset.x = 0,
.offset.y = 0,
.extent.width = anv_minify(image->vk.extent.width, level),
.extent.height = anv_minify(image->vk.extent.height, level),
};
uint32_t aux_layers =
anv_image_aux_layers(image, VK_IMAGE_ASPECT_STENCIL_BIT, level);
uint32_t level_layer_count =
MIN2(layer_count, aux_layers - base_layer);
/* From Bspec's 3DSTATE_STENCIL_BUFFER_BODY > Stencil Compression
* Enable:
*
* "When enabled, Stencil Buffer needs to be initialized via
* stencil clear (HZ_OP) before any renderpass."
*/
anv_image_hiz_clear(cmd_buffer, image, VK_IMAGE_ASPECT_STENCIL_BIT,
level, base_layer, level_layer_count,
clear_rect, 0 /* Stencil clear value */);
}
}
#endif
}
#define MI_PREDICATE_SRC0 0x2400
#define MI_PREDICATE_SRC1 0x2408
#define MI_PREDICATE_RESULT 0x2418
static void
set_image_compressed_bit(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
uint32_t level,
uint32_t base_layer, uint32_t layer_count,
bool compressed)
{
const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
/* We only have compression tracking for CCS_E */
if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E)
return;
for (uint32_t a = 0; a < layer_count; a++) {
uint32_t layer = base_layer + a;
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = anv_image_get_compression_state_addr(cmd_buffer->device,
image, aspect,
level, layer);
sdi.ImmediateData = compressed ? UINT32_MAX : 0;
}
}
}
static void
set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
enum anv_fast_clear_type fast_clear)
{
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = anv_image_get_fast_clear_type_addr(cmd_buffer->device,
image, aspect);
sdi.ImmediateData = fast_clear;
}
/* Whenever we have fast-clear, we consider that slice to be compressed.
* This makes building predicates much easier.
*/
if (fast_clear != ANV_FAST_CLEAR_NONE)
set_image_compressed_bit(cmd_buffer, image, aspect, 0, 0, 1, true);
}
/* This is only really practical on haswell and above because it requires
* MI math in order to get it correct.
*/
static void
anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
uint32_t level, uint32_t array_layer,
enum isl_aux_op resolve_op,
enum anv_fast_clear_type fast_clear_supported)
{
struct mi_builder b;
mi_builder_init(&b, cmd_buffer->device->info, &cmd_buffer->batch);
const struct mi_value fast_clear_type =
mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
image, aspect));
if (resolve_op == ISL_AUX_OP_FULL_RESOLVE) {
/* In this case, we're doing a full resolve which means we want the
* resolve to happen if any compression (including fast-clears) is
* present.
*
* In order to simplify the logic a bit, we make the assumption that,
* if the first slice has been fast-cleared, it is also marked as
* compressed. See also set_image_fast_clear_state.
*/
const struct mi_value compression_state =
mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
image, aspect,
level, array_layer));
mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), compression_state);
mi_store(&b, compression_state, mi_imm(0));
if (level == 0 && array_layer == 0) {
/* If the predicate is true, we want to write 0 to the fast clear type
* and, if it's false, leave it alone. We can do this by writing
*
* clear_type = clear_type & ~predicate;
*/
struct mi_value new_fast_clear_type =
mi_iand(&b, fast_clear_type,
mi_inot(&b, mi_reg64(MI_PREDICATE_SRC0)));
mi_store(&b, fast_clear_type, new_fast_clear_type);
}
} else if (level == 0 && array_layer == 0) {
/* In this case, we are doing a partial resolve to get rid of fast-clear
* colors. We don't care about the compression state but we do care
* about how much fast clear is allowed by the final layout.
*/
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
assert(fast_clear_supported < ANV_FAST_CLEAR_ANY);
/* We need to compute (fast_clear_supported < image->fast_clear) */
struct mi_value pred =
mi_ult(&b, mi_imm(fast_clear_supported), fast_clear_type);
mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), mi_value_ref(&b, pred));
/* If the predicate is true, we want to write 0 to the fast clear type
* and, if it's false, leave it alone. We can do this by writing
*
* clear_type = clear_type & ~predicate;
*/
struct mi_value new_fast_clear_type =
mi_iand(&b, fast_clear_type, mi_inot(&b, pred));
mi_store(&b, fast_clear_type, new_fast_clear_type);
} else {
/* In this case, we're trying to do a partial resolve on a slice that
* doesn't have clear color. There's nothing to do.
*/
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
return;
}
/* Set src1 to 0 and use a != condition */
mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
mip.LoadOperation = LOAD_LOADINV;
mip.CombineOperation = COMBINE_SET;
mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
}
static void
anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
enum isl_format format,
struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect,
uint32_t level, uint32_t array_layer,
enum isl_aux_op resolve_op,
enum anv_fast_clear_type fast_clear_supported)
{
const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
anv_cmd_compute_resolve_predicate(cmd_buffer, image,
aspect, level, array_layer,
resolve_op, fast_clear_supported);
/* CCS_D only supports full resolves and BLORP will assert on us if we try
* to do a partial resolve on a CCS_D surface.
*/
if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D)
resolve_op = ISL_AUX_OP_FULL_RESOLVE;
anv_image_ccs_op(cmd_buffer, image, format, swizzle, aspect,
level, array_layer, 1, resolve_op, NULL, true);
}
static void
anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
enum isl_format format,
struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect,
uint32_t array_layer,
enum isl_aux_op resolve_op,
enum anv_fast_clear_type fast_clear_supported)
{
assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
anv_cmd_compute_resolve_predicate(cmd_buffer, image,
aspect, 0, array_layer,
resolve_op, fast_clear_supported);
anv_image_mcs_op(cmd_buffer, image, format, swizzle, aspect,
array_layer, 1, resolve_op, NULL, true);
}
void
genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
enum isl_aux_usage aux_usage,
uint32_t level,
uint32_t base_layer,
uint32_t layer_count)
{
/* The aspect must be exactly one of the image aspects. */
assert(util_bitcount(aspect) == 1 && (aspect & image->vk.aspects));
/* The only compression types with more than just fast-clears are MCS,
* CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
* track the current fast-clear and compression state. This leaves us
* with just MCS and CCS_E.
*/
if (aux_usage != ISL_AUX_USAGE_CCS_E &&
aux_usage != ISL_AUX_USAGE_MCS)
return;
set_image_compressed_bit(cmd_buffer, image, aspect,
level, base_layer, layer_count, true);
}
static void
init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect)
{
assert(cmd_buffer && image);
assert(image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
set_image_fast_clear_state(cmd_buffer, image, aspect,
ANV_FAST_CLEAR_NONE);
/* Initialize the struct fields that are accessed for fast-clears so that
* the HW restrictions on the field values are satisfied.
*/
struct anv_address addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
const unsigned num_dwords = GFX_VER >= 10 ?
isl_dev->ss.clear_color_state_size / 4 :
isl_dev->ss.clear_value_size / 4;
for (unsigned i = 0; i < num_dwords; i++) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = addr;
sdi.Address.offset += i * 4;
sdi.ImmediateData = 0;
}
}
}
/* Copy the fast-clear value dword(s) between a surface state object and an
* image's fast clear state buffer.
*/
static void
genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
struct anv_state surface_state,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
bool copy_from_surface_state)
{
assert(cmd_buffer && image);
assert(image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
struct anv_address ss_clear_addr =
anv_state_pool_state_address(
&cmd_buffer->device->internal_surface_state_pool,
(struct anv_state) {
.offset = surface_state.offset +
cmd_buffer->device->isl_dev.ss.clear_value_offset
});
const struct anv_address entry_addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
struct mi_builder b;
mi_builder_init(&b, cmd_buffer->device->info, &cmd_buffer->batch);
if (copy_from_surface_state) {
mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
} else {
mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
/* Updating a surface state object may require that the state cache be
* invalidated. From the SKL PRM, Shared Functions -> State -> State
* Caching:
*
* Whenever the RENDER_SURFACE_STATE object in memory pointed to by
* the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
* modified [...], the L1 state cache must be invalidated to ensure
* the new surface or sampler state is fetched from system memory.
*
* In testing, SKL doesn't actually seem to need this, but HSW does.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT,
"after copy_fast_clear_dwords surface state update");
}
}
/**
* @brief Transitions a color buffer from one layout to another.
*
* See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
* more information.
*
* @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
* @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
* this represents the maximum layers to transition at each
* specified miplevel.
*/
static void
transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
VkImageAspectFlagBits aspect,
const uint32_t base_level, uint32_t level_count,
uint32_t base_layer, uint32_t layer_count,
VkImageLayout initial_layout,
VkImageLayout final_layout,
uint64_t src_queue_family,
uint64_t dst_queue_family,
bool will_full_fast_clear)
{
struct anv_device *device = cmd_buffer->device;
const struct intel_device_info *devinfo = device->info;
/* Validate the inputs. */
assert(cmd_buffer);
assert(image && image->vk.aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
/* These values aren't supported for simplicity's sake. */
assert(level_count != VK_REMAINING_MIP_LEVELS &&
layer_count != VK_REMAINING_ARRAY_LAYERS);
/* Ensure the subresource range is valid. */
UNUSED uint64_t last_level_num = base_level + level_count;
const uint32_t max_depth = anv_minify(image->vk.extent.depth, base_level);
UNUSED const uint32_t image_layers = MAX2(image->vk.array_layers, max_depth);
assert((uint64_t)base_layer + layer_count <= image_layers);
assert(last_level_num <= image->vk.mip_levels);
/* If there is a layout transfer, the final layout cannot be undefined or
* preinitialized (VUID-VkImageMemoryBarrier-newLayout-01198).
*/
assert(initial_layout == final_layout ||
(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED));
const struct isl_drm_modifier_info *isl_mod_info =
image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
? isl_drm_modifier_get_info(image->vk.drm_format_mod)
: NULL;
const bool src_queue_external =
src_queue_family == VK_QUEUE_FAMILY_FOREIGN_EXT ||
src_queue_family == VK_QUEUE_FAMILY_EXTERNAL;
const bool dst_queue_external =
dst_queue_family == VK_QUEUE_FAMILY_FOREIGN_EXT ||
dst_queue_family == VK_QUEUE_FAMILY_EXTERNAL;
/* Simultaneous acquire and release on external queues is illegal. */
assert(!src_queue_external || !dst_queue_external);
/* Ownership transition on an external queue requires special action if the
* image has a DRM format modifier because we store image data in
* a driver-private bo which is inaccessible to the external queue.
*/
const bool private_binding_acquire =
src_queue_external &&
anv_image_is_externally_shared(image) &&
anv_image_has_private_binding(image);
const bool private_binding_release =
dst_queue_external &&
anv_image_is_externally_shared(image) &&
anv_image_has_private_binding(image);
if (initial_layout == final_layout &&
!private_binding_acquire && !private_binding_release) {
/* No work is needed. */
return;
}
const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
if (anv_surface_is_valid(&image->planes[plane].shadow_surface) &&
final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
/* This surface is a linear compressed image with a tiled shadow surface
* for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
* we need to ensure the shadow copy is up-to-date.
*/
assert(image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT);
assert(image->vk.aspects == VK_IMAGE_ASPECT_COLOR_BIT);
assert(image->planes[plane].primary_surface.isl.tiling == ISL_TILING_LINEAR);
assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
assert(isl_format_is_compressed(image->planes[plane].primary_surface.isl.format));
assert(plane == 0);
anv_image_copy_to_shadow(cmd_buffer, image,
VK_IMAGE_ASPECT_COLOR_BIT,
base_level, level_count,
base_layer, layer_count);
}
if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
return;
assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR);
/* The following layouts are equivalent for non-linear images. */
const bool initial_layout_undefined =
initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED;
bool must_init_fast_clear_state = false;
bool must_init_aux_surface = false;
if (initial_layout_undefined) {
/* The subresource may have been aliased and populated with arbitrary
* data.
*/
must_init_fast_clear_state = true;
must_init_aux_surface = true;
} else if (private_binding_acquire) {
/* The fast clear state lives in a driver-private bo, and therefore the
* external/foreign queue is unaware of it.
*
* If this is the first time we are accessing the image, then the fast
* clear state is uninitialized.
*
* If this is NOT the first time we are accessing the image, then the fast
* clear state may still be valid and correct due to the resolve during
* our most recent ownership release. However, we do not track the aux
* state with MI stores, and therefore must assume the worst-case: that
* this is the first time we are accessing the image.
*/
assert(image->planes[plane].fast_clear_memory_range.binding ==
ANV_IMAGE_MEMORY_BINDING_PRIVATE);
must_init_fast_clear_state = true;
if (image->planes[plane].aux_surface.memory_range.binding ==
ANV_IMAGE_MEMORY_BINDING_PRIVATE) {
assert(isl_mod_info->aux_usage == ISL_AUX_USAGE_NONE);
/* The aux surface, like the fast clear state, lives in
* a driver-private bo. We must initialize the aux surface for the
* same reasons we must initialize the fast clear state.
*/
must_init_aux_surface = true;
} else {
assert(isl_mod_info->aux_usage != ISL_AUX_USAGE_NONE);
/* The aux surface, unlike the fast clear state, lives in
* application-visible VkDeviceMemory and is shared with the
* external/foreign queue. Therefore, when we acquire ownership of the
* image with a defined VkImageLayout, the aux surface is valid and has
* the aux state required by the modifier.
*/
must_init_aux_surface = false;
}
}
#if GFX_VER == 12
if (initial_layout_undefined) {
if (device->physical->has_implicit_ccs && devinfo->has_aux_map) {
anv_image_init_aux_tt(cmd_buffer, image, aspect,
base_level, level_count,
base_layer, layer_count);
}
}
#else
assert(!(device->physical->has_implicit_ccs && devinfo->has_aux_map));
#endif
if (must_init_fast_clear_state) {
if (base_level == 0 && base_layer == 0)
init_fast_clear_color(cmd_buffer, image, aspect);
}
if (must_init_aux_surface) {
assert(must_init_fast_clear_state);
/* Initialize the aux buffers to enable correct rendering. In order to
* ensure that things such as storage images work correctly, aux buffers
* need to be initialized to valid data.
*
* Having an aux buffer with invalid data is a problem for two reasons:
*
* 1) Having an invalid value in the buffer can confuse the hardware.
* For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
* invalid and leads to the hardware doing strange things. It
* doesn't hang as far as we can tell but rendering corruption can
* occur.
*
* 2) If this transition is into the GENERAL layout and we then use the
* image as a storage image, then we must have the aux buffer in the
* pass-through state so that, if we then go to texture from the
* image, we get the results of our storage image writes and not the
* fast clear color or other random data.
*
* For CCS both of the problems above are real demonstrable issues. In
* that case, the only thing we can do is to perform an ambiguate to
* transition the aux surface into the pass-through state.
*
* For MCS, (2) is never an issue because we don't support multisampled
* storage images. In theory, issue (1) is a problem with MCS but we've
* never seen it in the wild. For 4x and 16x, all bit patters could, in
* theory, be interpreted as something but we don't know that all bit
* patterns are actually valid. For 2x and 8x, you could easily end up
* with the MCS referring to an invalid plane because not all bits of
* the MCS value are actually used. Even though we've never seen issues
* in the wild, it's best to play it safe and initialize the MCS. We
* can use a fast-clear for MCS because we only ever touch from render
* and texture (no image load store).
*/
if (image->vk.samples == 1) {
for (uint32_t l = 0; l < level_count; l++) {
const uint32_t level = base_level + l;
uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
if (base_layer >= aux_layers)
break; /* We will only get fewer layers as level increases */
uint32_t level_layer_count =
MIN2(layer_count, aux_layers - base_layer);
/* If will_full_fast_clear is set, the caller promises to
* fast-clear the largest portion of the specified range as it can.
* For color images, that means only the first LOD and array slice.
*/
if (level == 0 && base_layer == 0 && will_full_fast_clear) {
base_layer++;
level_layer_count--;
if (level_layer_count == 0)
continue;
}
anv_image_ccs_op(cmd_buffer, image,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, level, base_layer, level_layer_count,
ISL_AUX_OP_AMBIGUATE, NULL, false);
if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
set_image_compressed_bit(cmd_buffer, image, aspect,
level, base_layer, level_layer_count,
false);
}
}
} else {
if (image->vk.samples == 4 || image->vk.samples == 16) {
anv_perf_warn(VK_LOG_OBJS(&image->vk.base),
"Doing a potentially unnecessary fast-clear to "
"define an MCS buffer.");
}
/* If will_full_fast_clear is set, the caller promises to fast-clear
* the largest portion of the specified range as it can.
*/
if (will_full_fast_clear)
return;
assert(base_level == 0 && level_count == 1);
anv_image_mcs_op(cmd_buffer, image,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, base_layer, layer_count,
ISL_AUX_OP_FAST_CLEAR, NULL, false);
}
return;
}
enum isl_aux_usage initial_aux_usage =
anv_layout_to_aux_usage(devinfo, image, aspect, 0, initial_layout);
enum isl_aux_usage final_aux_usage =
anv_layout_to_aux_usage(devinfo, image, aspect, 0, final_layout);
enum anv_fast_clear_type initial_fast_clear =
anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
enum anv_fast_clear_type final_fast_clear =
anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
/* We must override the anv_layout_to_* functions because they are unaware of
* acquire/release direction.
*/
if (private_binding_acquire) {
initial_aux_usage = isl_mod_info->aux_usage;
initial_fast_clear = isl_mod_info->supports_clear_color ?
initial_fast_clear : ANV_FAST_CLEAR_NONE;
} else if (private_binding_release) {
final_aux_usage = isl_mod_info->aux_usage;
final_fast_clear = isl_mod_info->supports_clear_color ?
final_fast_clear : ANV_FAST_CLEAR_NONE;
}
/* The current code assumes that there is no mixing of CCS_E and CCS_D.
* We can handle transitions between CCS_D/E to and from NONE. What we
* don't yet handle is switching between CCS_E and CCS_D within a given
* image. Doing so in a performant way requires more detailed aux state
* tracking such as what is done in i965. For now, just assume that we
* only have one type of compression.
*/
assert(initial_aux_usage == ISL_AUX_USAGE_NONE ||
final_aux_usage == ISL_AUX_USAGE_NONE ||
initial_aux_usage == final_aux_usage);
/* If initial aux usage is NONE, there is nothing to resolve */
if (initial_aux_usage == ISL_AUX_USAGE_NONE)
return;
enum isl_aux_op resolve_op = ISL_AUX_OP_NONE;
/* If the initial layout supports more fast clear than the final layout
* then we need at least a partial resolve.
*/
if (final_fast_clear < initial_fast_clear)
resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
if (initial_aux_usage == ISL_AUX_USAGE_CCS_E &&
final_aux_usage != ISL_AUX_USAGE_CCS_E)
resolve_op = ISL_AUX_OP_FULL_RESOLVE;
if (resolve_op == ISL_AUX_OP_NONE)
return;
/* Perform a resolve to synchronize data between the main and aux buffer.
* Before we begin, we must satisfy the cache flushing requirement specified
* in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
*
* Any transition from any value in {Clear, Render, Resolve} to a
* different value in {Clear, Render, Resolve} requires end of pipe
* synchronization.
*
* We perform a flush of the write cache before and after the clear and
* resolve operations to meet this requirement.
*
* Unlike other drawing, fast clear operations are not properly
* synchronized. The first PIPE_CONTROL here likely ensures that the
* contents of the previous render or clear hit the render target before we
* resolve and the second likely ensures that the resolve is complete before
* we do any more rendering or clearing.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after transition RT");
for (uint32_t l = 0; l < level_count; l++) {
uint32_t level = base_level + l;
uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
if (base_layer >= aux_layers)
break; /* We will only get fewer layers as level increases */
uint32_t level_layer_count =
MIN2(layer_count, aux_layers - base_layer);
for (uint32_t a = 0; a < level_layer_count; a++) {
uint32_t array_layer = base_layer + a;
/* If will_full_fast_clear is set, the caller promises to fast-clear
* the largest portion of the specified range as it can. For color
* images, that means only the first LOD and array slice.
*/
if (level == 0 && array_layer == 0 && will_full_fast_clear)
continue;
if (image->vk.samples == 1) {
anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, level, array_layer, resolve_op,
final_fast_clear);
} else {
/* We only support fast-clear on the first layer so partial
* resolves should not be used on other layers as they will use
* the clear color stored in memory that is only valid for layer0.
*/
if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
array_layer != 0)
continue;
anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, array_layer, resolve_op,
final_fast_clear);
}
}
}
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after transition RT");
}
static MUST_CHECK VkResult
anv_cmd_buffer_init_attachments(struct anv_cmd_buffer *cmd_buffer,
uint32_t color_att_count)
{
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
/* Reserve one for the NULL state. */
unsigned num_states = 1 + color_att_count;
const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
gfx->att_states =
anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
num_states * ss_stride, isl_dev->ss.align);
if (gfx->att_states.map == NULL) {
return anv_batch_set_error(&cmd_buffer->batch,
VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
struct anv_state next_state = gfx->att_states;
next_state.alloc_size = isl_dev->ss.size;
gfx->null_surface_state = next_state;
next_state.offset += ss_stride;
next_state.map += ss_stride;
gfx->color_att_count = color_att_count;
for (uint32_t i = 0; i < color_att_count; i++) {
gfx->color_att[i] = (struct anv_attachment) {
.surface_state.state = next_state,
};
next_state.offset += ss_stride;
next_state.map += ss_stride;
}
gfx->depth_att = (struct anv_attachment) { };
gfx->stencil_att = (struct anv_attachment) { };
return VK_SUCCESS;
}
static void
anv_cmd_buffer_reset_rendering(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
gfx->render_area = (VkRect2D) { };
gfx->layer_count = 0;
gfx->samples = 0;
gfx->color_att_count = 0;
gfx->depth_att = (struct anv_attachment) { };
gfx->stencil_att = (struct anv_attachment) { };
gfx->null_surface_state = ANV_STATE_NULL;
}
VkResult
genX(BeginCommandBuffer)(
VkCommandBuffer commandBuffer,
const VkCommandBufferBeginInfo* pBeginInfo)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
VkResult result;
/* If this is the first vkBeginCommandBuffer, we must *initialize* the
* command buffer's state. Otherwise, we must *reset* its state. In both
* cases we reset it.
*
* From the Vulkan 1.0 spec:
*
* If a command buffer is in the executable state and the command buffer
* was allocated from a command pool with the
* VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
* vkBeginCommandBuffer implicitly resets the command buffer, behaving
* as if vkResetCommandBuffer had been called with
* VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
* the command buffer in the recording state.
*/
anv_cmd_buffer_reset(cmd_buffer);
anv_cmd_buffer_reset_rendering(cmd_buffer);
cmd_buffer->usage_flags = pBeginInfo->flags;
/* VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT must be ignored for
* primary level command buffers.
*
* From the Vulkan 1.0 spec:
*
* VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT specifies that a
* secondary command buffer is considered to be entirely inside a render
* pass. If this is a primary command buffer, then this bit is ignored.
*/
if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY)
cmd_buffer->usage_flags &= ~VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT;
trace_intel_begin_cmd_buffer(&cmd_buffer->trace);
genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
/* We sometimes store vertex data in the dynamic state buffer for blorp
* operations and our dynamic state stream may re-use data from previous
* command buffers. In order to prevent stale cache data, we flush the VF
* cache. We could do this on every blorp call but that's not really
* needed as all of the data will get written by the CPU prior to the GPU
* executing anything. The chances are fairly high that they will use
* blorp at least once per primary command buffer so it shouldn't be
* wasted.
*
* There is also a workaround on gfx8 which requires us to invalidate the
* VF cache occasionally. It's easier if we can assume we start with a
* fresh cache (See also genX(cmd_buffer_set_binding_for_gfx8_vb_flush).)
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_VF_CACHE_INVALIDATE_BIT,
"new cmd buffer");
/* Re-emit the aux table register in every command buffer. This way we're
* ensured that we have the table even if this command buffer doesn't
* initialize any images.
*/
if (cmd_buffer->device->info->has_aux_map) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_AUX_TABLE_INVALIDATE_BIT,
"new cmd buffer with aux-tt");
}
/* We send an "Indirect State Pointers Disable" packet at
* EndCommandBuffer, so all push constant packets are ignored during a
* context restore. Documentation says after that command, we need to
* emit push constants again before any rendering operation. So we
* flag them dirty here to make sure they get emitted.
*/
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
if (cmd_buffer->usage_flags &
VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
char gcbiar_data[VK_GCBIARR_DATA_SIZE(MAX_RTS)];
const VkRenderingInfo *resume_info =
vk_get_command_buffer_inheritance_as_rendering_resume(cmd_buffer->vk.level,
pBeginInfo,
gcbiar_data);
if (resume_info != NULL) {
genX(CmdBeginRendering)(commandBuffer, resume_info);
} else {
const VkCommandBufferInheritanceRenderingInfo *inheritance_info =
vk_get_command_buffer_inheritance_rendering_info(cmd_buffer->vk.level,
pBeginInfo);
assert(inheritance_info);
gfx->rendering_flags = inheritance_info->flags;
gfx->render_area = (VkRect2D) { };
gfx->layer_count = 0;
gfx->samples = inheritance_info->rasterizationSamples;
gfx->view_mask = inheritance_info->viewMask;
uint32_t color_att_count = inheritance_info->colorAttachmentCount;
result = anv_cmd_buffer_init_attachments(cmd_buffer, color_att_count);
if (result != VK_SUCCESS)
return result;
for (uint32_t i = 0; i < color_att_count; i++) {
gfx->color_att[i].vk_format =
inheritance_info->pColorAttachmentFormats[i];
}
gfx->depth_att.vk_format =
inheritance_info->depthAttachmentFormat;
gfx->stencil_att.vk_format =
inheritance_info->stencilAttachmentFormat;
anv_cmd_graphic_state_update_has_uint_rt(gfx);
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
}
}
/* Emit the sample pattern at the beginning of the batch because the
* default locations emitted at the device initialization might have been
* changed by a previous command buffer.
*
* Do not change that when we're continuing a previous renderpass.
*/
if (cmd_buffer->device->vk.enabled_extensions.EXT_sample_locations &&
!(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT))
genX(emit_sample_pattern)(&cmd_buffer->batch, NULL);
if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
/* If secondary buffer supports conditional rendering
* we should emit commands as if conditional rendering is enabled.
*/
cmd_buffer->state.conditional_render_enabled =
conditional_rendering_info && conditional_rendering_info->conditionalRenderingEnable;
}
return VK_SUCCESS;
}
/* From the PRM, Volume 2a:
*
* "Indirect State Pointers Disable
*
* At the completion of the post-sync operation associated with this pipe
* control packet, the indirect state pointers in the hardware are
* considered invalid; the indirect pointers are not saved in the context.
* If any new indirect state commands are executed in the command stream
* while the pipe control is pending, the new indirect state commands are
* preserved.
*
* [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
* restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
* commands are only considered as Indirect State Pointers. Once ISP is
* issued in a context, SW must initialize by programming push constant
* commands for all the shaders (at least to zero length) before attempting
* any rendering operation for the same context."
*
* 3DSTATE_CONSTANT_* packets are restored during a context restore,
* even though they point to a BO that has been already unreferenced at
* the end of the previous batch buffer. This has been fine so far since
* we are protected by these scratch page (every address not covered by
* a BO should be pointing to the scratch page). But on CNL, it is
* causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
* instruction.
*
* The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
* hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
* context restore, so the mentioned hang doesn't happen. However,
* software must program push constant commands for all stages prior to
* rendering anything. So we flag them dirty in BeginCommandBuffer.
*
* Finally, we also make sure to stall at pixel scoreboard to make sure the
* constants have been loaded into the EUs prior to disable the push constants
* so that it doesn't hang a previous 3DPRIMITIVE.
*/
static void
emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
{
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.StallAtPixelScoreboard = true;
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.IndirectStatePointersDisable = true;
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
}
VkResult
genX(EndCommandBuffer)(
VkCommandBuffer commandBuffer)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
if (anv_batch_has_error(&cmd_buffer->batch))
return cmd_buffer->batch.status;
anv_measure_endcommandbuffer(cmd_buffer);
/* We want every command buffer to start with the PMA fix in a known state,
* so we disable it at the end of the command buffer.
*/
genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
emit_isp_disable(cmd_buffer);
trace_intel_end_cmd_buffer(&cmd_buffer->trace, cmd_buffer->vk.level);
anv_cmd_buffer_end_batch_buffer(cmd_buffer);
return VK_SUCCESS;
}
void
genX(CmdExecuteCommands)(
VkCommandBuffer commandBuffer,
uint32_t commandBufferCount,
const VkCommandBuffer* pCmdBuffers)
{
ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
assert(primary->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
if (anv_batch_has_error(&primary->batch))
return;
/* The secondary command buffers will assume that the PMA fix is disabled
* when they begin executing. Make sure this is true.
*/
genX(cmd_buffer_enable_pma_fix)(primary, false);
/* The secondary command buffer doesn't know which textures etc. have been
* flushed prior to their execution. Apply those flushes now.
*/
genX(cmd_buffer_apply_pipe_flushes)(primary);
for (uint32_t i = 0; i < commandBufferCount; i++) {
ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
assert(secondary->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
assert(!anv_batch_has_error(&secondary->batch));
if (secondary->state.conditional_render_enabled) {
if (!primary->state.conditional_render_enabled) {
/* Secondary buffer is constructed as if it will be executed
* with conditional rendering, we should satisfy this dependency
* regardless of conditional rendering being enabled in primary.
*/
struct mi_builder b;
mi_builder_init(&b, primary->device->info, &primary->batch);
mi_store(&b, mi_reg64(ANV_PREDICATE_RESULT_REG),
mi_imm(UINT64_MAX));
}
}
if (secondary->usage_flags &
VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
/* If we're continuing a render pass from the primary, we need to
* copy the surface states for the current subpass into the storage
* we allocated for them in BeginCommandBuffer.
*/
struct anv_state src_state = primary->state.gfx.att_states;
struct anv_state dst_state = secondary->state.gfx.att_states;
assert(src_state.alloc_size == dst_state.alloc_size);
genX(cmd_buffer_so_memcpy)(
primary,
anv_state_pool_state_address(&primary->device->internal_surface_state_pool,
dst_state),
anv_state_pool_state_address(&primary->device->internal_surface_state_pool,
src_state),
src_state.alloc_size);
}
anv_cmd_buffer_add_secondary(primary, secondary);
assert(secondary->perf_query_pool == NULL || primary->perf_query_pool == NULL ||
secondary->perf_query_pool == primary->perf_query_pool);
if (secondary->perf_query_pool)
primary->perf_query_pool = secondary->perf_query_pool;
#if GFX_VERx10 == 120
if (secondary->state.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN)
primary->state.depth_reg_mode = secondary->state.depth_reg_mode;
#endif
}
/* The secondary isn't counted in our VF cache tracking so we need to
* invalidate the whole thing.
*/
if (GFX_VER == 9) {
anv_add_pending_pipe_bits(primary,
ANV_PIPE_CS_STALL_BIT | ANV_PIPE_VF_CACHE_INVALIDATE_BIT,
"Secondary cmd buffer not tracked in VF cache");
}
/* The secondary may have selected a different pipeline (3D or compute) and
* may have changed the current L3$ configuration. Reset our tracking
* variables to invalid values to ensure that we re-emit these in the case
* where we do any draws or compute dispatches from the primary after the
* secondary has returned.
*/
primary->state.current_pipeline = UINT32_MAX;
primary->state.current_l3_config = NULL;
primary->state.current_hash_scale = 0;
primary->state.gfx.push_constant_stages = 0;
vk_dynamic_graphics_state_dirty_all(&primary->vk.dynamic_graphics_state);
/* Each of the secondary command buffers will use its own state base
* address. We need to re-emit state base address for the primary after
* all of the secondaries are done.
*
* TODO: Maybe we want to make this a dirty bit to avoid extra state base
* address calls?
*/
genX(cmd_buffer_emit_state_base_address)(primary);
}
/**
* Program the hardware to use the specified L3 configuration.
*/
void
genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
const struct intel_l3_config *cfg)
{
assert(cfg || GFX_VER >= 12);
if (cfg == cmd_buffer->state.current_l3_config)
return;
#if GFX_VER >= 11
/* On Gfx11+ we use only one config, so verify it remains the same and skip
* the stalling programming entirely.
*/
assert(cfg == cmd_buffer->device->l3_config);
#else
if (INTEL_DEBUG(DEBUG_L3)) {
mesa_logd("L3 config transition: ");
intel_dump_l3_config(cfg, stderr);
}
/* According to the hardware docs, the L3 partitioning can only be changed
* while the pipeline is completely drained and the caches are flushed,
* which involves a first PIPE_CONTROL flush which stalls the pipeline...
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DCFlushEnable = true;
pc.PostSyncOperation = NoWrite;
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
/* ...followed by a second pipelined PIPE_CONTROL that initiates
* invalidation of the relevant caches. Note that because RO invalidation
* happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
* command is processed by the CS) we cannot combine it with the previous
* stalling flush as the hardware documentation suggests, because that
* would cause the CS to stall on previous rendering *after* RO
* invalidation and wouldn't prevent the RO caches from being polluted by
* concurrent rendering before the stall completes. This intentionally
* doesn't implement the SKL+ hardware workaround suggesting to enable CS
* stall on PIPE_CONTROLs with the texture cache invalidation bit set for
* GPGPU workloads because the previous and subsequent PIPE_CONTROLs
* already guarantee that there is no concurrent GPGPU kernel execution
* (see SKL HSD 2132585).
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
pc.ConstantCacheInvalidationEnable = true;
pc.InstructionCacheInvalidateEnable = true;
pc.StateCacheInvalidationEnable = true;
pc.PostSyncOperation = NoWrite;
anv_debug_dump_pc(pc);
}
/* Now send a third stalling flush to make sure that invalidation is
* complete when the L3 configuration registers are modified.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DCFlushEnable = true;
pc.PostSyncOperation = NoWrite;
pc.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pc);
}
genX(emit_l3_config)(&cmd_buffer->batch, cmd_buffer->device, cfg);
#endif /* GFX_VER >= 11 */
cmd_buffer->state.current_l3_config = cfg;
}
ALWAYS_INLINE enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
struct anv_device *device,
uint32_t current_pipeline,
enum anv_pipe_bits bits)
{
#if GFX_VER >= 12
/* From the TGL PRM, Volume 2a, "PIPE_CONTROL":
*
* "SW must follow below programming restrictions when programming
* PIPE_CONTROL command [for ComputeCS]:
* ...
* Following bits must not be set when programmed for ComputeCS:
* - "Render Target Cache Flush Enable", "Depth Cache Flush Enable"
* and "Tile Cache Flush Enable"
* - "Depth Stall Enable", Stall at Pixel Scoreboard and
* "PSD Sync Enable".
* - "OVR Tile 0 Flush", "TBIMR Force Batch Closure",
* "AMFS Flush Enable", "VF Cache Invalidation Enable" and
* "Global Snapshot Count Reset"."
*
* XXX: According to spec this should not be a concern for a regular
* RCS in GPGPU mode, but during testing it was found that at least
* "VF Cache Invalidation Enable" bit is ignored in such case.
* This can cause us to miss some important invalidations
* (e.g. from CmdPipelineBarriers) and have incoherent data.
*
* There is also a Wa_1606932921 "RCS is not waking up fixed function clock
* when specific 3d related bits are programmed in pipecontrol in
* compute mode" that suggests us not to use "RT Cache Flush" in GPGPU mode.
*
* The other bits are not confirmed to cause problems, but included here
* just to be safe, as they're also not really relevant in the GPGPU mode,
* and having them doesn't seem to cause any regressions.
*
* So if we're currently in GPGPU mode, we hide some bits from
* this flush, and will flush them only when we'll be able to.
* Similar thing with GPGPU-only bits.
*/
enum anv_pipe_bits defer_bits = bits &
(current_pipeline == GPGPU ? ANV_PIPE_GFX_BITS: ANV_PIPE_GPGPU_BITS);
bits &= ~defer_bits;
#endif
/*
* From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
*
* Write synchronization is a special case of end-of-pipe
* synchronization that requires that the render cache and/or depth
* related caches are flushed to memory, where the data will become
* globally visible. This type of synchronization is required prior to
* SW (CPU) actually reading the result data from memory, or initiating
* an operation that will use as a read surface (such as a texture
* surface) a previous render target and/or depth/stencil buffer
*
*
* From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
*
* Exercising the write cache flush bits (Render Target Cache Flush
* Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
* ensures the write caches are flushed and doesn't guarantee the data
* is globally visible.
*
* SW can track the completion of the end-of-pipe-synchronization by
* using "Notify Enable" and "PostSync Operation - Write Immediate
* Data" in the PIPE_CONTROL command.
*
* In other words, flushes are pipelined while invalidations are handled
* immediately. Therefore, if we're flushing anything then we need to
* schedule an end-of-pipe sync before any invalidations can happen.
*/
if (bits & ANV_PIPE_FLUSH_BITS)
bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
/* HSD 1209978178: docs say that before programming the aux table:
*
* "Driver must ensure that the engine is IDLE but ensure it doesn't
* add extra flushes in the case it knows that the engine is already
* IDLE."
*/
if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
/* If we're going to do an invalidate and we have a pending end-of-pipe
* sync that has yet to be resolved, we do the end-of-pipe sync now.
*/
if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
(bits & ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT)) {
bits |= ANV_PIPE_END_OF_PIPE_SYNC_BIT;
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be
* programmed prior to programming a PIPECONTROL command with "LRI
* Post Sync Operation" in GPGPU mode of operation (i.e when
* PIPELINE_SELECT command is set to GPGPU mode of operation)."
*
* The same text exists a few rows below for Post Sync Op.
*/
if (bits & ANV_PIPE_POST_SYNC_BIT) {
if (GFX_VER == 9 && current_pipeline == GPGPU)
bits |= ANV_PIPE_CS_STALL_BIT;
bits &= ~ANV_PIPE_POST_SYNC_BIT;
}
if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
ANV_PIPE_END_OF_PIPE_SYNC_BIT)) {
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
#if GFX_VERx10 >= 125
/* BSpec 47112: PIPE_CONTROL::Untyped Data-Port Cache Flush:
*
* "'HDC Pipeline Flush' bit must be set for this bit to take
* effect."
*
* BSpec 47112: PIPE_CONTROL::HDC Pipeline Flush:
*
* "When the "Pipeline Select" mode in PIPELINE_SELECT command is
* set to "3D", HDC Pipeline Flush can also flush/invalidate the
* LSC Untyped L1 cache based on the programming of HDC_Chicken0
* register bits 13:11."
*
* "When the 'Pipeline Select' mode is set to 'GPGPU', the LSC
* Untyped L1 cache flush is controlled by 'Untyped Data-Port
* Cache Flush' bit in the PIPE_CONTROL command."
*
* As part of Wa_1608949956 & Wa_14010198302, i915 is programming
* HDC_CHICKEN0[11:13] = 0 ("Untyped L1 is flushed, for both 3D
* Pipecontrol Dataport flush, and UAV coherency barrier event").
* So there is no need to set "Untyped Data-Port Cache" in 3D
* mode.
*/
pipe.UntypedDataPortCacheFlushEnable =
(bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT) &&
current_pipeline == GPGPU;
pipe.HDCPipelineFlushEnable |= pipe.UntypedDataPortCacheFlushEnable;
#endif
#if GFX_VER >= 12
pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe.HDCPipelineFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
#else
/* Flushing HDC pipeline requires DC Flush on earlier HW. */
pipe.DCFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
#endif
pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
pipe.DCFlushEnable |= bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
#if GFX_VER >= 12
pipe.DepthStallEnable =
pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT);
#else
pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
#endif
#if GFX_VERx10 >= 125
pipe.PSSStallSyncEnable = bits & ANV_PIPE_PSS_STALL_SYNC_BIT;
#endif
pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
/* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
*
* "The most common action to perform upon reaching a
* synchronization point is to write a value out to memory. An
* immediate value (included with the synchronization command) may
* be written."
*
*
* From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
*
* "In case the data flushed out by the render engine is to be
* read back in to the render engine in coherent manner, then the
* render engine has to wait for the fence completion before
* accessing the flushed data. This can be achieved by following
* means on various products: PIPE_CONTROL command with CS Stall
* and the required write caches flushed with Post-Sync-Operation
* as Write Immediate Data.
*
* Example:
* - Workload-1 (3D/GPGPU/MEDIA)
* - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
* Immediate Data, Required Write Cache Flush bits set)
* - Workload-2 (Can use the data produce or output by
* Workload-1)
*/
if (bits & ANV_PIPE_END_OF_PIPE_SYNC_BIT) {
pipe.CommandStreamerStallEnable = true;
pipe.PostSyncOperation = WriteImmediateData;
pipe.Address = device->workaround_address;
}
/*
* According to the Broadwell documentation, any PIPE_CONTROL with the
* "Command Streamer Stall" bit set must also have another bit set,
* with five different options:
*
* - Render Target Cache Flush
* - Depth Cache Flush
* - Stall at Pixel Scoreboard
* - Post-Sync Operation
* - Depth Stall
* - DC Flush Enable
*
* I chose "Stall at Pixel Scoreboard" since that's what we use in
* mesa and it seems to work fine. The choice is fairly arbitrary.
*/
if (pipe.CommandStreamerStallEnable &&
!pipe.RenderTargetCacheFlushEnable &&
!pipe.DepthCacheFlushEnable &&
!pipe.StallAtPixelScoreboard &&
!pipe.PostSyncOperation &&
!pipe.DepthStallEnable &&
!pipe.DCFlushEnable)
pipe.StallAtPixelScoreboard = true;
anv_debug_dump_pc(pipe);
}
/* If a render target flush was emitted, then we can toggle off the bit
* saying that render target writes are ongoing.
*/
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
ANV_PIPE_END_OF_PIPE_SYNC_BIT);
}
if (bits & ANV_PIPE_INVALIDATE_BITS) {
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "If the VF Cache Invalidation Enable is set to a 1 in a
* PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
* 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
* prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
* a 1."
*
* This appears to hang Broadwell, so we restrict it to just gfx9.
*/
if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe);
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
pipe.StateCacheInvalidationEnable =
bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
pipe.ConstantCacheInvalidationEnable =
bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
#if GFX_VER >= 12
/* Invalidates the L3 cache part in which index & vertex data is loaded
* when VERTEX_BUFFER_STATE::L3BypassDisable is set.
*/
pipe.L3ReadOnlyCacheInvalidationEnable =
bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
#endif
pipe.VFCacheInvalidationEnable =
bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
pipe.TextureCacheInvalidationEnable =
bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
pipe.InstructionCacheInvalidateEnable =
bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache
* Invalidation Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
if (current_pipeline == GPGPU && pipe.TextureCacheInvalidationEnable)
pipe.CommandStreamerStallEnable = true;
#endif
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "When VF Cache Invalidate is set “Post Sync Operation” must be
* enabled to “Write Immediate Data” or “Write PS Depth Count” or
* “Write Timestamp”.
*/
if (GFX_VER == 9 && pipe.VFCacheInvalidationEnable) {
pipe.PostSyncOperation = WriteImmediateData;
pipe.Address = device->workaround_address;
}
anv_debug_dump_pc(pipe);
}
#if GFX_VER == 12
if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info->has_aux_map) {
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num);
lri.DataDWord = 1;
}
}
#endif
bits &= ~ANV_PIPE_INVALIDATE_BITS;
}
#if GFX_VER >= 12
bits |= defer_bits;
#endif
return bits;
}
ALWAYS_INLINE void
genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
{
#if GFX_VERx10 == 120
/* If we're changing the state of the RHWO optimization, we need to have
* sb_stall+cs_stall.
*/
const bool rhwo_opt_change =
cmd_buffer->state.rhwo_optimization_enabled !=
cmd_buffer->state.pending_rhwo_optimization_enabled;
if (rhwo_opt_change) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_STALL_AT_SCOREBOARD_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"change RHWO optimization");
}
#endif
enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
if (unlikely(cmd_buffer->device->physical->always_flush_cache))
bits |= ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS;
else if (bits == 0)
return;
bool trace_flush =
(bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS | ANV_PIPE_INVALIDATE_BITS)) != 0;
if (trace_flush)
trace_intel_begin_stall(&cmd_buffer->trace);
if (GFX_VER == 9 &&
(bits & ANV_PIPE_CS_STALL_BIT) &&
(bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
/* If we are doing a VF cache invalidate AND a CS stall (it must be
* both) then we can reset our vertex cache tracking.
*/
memset(cmd_buffer->state.gfx.vb_dirty_ranges, 0,
sizeof(cmd_buffer->state.gfx.vb_dirty_ranges));
memset(&cmd_buffer->state.gfx.ib_dirty_range, 0,
sizeof(cmd_buffer->state.gfx.ib_dirty_range));
}
cmd_buffer->state.pending_pipe_bits =
genX(emit_apply_pipe_flushes)(&cmd_buffer->batch,
cmd_buffer->device,
cmd_buffer->state.current_pipeline,
bits);
#if GFX_VERx10 == 120
/* Wa_1508744258 handling */
if (rhwo_opt_change) {
anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
c1.RCCRHWOOptimizationDisable =
!cmd_buffer->state.pending_rhwo_optimization_enabled;
c1.RCCRHWOOptimizationDisableMask = true;
}
cmd_buffer->state.rhwo_optimization_enabled =
cmd_buffer->state.pending_rhwo_optimization_enabled;
}
#endif
if (trace_flush) {
trace_intel_end_stall(&cmd_buffer->trace, bits,
anv_pipe_flush_bit_to_ds_stall_flag, NULL);
}
}
static void
cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
const VkDependencyInfo *dep_info,
const char *reason)
{
/* XXX: Right now, we're really dumb and just flush whatever categories
* the app asks for. One of these days we may make this a bit better
* but right now that's all the hardware allows for in most areas.
*/
VkAccessFlags2 src_flags = 0;
VkAccessFlags2 dst_flags = 0;
for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
src_flags |= dep_info->pMemoryBarriers[i].srcAccessMask;
dst_flags |= dep_info->pMemoryBarriers[i].dstAccessMask;
}
for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
src_flags |= dep_info->pBufferMemoryBarriers[i].srcAccessMask;
dst_flags |= dep_info->pBufferMemoryBarriers[i].dstAccessMask;
}
for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
const VkImageMemoryBarrier2 *img_barrier =
&dep_info->pImageMemoryBarriers[i];
src_flags |= img_barrier->srcAccessMask;
dst_flags |= img_barrier->dstAccessMask;
ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
uint32_t base_layer, layer_count;
if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
base_layer = 0;
layer_count = anv_minify(image->vk.extent.depth, range->baseMipLevel);
} else {
base_layer = range->baseArrayLayer;
layer_count = vk_image_subresource_layer_count(&image->vk, range);
}
const uint32_t level_count =
vk_image_subresource_level_count(&image->vk, range);
if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
transition_depth_buffer(cmd_buffer, image,
base_layer, layer_count,
img_barrier->oldLayout,
img_barrier->newLayout,
false /* will_full_fast_clear */);
}
if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
transition_stencil_buffer(cmd_buffer, image,
range->baseMipLevel, level_count,
base_layer, layer_count,
img_barrier->oldLayout,
img_barrier->newLayout,
false /* will_full_fast_clear */);
}
if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
VkImageAspectFlags color_aspects =
vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
range->baseMipLevel, level_count,
base_layer, layer_count,
img_barrier->oldLayout,
img_barrier->newLayout,
img_barrier->srcQueueFamilyIndex,
img_barrier->dstQueueFamilyIndex,
false /* will_full_fast_clear */);
}
}
}
enum anv_pipe_bits bits =
anv_pipe_flush_bits_for_access_flags(cmd_buffer->device, src_flags) |
anv_pipe_invalidate_bits_for_access_flags(cmd_buffer->device, dst_flags);
anv_add_pending_pipe_bits(cmd_buffer, bits, reason);
}
void genX(CmdPipelineBarrier2)(
VkCommandBuffer commandBuffer,
const VkDependencyInfo* pDependencyInfo)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
cmd_buffer_barrier(cmd_buffer, pDependencyInfo, "pipe barrier");
}
static void
cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
{
VkShaderStageFlags stages =
cmd_buffer->state.gfx.pipeline->active_stages;
/* In order to avoid thrash, we assume that vertex and fragment stages
* always exist. In the rare case where one is missing *and* the other
* uses push concstants, this may be suboptimal. However, avoiding stalls
* seems more important.
*/
stages |= VK_SHADER_STAGE_FRAGMENT_BIT;
if (anv_pipeline_is_primitive(cmd_buffer->state.gfx.pipeline))
stages |= VK_SHADER_STAGE_VERTEX_BIT;
if (stages == cmd_buffer->state.gfx.push_constant_stages)
return;
const unsigned push_constant_kb =
cmd_buffer->device->info->max_constant_urb_size_kb;
const unsigned num_stages =
util_bitcount(stages & VK_SHADER_STAGE_ALL_GRAPHICS);
unsigned size_per_stage = push_constant_kb / num_stages;
/* Broadwell+ and Haswell gt3 require that the push constant sizes be in
* units of 2KB. Incidentally, these are the same platforms that have
* 32KB worth of push constant space.
*/
if (push_constant_kb == 32)
size_per_stage &= ~1u;
uint32_t kb_used = 0;
for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
unsigned push_size = (stages & (1 << i)) ? size_per_stage : 0;
anv_batch_emit(&cmd_buffer->batch,
GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
alloc._3DCommandSubOpcode = 18 + i;
alloc.ConstantBufferOffset = (push_size > 0) ? kb_used : 0;
alloc.ConstantBufferSize = push_size;
}
kb_used += push_size;
}
anv_batch_emit(&cmd_buffer->batch,
GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
alloc.ConstantBufferOffset = kb_used;
alloc.ConstantBufferSize = push_constant_kb - kb_used;
}
#if GFX_VERx10 == 125
/* Wa_22011440098
*
* In 3D mode, after programming push constant alloc command immediately
* program push constant command(ZERO length) without any commit between
* them.
*/
if (intel_device_info_is_dg2(cmd_buffer->device->info)) {
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
/* Update empty push constants for all stages (bitmask = 11111b) */
c.ShaderUpdateEnable = 0x1f;
c.MOCS = anv_mocs(cmd_buffer->device, NULL, 0);
}
}
#endif
cmd_buffer->state.gfx.push_constant_stages = stages;
/* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
*
* "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
* the next 3DPRIMITIVE command after programming the
* 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
*
* Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
* pipeline setup, we need to dirty push constants.
*/
cmd_buffer->state.push_constants_dirty |= stages;
}
static VkResult
emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *pipe_state,
struct anv_shader_bin *shader,
struct anv_state *bt_state)
{
uint32_t state_offset;
struct anv_pipeline_bind_map *map = &shader->bind_map;
if (map->surface_count == 0) {
*bt_state = (struct anv_state) { 0, };
return VK_SUCCESS;
}
*bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
map->surface_count,
&state_offset);
uint32_t *bt_map = bt_state->map;
if (bt_state->map == NULL)
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
/* Note that we always keep all user-allocated memory objects resident. */
struct anv_push_constants *push = &pipe_state->push_constants;
for (uint32_t s = 0; s < map->surface_count; s++) {
struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
struct anv_state surface_state;
switch (binding->set) {
case ANV_DESCRIPTOR_SET_NULL:
bt_map[s] = 0;
break;
case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS:
/* Color attachment binding */
assert(shader->stage == MESA_SHADER_FRAGMENT);
if (binding->index < cmd_buffer->state.gfx.color_att_count) {
const struct anv_attachment *att =
&cmd_buffer->state.gfx.color_att[binding->index];
surface_state = att->surface_state.state;
} else {
surface_state = cmd_buffer->state.gfx.null_surface_state;
}
assert(surface_state.map);
bt_map[s] = surface_state.offset + state_offset;
break;
case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: {
/* This is always the first binding for compute shaders */
assert(shader->stage == MESA_SHADER_COMPUTE && s == 0);
struct anv_state surface_state =
anv_cmd_buffer_alloc_surface_state(cmd_buffer);
const enum isl_format format =
anv_isl_format_for_descriptor_type(cmd_buffer->device,
VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
format, ISL_SWIZZLE_IDENTITY,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
cmd_buffer->state.compute.num_workgroups,
12, 1);
assert(surface_state.map);
bt_map[s] = surface_state.offset + state_offset;
break;
}
case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
struct anv_descriptor_set *set =
pipe_state->descriptors[binding->index];
/* If the shader doesn't access the set buffer, just put the null
* surface.
*/
if (set->is_push && !shader->push_desc_info.used_set_buffer) {
bt_map[s] = 0;
break;
}
/* This is a descriptor set buffer so the set index is actually
* given by binding->binding. (Yes, that's confusing.)
*/
assert(set->desc_mem.alloc_size);
assert(set->desc_surface_state.alloc_size);
bt_map[s] = set->desc_surface_state.offset + state_offset;
add_surface_reloc(cmd_buffer, set->desc_surface_state,
anv_descriptor_set_address(set));
break;
}
default: {
assert(binding->set < MAX_SETS);
const struct anv_descriptor_set *set =
pipe_state->descriptors[binding->set];
if (binding->index >= set->descriptor_count) {
/* From the Vulkan spec section entitled "DescriptorSet and
* Binding Assignment":
*
* "If the array is runtime-sized, then array elements greater
* than or equal to the size of that binding in the bound
* descriptor set must not be used."
*
* Unfortunately, the compiler isn't smart enough to figure out
* when a dynamic binding isn't used so it may grab the whole
* array and stick it in the binding table. In this case, it's
* safe to just skip those bindings that are OOB.
*/
assert(binding->index < set->layout->descriptor_count);
continue;
}
/* For push descriptor, if the binding is fully promoted to push
* constants, just reference the null surface in the binding table.
* It's unused and we didn't allocate/pack a surface state for it .
*/
if (set->is_push) {
uint32_t desc_idx = set->layout->binding[binding->binding].descriptor_index;
assert(desc_idx < MAX_PUSH_DESCRIPTORS);
if (shader->push_desc_info.fully_promoted_ubo_descriptors & BITFIELD_BIT(desc_idx)) {
surface_state = anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
break;
}
}
const struct anv_descriptor *desc = &set->descriptors[binding->index];
/* Relative offset in the STATE_BASE_ADDRESS::SurfaceStateBaseAddress
* heap. Depending on where the descriptor surface state is
* allocated, they can either come from
* device->internal_surface_state_pool or
* device->bindless_surface_state_pool.
*/
switch (desc->type) {
case VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR:
case VK_DESCRIPTOR_TYPE_SAMPLER:
/* Nothing for us to do here */
continue;
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: {
if (desc->image_view) {
struct anv_surface_state sstate =
(desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
desc->image_view->planes[binding->plane].general_sampler_surface_state :
desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
surface_state =
anv_bindless_state_for_binding_table(sstate.state);
assert(surface_state.alloc_size);
} else {
surface_state =
anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
}
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
if (desc->image_view) {
struct anv_surface_state sstate =
binding->lowered_storage_surface
? desc->image_view->planes[binding->plane].lowered_storage_surface_state
: desc->image_view->planes[binding->plane].storage_surface_state;
const bool lowered_surface_state_is_null =
desc->image_view->planes[binding->plane].lowered_surface_state_is_null;
surface_state = anv_bindless_state_for_binding_table(sstate.state);
assert(surface_state.alloc_size);
if (binding->lowered_storage_surface && lowered_surface_state_is_null) {
mesa_loge("Bound a image to a descriptor where the "
"descriptor does not have NonReadable "
"set and the image does not have a "
"corresponding SPIR-V format enum.");
vk_debug_report(&cmd_buffer->device->physical->instance->vk,
VK_DEBUG_REPORT_ERROR_BIT_EXT,
&desc->image_view->vk.base,
__LINE__, 0, "anv",
"Bound a image to a descriptor where the "
"descriptor does not have NonReadable "
"set and the image does not have a "
"corresponding SPIR-V format enum.");
}
} else {
surface_state = anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
}
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
if (desc->set_buffer_view) {
surface_state = desc->set_buffer_view->surface_state;
assert(surface_state.alloc_size);
} else {
surface_state = anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
if (desc->buffer_view) {
surface_state = anv_bindless_state_for_binding_table(
desc->buffer_view->surface_state);
assert(surface_state.alloc_size);
} else {
surface_state = anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
if (desc->buffer) {
/* Compute the offset within the buffer */
uint32_t dynamic_offset =
push->dynamic_offsets[binding->dynamic_offset_index];
uint64_t offset = desc->offset + dynamic_offset;
/* Clamp to the buffer size */
offset = MIN2(offset, desc->buffer->vk.size);
/* Clamp the range to the buffer size */
uint32_t range = MIN2(desc->range, desc->buffer->vk.size - offset);
/* Align the range for consistency */
if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC)
range = align_u32(range, ANV_UBO_ALIGNMENT);
struct anv_address address =
anv_address_add(desc->buffer->address, offset);
surface_state = anv_cmd_buffer_alloc_surface_state(cmd_buffer);
enum isl_format format =
anv_isl_format_for_descriptor_type(cmd_buffer->device,
desc->type);
isl_surf_usage_flags_t usage =
desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ?
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT :
ISL_SURF_USAGE_STORAGE_BIT;
anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
format, ISL_SWIZZLE_IDENTITY,
usage, address, range, 1);
} else {
surface_state =
anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
}
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
if (desc->buffer_view) {
surface_state = anv_bindless_state_for_binding_table(
binding->lowered_storage_surface
? desc->buffer_view->lowered_storage_surface_state
: desc->buffer_view->storage_surface_state);
assert(surface_state.alloc_size);
} else {
surface_state = anv_bindless_state_for_binding_table(
cmd_buffer->device->null_surface_state);
}
break;
default:
assert(!"Invalid descriptor type");
continue;
}
assert(surface_state.map);
bt_map[s] = surface_state.offset + state_offset;
break;
}
}
}
return VK_SUCCESS;
}
static VkResult
emit_samplers(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *pipe_state,
struct anv_shader_bin *shader,
struct anv_state *state)
{
struct anv_pipeline_bind_map *map = &shader->bind_map;
if (map->sampler_count == 0) {
*state = (struct anv_state) { 0, };
return VK_SUCCESS;
}
uint32_t size = map->sampler_count * 16;
*state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
if (state->map == NULL)
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
for (uint32_t s = 0; s < map->sampler_count; s++) {
struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
const struct anv_descriptor *desc =
&pipe_state->descriptors[binding->set]->descriptors[binding->index];
if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
continue;
struct anv_sampler *sampler = desc->sampler;
/* This can happen if we have an unfilled slot since TYPE_SAMPLER
* happens to be zero.
*/
if (sampler == NULL)
continue;
memcpy(state->map + (s * 16),
sampler->state[binding->plane], sizeof(sampler->state[0]));
}
return VK_SUCCESS;
}
static uint32_t
flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *pipe_state,
const VkShaderStageFlags dirty,
struct anv_shader_bin **shaders,
uint32_t num_shaders)
{
VkShaderStageFlags flushed = 0;
VkResult result = VK_SUCCESS;
for (uint32_t i = 0; i < num_shaders; i++) {
if (!shaders[i])
continue;
gl_shader_stage stage = shaders[i]->stage;
VkShaderStageFlags vk_stage = mesa_to_vk_shader_stage(stage);
if ((vk_stage & dirty) == 0)
continue;
assert(stage < ARRAY_SIZE(cmd_buffer->state.samplers));
result = emit_samplers(cmd_buffer, pipe_state, shaders[i],
&cmd_buffer->state.samplers[stage]);
if (result != VK_SUCCESS)
break;
assert(stage < ARRAY_SIZE(cmd_buffer->state.binding_tables));
result = emit_binding_table(cmd_buffer, pipe_state, shaders[i],
&cmd_buffer->state.binding_tables[stage]);
if (result != VK_SUCCESS)
break;
flushed |= vk_stage;
}
if (result != VK_SUCCESS) {
assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
if (result != VK_SUCCESS)
return 0;
/* Re-emit state base addresses so we get the new surface state base
* address before we start emitting binding tables etc.
*/
genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
/* Re-emit all active binding tables */
flushed = 0;
for (uint32_t i = 0; i < num_shaders; i++) {
if (!shaders[i])
continue;
gl_shader_stage stage = shaders[i]->stage;
result = emit_samplers(cmd_buffer, pipe_state, shaders[i],
&cmd_buffer->state.samplers[stage]);
if (result != VK_SUCCESS) {
anv_batch_set_error(&cmd_buffer->batch, result);
return 0;
}
result = emit_binding_table(cmd_buffer, pipe_state, shaders[i],
&cmd_buffer->state.binding_tables[stage]);
if (result != VK_SUCCESS) {
anv_batch_set_error(&cmd_buffer->batch, result);
return 0;
}
flushed |= mesa_to_vk_shader_stage(stage);
}
}
return flushed;
}
/* This functions generates surface states used by a pipeline for push
* descriptors. This is delayed to the draw/dispatch time to avoid allocation
* and surface state generation when a pipeline is not going to use the
* binding table to access any push descriptor data.
*/
static void
flush_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
struct anv_cmd_pipeline_state *state,
struct anv_pipeline *pipeline)
{
struct anv_descriptor_set *set = &state->push_descriptor->set;
struct anv_descriptor_set_layout *layout = set->layout;
if (pipeline->use_push_descriptor) {
while (set->generate_surface_states) {
int desc_idx = u_bit_scan(&set->generate_surface_states);
struct anv_descriptor *desc = &set->descriptors[desc_idx];
struct anv_buffer_view *bview = desc->set_buffer_view;
if (bview != NULL) {
bview->surface_state = anv_cmd_buffer_alloc_surface_state(cmd_buffer);
anv_descriptor_write_surface_state(cmd_buffer->device, desc,
bview->surface_state);
}
}
}
if (pipeline->use_push_descriptor_buffer) {
enum isl_format format =
anv_isl_format_for_descriptor_type(cmd_buffer->device,
VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER);
set->desc_surface_state = anv_cmd_buffer_alloc_surface_state(cmd_buffer);
anv_fill_buffer_surface_state(cmd_buffer->device,
set->desc_surface_state,
format, ISL_SWIZZLE_IDENTITY,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
set->desc_addr,
layout->descriptor_buffer_size, 1);
}
}
static void
cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
uint32_t stages)
{
static const uint32_t sampler_state_opcodes[] = {
[MESA_SHADER_VERTEX] = 43,
[MESA_SHADER_TESS_CTRL] = 44, /* HS */
[MESA_SHADER_TESS_EVAL] = 45, /* DS */
[MESA_SHADER_GEOMETRY] = 46,
[MESA_SHADER_FRAGMENT] = 47,
};
static const uint32_t binding_table_opcodes[] = {
[MESA_SHADER_VERTEX] = 38,
[MESA_SHADER_TESS_CTRL] = 39,
[MESA_SHADER_TESS_EVAL] = 40,
[MESA_SHADER_GEOMETRY] = 41,
[MESA_SHADER_FRAGMENT] = 42,
};
anv_foreach_stage(s, stages) {
assert(s < ARRAY_SIZE(binding_table_opcodes));
if (cmd_buffer->state.samplers[s].alloc_size > 0) {
anv_batch_emit(&cmd_buffer->batch,
GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
}
}
/* Always emit binding table pointers if we're asked to, since on SKL
* this is what flushes push constants. */
anv_batch_emit(&cmd_buffer->batch,
GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
btp._3DCommandSubOpcode = binding_table_opcodes[s];
#if GFX_VERX10 >= 125
btp.PointertoVSBindingTable = SCRATCH_SURFACE_STATE_POOL_SIZE +
cmd_buffer->state.binding_tables[s].offset;
#else
btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
#endif
}
}
}
static struct anv_address
get_push_range_address(struct anv_cmd_buffer *cmd_buffer,
const struct anv_shader_bin *shader,
const struct anv_push_range *range)
{
struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
switch (range->set) {
case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
/* This is a descriptor set buffer so the set index is
* actually given by binding->binding. (Yes, that's
* confusing.)
*/
struct anv_descriptor_set *set =
gfx_state->base.descriptors[range->index];
return anv_descriptor_set_address(set);
}
case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS: {
if (gfx_state->base.push_constants_state.alloc_size == 0) {
gfx_state->base.push_constants_state =
anv_cmd_buffer_gfx_push_constants(cmd_buffer);
}
return (struct anv_address) {
.bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = gfx_state->base.push_constants_state.offset,
};
}
default: {
assert(range->set < MAX_SETS);
struct anv_descriptor_set *set =
gfx_state->base.descriptors[range->set];
const struct anv_descriptor *desc =
&set->descriptors[range->index];
if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
if (desc->buffer_view)
return desc->buffer_view->address;
} else {
assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
if (desc->buffer) {
const struct anv_push_constants *push =
&gfx_state->base.push_constants;
uint32_t dynamic_offset =
push->dynamic_offsets[range->dynamic_offset_index];
return anv_address_add(desc->buffer->address,
desc->offset + dynamic_offset);
}
}
/* For NULL UBOs, we just return an address in the workaround BO. We do
* writes to it for workarounds but always at the bottom. The higher
* bytes should be all zeros.
*/
assert(range->length * 32 <= 2048);
return (struct anv_address) {
.bo = cmd_buffer->device->workaround_bo,
.offset = 1024,
};
}
}
}
/** Returns the size in bytes of the bound buffer
*
* The range is relative to the start of the buffer, not the start of the
* range. The returned range may be smaller than
*
* (range->start + range->length) * 32;
*/
static uint32_t
get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer,
const struct anv_shader_bin *shader,
const struct anv_push_range *range)
{
assert(shader->stage != MESA_SHADER_COMPUTE);
const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
switch (range->set) {
case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
struct anv_descriptor_set *set =
gfx_state->base.descriptors[range->index];
assert(range->start * 32 < set->desc_mem.alloc_size);
assert((range->start + range->length) * 32 <= set->desc_mem.alloc_size);
return set->desc_mem.alloc_size;
}
case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS:
return (range->start + range->length) * 32;
default: {
assert(range->set < MAX_SETS);
struct anv_descriptor_set *set =
gfx_state->base.descriptors[range->set];
const struct anv_descriptor *desc =
&set->descriptors[range->index];
if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
/* Here we promote a UBO to a binding table entry so that we can avoid a layer of indirection.
* We use the descriptor set's internally allocated surface state to fill the binding table entry.
*/
if (!desc->set_buffer_view)
return 0;
if (range->start * 32 > desc->set_buffer_view->range)
return 0;
return desc->set_buffer_view->range;
} else {
if (!desc->buffer)
return 0;
assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
/* Compute the offset within the buffer */
const struct anv_push_constants *push =
&gfx_state->base.push_constants;
uint32_t dynamic_offset =
push->dynamic_offsets[range->dynamic_offset_index];
uint64_t offset = desc->offset + dynamic_offset;
/* Clamp to the buffer size */
offset = MIN2(offset, desc->buffer->vk.size);
/* Clamp the range to the buffer size */
uint32_t bound_range = MIN2(desc->range, desc->buffer->vk.size - offset);
/* Align the range for consistency */
bound_range = align_u32(bound_range, ANV_UBO_ALIGNMENT);
return bound_range;
}
}
}
}
static void
cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
gl_shader_stage stage,
struct anv_address *buffers,
unsigned buffer_count)
{
const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline;
static const uint32_t push_constant_opcodes[] = {
[MESA_SHADER_VERTEX] = 21,
[MESA_SHADER_TESS_CTRL] = 25, /* HS */
[MESA_SHADER_TESS_EVAL] = 26, /* DS */
[MESA_SHADER_GEOMETRY] = 22,
[MESA_SHADER_FRAGMENT] = 23,
};
assert(stage < ARRAY_SIZE(push_constant_opcodes));
UNUSED uint32_t mocs = anv_mocs(cmd_buffer->device, NULL, 0);
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
c._3DCommandSubOpcode = push_constant_opcodes[stage];
/* Set MOCS.
*
* We only have one MOCS field for the whole packet, not one per
* buffer. We could go out of our way here to walk over all of
* the buffers and see if any of them are used externally and use
* the external MOCS. However, the notion that someone would use
* the same bit of memory for both scanout and a UBO is nuts.
*
* Let's not bother and assume it's all internal.
*/
c.MOCS = mocs;
if (anv_pipeline_has_stage(pipeline, stage)) {
const struct anv_pipeline_bind_map *bind_map =
&pipeline->shaders[stage]->bind_map;
/* The Skylake PRM contains the following restriction:
*
* "The driver must ensure The following case does not occur
* without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
* buffer 3 read length equal to zero committed followed by a
* 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
* zero committed."
*
* To avoid this, we program the buffers in the highest slots.
* This way, slot 0 is only used if slot 3 is also used.
*/
assert(buffer_count <= 4);
const unsigned shift = 4 - buffer_count;
for (unsigned i = 0; i < buffer_count; i++) {
const struct anv_push_range *range = &bind_map->push_ranges[i];
/* At this point we only have non-empty ranges */
assert(range->length > 0);
c.ConstantBody.ReadLength[i + shift] = range->length;
c.ConstantBody.Buffer[i + shift] =
anv_address_add(buffers[i], range->start * 32);
}
}