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fuchsia / third_party / mesa / 2cbf6ace6fb6b7c4b8ce2b886e8f58cd0107ce45 / . / src / broadcom / compiler / nir_to_vir.c
blob: 64c3eb12aec1d041fc1ec4391ee726e2ffb83cd0 [file] [log] [blame]
/*
* Copyright © 2016 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <inttypes.h>
#include "util/format/u_format.h"
#include "util/u_helpers.h"
#include "util/u_math.h"
#include "util/u_memory.h"
#include "util/ralloc.h"
#include "util/hash_table.h"
#include "compiler/nir/nir.h"
#include "compiler/nir/nir_builder.h"
#include "common/v3d_device_info.h"
#include "v3d_compiler.h"
/* We don't do any address packing. */
#define __gen_user_data void
#define __gen_address_type uint32_t
#define __gen_address_offset(reloc) (*reloc)
#define __gen_emit_reloc(cl, reloc)
#include "cle/v3d_packet_v41_pack.h"
#define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
#define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
#define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
#define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
#define V3D_TSY_SET_QUORUM 0
#define V3D_TSY_INC_WAITERS 1
#define V3D_TSY_DEC_WAITERS 2
#define V3D_TSY_INC_QUORUM 3
#define V3D_TSY_DEC_QUORUM 4
#define V3D_TSY_FREE_ALL 5
#define V3D_TSY_RELEASE 6
#define V3D_TSY_ACQUIRE 7
#define V3D_TSY_WAIT 8
#define V3D_TSY_WAIT_INC 9
#define V3D_TSY_WAIT_CHECK 10
#define V3D_TSY_WAIT_INC_CHECK 11
#define V3D_TSY_WAIT_CV 12
#define V3D_TSY_INC_SEMAPHORE 13
#define V3D_TSY_DEC_SEMAPHORE 14
#define V3D_TSY_SET_QUORUM_FREE_ALL 15
enum v3d_tmu_op_type
{
V3D_TMU_OP_TYPE_REGULAR,
V3D_TMU_OP_TYPE_ATOMIC,
V3D_TMU_OP_TYPE_CACHE
};
static enum v3d_tmu_op_type
v3d_tmu_get_type_from_op(uint32_t tmu_op, bool is_write)
{
switch(tmu_op) {
case V3D_TMU_OP_WRITE_ADD_READ_PREFETCH:
case V3D_TMU_OP_WRITE_SUB_READ_CLEAR:
case V3D_TMU_OP_WRITE_XCHG_READ_FLUSH:
case V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH:
case V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR:
return is_write ? V3D_TMU_OP_TYPE_ATOMIC : V3D_TMU_OP_TYPE_CACHE;
case V3D_TMU_OP_WRITE_UMAX:
case V3D_TMU_OP_WRITE_SMIN:
case V3D_TMU_OP_WRITE_SMAX:
assert(is_write);
FALLTHROUGH;
case V3D_TMU_OP_WRITE_AND_READ_INC:
case V3D_TMU_OP_WRITE_OR_READ_DEC:
case V3D_TMU_OP_WRITE_XOR_READ_NOT:
return V3D_TMU_OP_TYPE_ATOMIC;
case V3D_TMU_OP_REGULAR:
return V3D_TMU_OP_TYPE_REGULAR;
default:
unreachable("Unknown tmu_op\n");
}
}
static void
ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
static void
resize_qreg_array(struct v3d_compile *c,
struct qreg **regs,
uint32_t *size,
uint32_t decl_size)
{
if (*size >= decl_size)
return;
uint32_t old_size = *size;
*size = MAX2(*size * 2, decl_size);
*regs = reralloc(c, *regs, struct qreg, *size);
if (!*regs) {
fprintf(stderr, "Malloc failure\n");
abort();
}
for (uint32_t i = old_size; i < *size; i++)
(*regs)[i] = c->undef;
}
static void
resize_interp_array(struct v3d_compile *c,
struct v3d_interp_input **regs,
uint32_t *size,
uint32_t decl_size)
{
if (*size >= decl_size)
return;
uint32_t old_size = *size;
*size = MAX2(*size * 2, decl_size);
*regs = reralloc(c, *regs, struct v3d_interp_input, *size);
if (!*regs) {
fprintf(stderr, "Malloc failure\n");
abort();
}
for (uint32_t i = old_size; i < *size; i++) {
(*regs)[i].vp = c->undef;
(*regs)[i].C = c->undef;
}
}
void
vir_emit_thrsw(struct v3d_compile *c)
{
if (c->threads == 1)
return;
/* Always thread switch after each texture operation for now.
*
* We could do better by batching a bunch of texture fetches up and
* then doing one thread switch and collecting all their results
* afterward.
*/
c->last_thrsw = vir_NOP(c);
c->last_thrsw->qpu.sig.thrsw = true;
c->last_thrsw_at_top_level = !c->in_control_flow;
/* We need to lock the scoreboard before any tlb acess happens. If this
* thread switch comes after we have emitted a tlb load, then it means
* that we can't lock on the last thread switch any more.
*/
if (c->emitted_tlb_load)
c->lock_scoreboard_on_first_thrsw = true;
}
uint32_t
v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
{
if (nir_src_is_const(instr->src[src])) {
int64_t add_val = nir_src_as_int(instr->src[src]);
if (add_val == 1)
return V3D_TMU_OP_WRITE_AND_READ_INC;
else if (add_val == -1)
return V3D_TMU_OP_WRITE_OR_READ_DEC;
}
return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
}
static uint32_t
v3d_general_tmu_op(nir_intrinsic_instr *instr)
{
switch (instr->intrinsic) {
case nir_intrinsic_load_ssbo:
case nir_intrinsic_load_ubo:
case nir_intrinsic_load_uniform:
case nir_intrinsic_load_shared:
case nir_intrinsic_load_scratch:
case nir_intrinsic_load_global_2x32:
case nir_intrinsic_store_ssbo:
case nir_intrinsic_store_shared:
case nir_intrinsic_store_scratch:
case nir_intrinsic_store_global_2x32:
return V3D_TMU_OP_REGULAR;
case nir_intrinsic_ssbo_atomic_add:
return v3d_get_op_for_atomic_add(instr, 2);
case nir_intrinsic_shared_atomic_add:
case nir_intrinsic_global_atomic_add_2x32:
return v3d_get_op_for_atomic_add(instr, 1);
case nir_intrinsic_ssbo_atomic_imin:
case nir_intrinsic_global_atomic_imin_2x32:
case nir_intrinsic_shared_atomic_imin:
return V3D_TMU_OP_WRITE_SMIN;
case nir_intrinsic_ssbo_atomic_umin:
case nir_intrinsic_global_atomic_umin_2x32:
case nir_intrinsic_shared_atomic_umin:
return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
case nir_intrinsic_ssbo_atomic_imax:
case nir_intrinsic_global_atomic_imax_2x32:
case nir_intrinsic_shared_atomic_imax:
return V3D_TMU_OP_WRITE_SMAX;
case nir_intrinsic_ssbo_atomic_umax:
case nir_intrinsic_global_atomic_umax_2x32:
case nir_intrinsic_shared_atomic_umax:
return V3D_TMU_OP_WRITE_UMAX;
case nir_intrinsic_ssbo_atomic_and:
case nir_intrinsic_global_atomic_and_2x32:
case nir_intrinsic_shared_atomic_and:
return V3D_TMU_OP_WRITE_AND_READ_INC;
case nir_intrinsic_ssbo_atomic_or:
case nir_intrinsic_global_atomic_or_2x32:
case nir_intrinsic_shared_atomic_or:
return V3D_TMU_OP_WRITE_OR_READ_DEC;
case nir_intrinsic_ssbo_atomic_xor:
case nir_intrinsic_global_atomic_xor_2x32:
case nir_intrinsic_shared_atomic_xor:
return V3D_TMU_OP_WRITE_XOR_READ_NOT;
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_global_atomic_exchange_2x32:
case nir_intrinsic_shared_atomic_exchange:
return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
case nir_intrinsic_ssbo_atomic_comp_swap:
case nir_intrinsic_global_atomic_comp_swap_2x32:
case nir_intrinsic_shared_atomic_comp_swap:
return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
default:
unreachable("unknown intrinsic op");
}
}
/**
* Checks if pipelining a new TMU operation requiring 'components' LDTMUs
* would overflow the Output TMU fifo.
*
* It is not allowed to overflow the Output fifo, however, we can overflow
* Input and Config fifos. Doing that makes the shader stall, but only for as
* long as it needs to be able to continue so it is better for pipelining to
* let the QPU stall on these if needed than trying to emit TMU flushes in the
* driver.
*/
bool
ntq_tmu_fifo_overflow(struct v3d_compile *c, uint32_t components)
{
if (c->tmu.flush_count >= MAX_TMU_QUEUE_SIZE)
return true;
return components > 0 &&
c->tmu.output_fifo_size + components > 16 / c->threads;
}
/**
* Emits the thread switch and LDTMU/TMUWT for all outstanding TMU operations,
* popping all TMU fifo entries.
*/
void
ntq_flush_tmu(struct v3d_compile *c)
{
if (c->tmu.flush_count == 0)
return;
vir_emit_thrsw(c);
bool emitted_tmuwt = false;
for (int i = 0; i < c->tmu.flush_count; i++) {
if (c->tmu.flush[i].component_mask > 0) {
nir_dest *dest = c->tmu.flush[i].dest;
assert(dest);
for (int j = 0; j < 4; j++) {
if (c->tmu.flush[i].component_mask & (1 << j)) {
ntq_store_dest(c, dest, j,
vir_MOV(c, vir_LDTMU(c)));
}
}
} else if (!emitted_tmuwt) {
vir_TMUWT(c);
emitted_tmuwt = true;
}
}
c->tmu.output_fifo_size = 0;
c->tmu.flush_count = 0;
_mesa_set_clear(c->tmu.outstanding_regs, NULL);
}
/**
* Queues a pending thread switch + LDTMU/TMUWT for a TMU operation. The caller
* is reponsible for ensuring that doing this doesn't overflow the TMU fifos,
* and more specifically, the output fifo, since that can't stall.
*/
void
ntq_add_pending_tmu_flush(struct v3d_compile *c,
nir_dest *dest,
uint32_t component_mask)
{
const uint32_t num_components = util_bitcount(component_mask);
assert(!ntq_tmu_fifo_overflow(c, num_components));
if (num_components > 0) {
c->tmu.output_fifo_size += num_components;
if (!dest->is_ssa)
_mesa_set_add(c->tmu.outstanding_regs, dest->reg.reg);
}
c->tmu.flush[c->tmu.flush_count].dest = dest;
c->tmu.flush[c->tmu.flush_count].component_mask = component_mask;
c->tmu.flush_count++;
c->tmu.total_count++;
if (c->disable_tmu_pipelining)
ntq_flush_tmu(c);
else if (c->tmu.flush_count > 1)
c->pipelined_any_tmu = true;
}
enum emit_mode {
MODE_COUNT = 0,
MODE_EMIT,
MODE_LAST,
};
/**
* For a TMU general store instruction:
*
* In MODE_COUNT mode, records the number of TMU writes required and flushes
* any outstanding TMU operations the instruction depends on, but it doesn't
* emit any actual register writes.
*
* In MODE_EMIT mode, emits the data register writes required by the
* instruction.
*/
static void
emit_tmu_general_store_writes(struct v3d_compile *c,
enum emit_mode mode,
nir_intrinsic_instr *instr,
uint32_t base_const_offset,
uint32_t *writemask,
uint32_t *const_offset,
uint32_t *type_size,
uint32_t *tmu_writes)
{
struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
/* Find the first set of consecutive components that
* are enabled in the writemask and emit the TMUD
* instructions for them.
*/
assert(*writemask != 0);
uint32_t first_component = ffs(*writemask) - 1;
uint32_t last_component = first_component;
while (*writemask & BITFIELD_BIT(last_component + 1))
last_component++;
assert(first_component <= last_component &&
last_component < instr->num_components);
for (int i = first_component; i <= last_component; i++) {
struct qreg data = ntq_get_src(c, instr->src[0], i);
if (mode == MODE_COUNT)
(*tmu_writes)++;
else
vir_MOV_dest(c, tmud, data);
}
if (mode == MODE_EMIT) {
/* Update the offset for the TMU write based on the
* the first component we are writing.
*/
*type_size = nir_src_bit_size(instr->src[0]) / 8;
*const_offset =
base_const_offset + first_component * (*type_size);
/* Clear these components from the writemask */
uint32_t written_mask =
BITFIELD_RANGE(first_component, *tmu_writes);
(*writemask) &= ~written_mask;
}
}
/**
* For a TMU general atomic instruction:
*
* In MODE_COUNT mode, records the number of TMU writes required and flushes
* any outstanding TMU operations the instruction depends on, but it doesn't
* emit any actual register writes.
*
* In MODE_EMIT mode, emits the data register writes required by the
* instruction.
*/
static void
emit_tmu_general_atomic_writes(struct v3d_compile *c,
enum emit_mode mode,
nir_intrinsic_instr *instr,
uint32_t tmu_op,
bool has_index,
uint32_t *tmu_writes)
{
struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
struct qreg data = ntq_get_src(c, instr->src[1 + has_index], 0);
if (mode == MODE_COUNT)
(*tmu_writes)++;
else
vir_MOV_dest(c, tmud, data);
if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
data = ntq_get_src(c, instr->src[2 + has_index], 0);
if (mode == MODE_COUNT)
(*tmu_writes)++;
else
vir_MOV_dest(c, tmud, data);
}
}
/**
* For any TMU general instruction:
*
* In MODE_COUNT mode, records the number of TMU writes required to emit the
* address parameter and flushes any outstanding TMU operations the instruction
* depends on, but it doesn't emit any actual register writes.
*
* In MODE_EMIT mode, emits register writes required to emit the address.
*/
static void
emit_tmu_general_address_write(struct v3d_compile *c,
enum emit_mode mode,
nir_intrinsic_instr *instr,
uint32_t config,
bool dynamic_src,
int offset_src,
struct qreg base_offset,
uint32_t const_offset,
uint32_t *tmu_writes)
{
if (mode == MODE_COUNT) {
(*tmu_writes)++;
if (dynamic_src)
ntq_get_src(c, instr->src[offset_src], 0);
return;
}
if (vir_in_nonuniform_control_flow(c)) {
vir_set_pf(c, vir_MOV_dest(c, vir_nop_reg(), c->execute),
V3D_QPU_PF_PUSHZ);
}
struct qreg tmua;
if (config == ~0)
tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
else
tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
struct qinst *tmu;
if (dynamic_src) {
struct qreg offset = base_offset;
if (const_offset != 0) {
offset = vir_ADD(c, offset,
vir_uniform_ui(c, const_offset));
}
struct qreg data = ntq_get_src(c, instr->src[offset_src], 0);
tmu = vir_ADD_dest(c, tmua, offset, data);
} else {
if (const_offset != 0) {
tmu = vir_ADD_dest(c, tmua, base_offset,
vir_uniform_ui(c, const_offset));
} else {
tmu = vir_MOV_dest(c, tmua, base_offset);
}
}
if (config != ~0) {
tmu->uniform =
vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
}
if (vir_in_nonuniform_control_flow(c))
vir_set_cond(tmu, V3D_QPU_COND_IFA);
}
/**
* Implements indirect uniform loads and SSBO accesses through the TMU general
* memory access interface.
*/
static void
ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
bool is_shared_or_scratch, bool is_global)
{
uint32_t tmu_op = v3d_general_tmu_op(instr);
/* If we were able to replace atomic_add for an inc/dec, then we
* need/can to do things slightly different, like not loading the
* amount to add/sub, as that is implicit.
*/
bool atomic_add_replaced =
((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
instr->intrinsic == nir_intrinsic_shared_atomic_add ||
instr->intrinsic == nir_intrinsic_global_atomic_add_2x32) &&
(tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
instr->intrinsic == nir_intrinsic_store_scratch ||
instr->intrinsic == nir_intrinsic_store_shared ||
instr->intrinsic == nir_intrinsic_store_global_2x32);
bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
instr->intrinsic == nir_intrinsic_load_ubo ||
instr->intrinsic == nir_intrinsic_load_ssbo ||
instr->intrinsic == nir_intrinsic_load_scratch ||
instr->intrinsic == nir_intrinsic_load_shared ||
instr->intrinsic == nir_intrinsic_load_global_2x32);
if (!is_load)
c->tmu_dirty_rcl = true;
if (is_global)
c->has_global_address = true;
bool has_index = !is_shared_or_scratch && !is_global;
int offset_src;
if (instr->intrinsic == nir_intrinsic_load_uniform) {
offset_src = 0;
} else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
instr->intrinsic == nir_intrinsic_load_ubo ||
instr->intrinsic == nir_intrinsic_load_scratch ||
instr->intrinsic == nir_intrinsic_load_shared ||
instr->intrinsic == nir_intrinsic_load_global_2x32 ||
atomic_add_replaced) {
offset_src = 0 + has_index;
} else if (is_store) {
offset_src = 1 + has_index;
} else {
offset_src = 0 + has_index;
}
bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
uint32_t const_offset = 0;
if (!dynamic_src)
const_offset = nir_src_as_uint(instr->src[offset_src]);
struct qreg base_offset;
if (instr->intrinsic == nir_intrinsic_load_uniform) {
const_offset += nir_intrinsic_base(instr);
base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
v3d_unit_data_create(0, const_offset));
const_offset = 0;
} else if (instr->intrinsic == nir_intrinsic_load_ubo) {
uint32_t index = nir_src_as_uint(instr->src[0]);
/* On OpenGL QUNIFORM_UBO_ADDR takes a UBO index
* shifted up by 1 (0 is gallium's constant buffer 0).
*/
if (c->key->environment == V3D_ENVIRONMENT_OPENGL)
index++;
base_offset =
vir_uniform(c, QUNIFORM_UBO_ADDR,
v3d_unit_data_create(index, const_offset));
const_offset = 0;
} else if (is_shared_or_scratch) {
/* Shared and scratch variables have no buffer index, and all
* start from a common base that we set up at the start of
* dispatch.
*/
if (instr->intrinsic == nir_intrinsic_load_scratch ||
instr->intrinsic == nir_intrinsic_store_scratch) {
base_offset = c->spill_base;
} else {
base_offset = c->cs_shared_offset;
const_offset += nir_intrinsic_base(instr);
}
} else if (is_global) {
/* Global load/store intrinsics use gloal addresses, so the
* offset is the target address and we don't need to add it
* to a base offset.
*/
base_offset = vir_uniform_ui(c, 0);
} else {
uint32_t idx = is_store ? 1 : 0;
base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
nir_src_comp_as_uint(instr->src[idx], 0));
}
/* We are ready to emit TMU register writes now, but before we actually
* emit them we need to flush outstanding TMU operations if any of our
* writes reads from the result of an outstanding TMU operation before
* we start the TMU sequence for this operation, since otherwise the
* flush could happen in the middle of the TMU sequence we are about to
* emit, which is illegal. To do this we run this logic twice, the
* first time it will count required register writes and flush pending
* TMU requests if necessary due to a dependency, and the second one
* will emit the actual TMU writes.
*/
const uint32_t dest_components = nir_intrinsic_dest_components(instr);
uint32_t base_const_offset = const_offset;
uint32_t writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
uint32_t tmu_writes = 0;
for (enum emit_mode mode = MODE_COUNT; mode != MODE_LAST; mode++) {
assert(mode == MODE_COUNT || tmu_writes > 0);
uint32_t type_size = 4;
if (is_store) {
emit_tmu_general_store_writes(c, mode, instr,
base_const_offset,
&writemask,
&const_offset,
&type_size,
&tmu_writes);
} else if (!is_load && !atomic_add_replaced) {
emit_tmu_general_atomic_writes(c, mode, instr,
tmu_op, has_index,
&tmu_writes);
} else if (is_load) {
type_size = nir_dest_bit_size(instr->dest) / 8;
}
/* For atomics we use 32bit except for CMPXCHG, that we need
* to use VEC2. For the rest of the cases we use the number of
* tmud writes we did to decide the type. For cache operations
* the type is ignored.
*/
uint32_t config = 0;
if (mode == MODE_EMIT) {
uint32_t num_components;
if (is_load || atomic_add_replaced) {
num_components = instr->num_components;
} else {
assert(tmu_writes > 0);
num_components = tmu_writes - 1;
}
bool is_atomic =
v3d_tmu_get_type_from_op(tmu_op, !is_load) ==
V3D_TMU_OP_TYPE_ATOMIC;
uint32_t perquad =
is_load && !vir_in_nonuniform_control_flow(c)
? GENERAL_TMU_LOOKUP_PER_QUAD
: GENERAL_TMU_LOOKUP_PER_PIXEL;
config = 0xffffff00 | tmu_op << 3 | perquad;
if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
config |= GENERAL_TMU_LOOKUP_TYPE_VEC2;
} else if (is_atomic || num_components == 1) {
switch (type_size) {
case 4:
config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
break;
case 2:
config |= GENERAL_TMU_LOOKUP_TYPE_16BIT_UI;
break;
case 1:
config |= GENERAL_TMU_LOOKUP_TYPE_8BIT_UI;
break;
default:
unreachable("Unsupported bitsize");
}
} else {
assert(type_size == 4);
config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 +
num_components - 2;
}
}
emit_tmu_general_address_write(c, mode, instr, config,
dynamic_src, offset_src,
base_offset, const_offset,
&tmu_writes);
assert(tmu_writes > 0);
if (mode == MODE_COUNT) {
/* Make sure we won't exceed the 16-entry TMU
* fifo if each thread is storing at the same
* time.
*/
while (tmu_writes > 16 / c->threads)
c->threads /= 2;
/* If pipelining this TMU operation would
* overflow TMU fifos, we need to flush.
*/
if (ntq_tmu_fifo_overflow(c, dest_components))
ntq_flush_tmu(c);
} else {
/* Delay emission of the thread switch and
* LDTMU/TMUWT until we really need to do it to
* improve pipelining.
*/
const uint32_t component_mask =
(1 << dest_components) - 1;
ntq_add_pending_tmu_flush(c, &instr->dest,
component_mask);
}
}
/* nir_lower_wrmasks should've ensured that any writemask on a store
* operation only has consecutive bits set, in which case we should've
* processed the full writemask above.
*/
assert(writemask == 0);
}
static struct qreg *
ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
{
struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
def->num_components);
_mesa_hash_table_insert(c->def_ht, def, qregs);
return qregs;
}
static bool
is_ld_signal(const struct v3d_qpu_sig *sig)
{
return (sig->ldunif ||
sig->ldunifa ||
sig->ldunifrf ||
sig->ldunifarf ||
sig->ldtmu ||
sig->ldvary ||
sig->ldvpm ||
sig->ldtlb ||
sig->ldtlbu);
}
static inline bool
is_ldunif_signal(const struct v3d_qpu_sig *sig)
{
return sig->ldunif || sig->ldunifrf;
}
/**
* This function is responsible for getting VIR results into the associated
* storage for a NIR instruction.
*
* If it's a NIR SSA def, then we just set the associated hash table entry to
* the new result.
*
* If it's a NIR reg, then we need to update the existing qreg assigned to the
* NIR destination with the incoming value. To do that without introducing
* new MOVs, we require that the incoming qreg either be a uniform, or be
* SSA-defined by the previous VIR instruction in the block and rewritable by
* this function. That lets us sneak ahead and insert the SF flag beforehand
* (knowing that the previous instruction doesn't depend on flags) and rewrite
* its destination to be the NIR reg's destination
*/
void
ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
struct qreg result)
{
struct qinst *last_inst = NULL;
if (!list_is_empty(&c->cur_block->instructions))
last_inst = (struct qinst *)c->cur_block->instructions.prev;
bool is_reused_uniform =
is_ldunif_signal(&c->defs[result.index]->qpu.sig) &&
last_inst != c->defs[result.index];
assert(result.file == QFILE_TEMP && last_inst &&
(last_inst == c->defs[result.index] || is_reused_uniform));
if (dest->is_ssa) {
assert(chan < dest->ssa.num_components);
struct qreg *qregs;
struct hash_entry *entry =
_mesa_hash_table_search(c->def_ht, &dest->ssa);
if (entry)
qregs = entry->data;
else
qregs = ntq_init_ssa_def(c, &dest->ssa);
qregs[chan] = result;
} else {
nir_register *reg = dest->reg.reg;
assert(dest->reg.base_offset == 0);
assert(reg->num_array_elems == 0);
struct hash_entry *entry =
_mesa_hash_table_search(c->def_ht, reg);
struct qreg *qregs = entry->data;
/* If the previous instruction can't be predicated for
* the store into the nir_register, then emit a MOV
* that can be.
*/
if (is_reused_uniform ||
(vir_in_nonuniform_control_flow(c) &&
is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig))) {
result = vir_MOV(c, result);
last_inst = c->defs[result.index];
}
/* We know they're both temps, so just rewrite index. */
c->defs[last_inst->dst.index] = NULL;
last_inst->dst.index = qregs[chan].index;
/* If we're in control flow, then make this update of the reg
* conditional on the execution mask.
*/
if (vir_in_nonuniform_control_flow(c)) {
last_inst->dst.index = qregs[chan].index;
/* Set the flags to the current exec mask.
*/
c->cursor = vir_before_inst(last_inst);
vir_set_pf(c, vir_MOV_dest(c, vir_nop_reg(), c->execute),
V3D_QPU_PF_PUSHZ);
c->cursor = vir_after_inst(last_inst);
vir_set_cond(last_inst, V3D_QPU_COND_IFA);
}
}
}
/**
* This looks up the qreg associated with a particular ssa/reg used as a source
* in any instruction.
*
* It is expected that the definition for any NIR value read as a source has
* been emitted by a previous instruction, however, in the case of TMU
* operations we may have postponed emission of the thread switch and LDTMUs
* required to read the TMU results until the results are actually used to
* improve pipelining, which then would lead to us not finding them here
* (for SSA defs) or finding them in the list of registers awaiting a TMU flush
* (for registers), meaning that we need to flush outstanding TMU operations
* to read the correct value.
*/
struct qreg
ntq_get_src(struct v3d_compile *c, nir_src src, int i)
{
struct hash_entry *entry;
if (src.is_ssa) {
assert(i < src.ssa->num_components);
entry = _mesa_hash_table_search(c->def_ht, src.ssa);
if (!entry) {
ntq_flush_tmu(c);
entry = _mesa_hash_table_search(c->def_ht, src.ssa);
}
} else {
nir_register *reg = src.reg.reg;
assert(reg->num_array_elems == 0);
assert(src.reg.base_offset == 0);
assert(i < reg->num_components);
if (_mesa_set_search(c->tmu.outstanding_regs, reg))
ntq_flush_tmu(c);
entry = _mesa_hash_table_search(c->def_ht, reg);
}
assert(entry);
struct qreg *qregs = entry->data;
return qregs[i];
}
static struct qreg
ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
unsigned src)
{
assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
unsigned chan = ffs(instr->dest.write_mask) - 1;
struct qreg r = ntq_get_src(c, instr->src[src].src,
instr->src[src].swizzle[chan]);
assert(!instr->src[src].abs);
assert(!instr->src[src].negate);
return r;
};
static struct qreg
ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
{
return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
}
static void
ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
{
unsigned unit = instr->texture_index;
int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
int dest_size = nir_tex_instr_dest_size(instr);
struct qreg lod = c->undef;
if (lod_index != -1)
lod = ntq_get_src(c, instr->src[lod_index].src, 0);
for (int i = 0; i < dest_size; i++) {
assert(i < 3);
enum quniform_contents contents;
if (instr->is_array && i == dest_size - 1)
contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
else
contents = QUNIFORM_TEXTURE_WIDTH + i;
struct qreg size = vir_uniform(c, contents, unit);
switch (instr->sampler_dim) {
case GLSL_SAMPLER_DIM_1D:
case GLSL_SAMPLER_DIM_2D:
case GLSL_SAMPLER_DIM_MS:
case GLSL_SAMPLER_DIM_3D:
case GLSL_SAMPLER_DIM_CUBE:
case GLSL_SAMPLER_DIM_BUF:
/* Don't minify the array size. */
if (!(instr->is_array && i == dest_size - 1)) {
size = ntq_minify(c, size, lod);
}
break;
case GLSL_SAMPLER_DIM_RECT:
/* There's no LOD field for rects */
break;
default:
unreachable("Bad sampler type");
}
ntq_store_dest(c, &instr->dest, i, size);
}
}
static void
ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
{
unsigned unit = instr->texture_index;
/* Since each texture sampling op requires uploading uniforms to
* reference the texture, there's no HW support for texture size and
* you just upload uniforms containing the size.
*/
switch (instr->op) {
case nir_texop_query_levels:
ntq_store_dest(c, &instr->dest, 0,
vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
return;
case nir_texop_texture_samples:
ntq_store_dest(c, &instr->dest, 0,
vir_uniform(c, QUNIFORM_TEXTURE_SAMPLES, unit));
return;
case nir_texop_txs:
ntq_emit_txs(c, instr);
return;
default:
break;
}
if (c->devinfo->ver >= 40)
v3d40_vir_emit_tex(c, instr);
else
v3d33_vir_emit_tex(c, instr);
}
static struct qreg
ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
{
struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
if (is_cos)
input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
struct qreg periods = vir_FROUND(c, input);
struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
return vir_XOR(c, sin_output, vir_SHL(c,
vir_FTOIN(c, periods),
vir_uniform_ui(c, -1)));
}
static struct qreg
ntq_fsign(struct v3d_compile *c, struct qreg src)
{
struct qreg t = vir_get_temp(c);
vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
vir_set_pf(c, vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
vir_set_pf(c, vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
return vir_MOV(c, t);
}
static void
emit_fragcoord_input(struct v3d_compile *c, int attr)
{
c->inputs[attr * 4 + 0] = vir_FXCD(c);
c->inputs[attr * 4 + 1] = vir_FYCD(c);
c->inputs[attr * 4 + 2] = c->payload_z;
c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
}
static struct qreg
emit_smooth_varying(struct v3d_compile *c,
struct qreg vary, struct qreg w, struct qreg r5)
{
return vir_FADD(c, vir_FMUL(c, vary, w), r5);
}
static struct qreg
emit_noperspective_varying(struct v3d_compile *c,
struct qreg vary, struct qreg r5)
{
return vir_FADD(c, vir_MOV(c, vary), r5);
}
static struct qreg
emit_flat_varying(struct v3d_compile *c,
struct qreg vary, struct qreg r5)
{
vir_MOV_dest(c, c->undef, vary);
return vir_MOV(c, r5);
}
static struct qreg
emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
int8_t input_idx, uint8_t swizzle, int array_index)
{
struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
struct qinst *ldvary = NULL;
struct qreg vary;
if (c->devinfo->ver >= 41) {
ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
c->undef, c->undef);
ldvary->qpu.sig.ldvary = true;
vary = vir_emit_def(c, ldvary);
} else {
vir_NOP(c)->qpu.sig.ldvary = true;
vary = r3;
}
/* Store the input value before interpolation so we can implement
* GLSL's interpolateAt functions if the shader uses them.
*/
if (input_idx >= 0) {
assert(var);
c->interp[input_idx].vp = vary;
c->interp[input_idx].C = vir_MOV(c, r5);
c->interp[input_idx].mode = var->data.interpolation;
}
/* For gl_PointCoord input or distance along a line, we'll be called
* with no nir_variable, and we don't count toward VPM size so we
* don't track an input slot.
*/
if (!var) {
assert(input_idx < 0);
return emit_smooth_varying(c, vary, c->payload_w, r5);
}
int i = c->num_inputs++;
c->input_slots[i] =
v3d_slot_from_slot_and_component(var->data.location +
array_index, swizzle);
struct qreg result;
switch (var->data.interpolation) {
case INTERP_MODE_NONE:
case INTERP_MODE_SMOOTH:
if (var->data.centroid) {
BITSET_SET(c->centroid_flags, i);
result = emit_smooth_varying(c, vary,
c->payload_w_centroid, r5);
} else {
result = emit_smooth_varying(c, vary, c->payload_w, r5);
}
break;
case INTERP_MODE_NOPERSPECTIVE:
BITSET_SET(c->noperspective_flags, i);
result = emit_noperspective_varying(c, vary, r5);
break;
case INTERP_MODE_FLAT:
BITSET_SET(c->flat_shade_flags, i);
result = emit_flat_varying(c, vary, r5);
break;
default:
unreachable("Bad interp mode");
}
if (input_idx >= 0)
c->inputs[input_idx] = result;
return result;
}
static void
emit_fragment_input(struct v3d_compile *c, int base_attr, nir_variable *var,
int array_index, unsigned nelem)
{
for (int i = 0; i < nelem ; i++) {
int chan = var->data.location_frac + i;
int input_idx = (base_attr + array_index) * 4 + chan;
emit_fragment_varying(c, var, input_idx, chan, array_index);
}
}
static void
emit_compact_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
int array_index)
{
/* Compact variables are scalar arrays where each set of 4 elements
* consumes a single location.
*/
int loc_offset = array_index / 4;
int chan = var->data.location_frac + array_index % 4;
int input_idx = (attr + loc_offset) * 4 + chan;
emit_fragment_varying(c, var, input_idx, chan, loc_offset);
}
static void
add_output(struct v3d_compile *c,
uint32_t decl_offset,
uint8_t slot,
uint8_t swizzle)
{
uint32_t old_array_size = c->outputs_array_size;
resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
decl_offset + 1);
if (old_array_size != c->outputs_array_size) {
c->output_slots = reralloc(c,
c->output_slots,
struct v3d_varying_slot,
c->outputs_array_size);
}
c->output_slots[decl_offset] =
v3d_slot_from_slot_and_component(slot, swizzle);
}
/**
* If compare_instr is a valid comparison instruction, emits the
* compare_instr's comparison and returns the sel_instr's return value based
* on the compare_instr's result.
*/
static bool
ntq_emit_comparison(struct v3d_compile *c,
nir_alu_instr *compare_instr,
enum v3d_qpu_cond *out_cond)
{
struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
struct qreg src1;
if (nir_op_infos[compare_instr->op].num_inputs > 1)
src1 = ntq_get_alu_src(c, compare_instr, 1);
bool cond_invert = false;
struct qreg nop = vir_nop_reg();
switch (compare_instr->op) {
case nir_op_feq32:
case nir_op_seq:
vir_set_pf(c, vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
break;
case nir_op_ieq32:
vir_set_pf(c, vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
break;
case nir_op_fneu32:
case nir_op_sne:
vir_set_pf(c, vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
cond_invert = true;
break;
case nir_op_ine32:
vir_set_pf(c, vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
cond_invert = true;
break;
case nir_op_fge32:
case nir_op_sge:
vir_set_pf(c, vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
break;
case nir_op_ige32:
vir_set_pf(c, vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
cond_invert = true;
break;
case nir_op_uge32:
vir_set_pf(c, vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
cond_invert = true;
break;
case nir_op_slt:
case nir_op_flt32:
vir_set_pf(c, vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
break;
case nir_op_ilt32:
vir_set_pf(c, vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
break;
case nir_op_ult32:
vir_set_pf(c, vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
break;
case nir_op_i2b32:
vir_set_pf(c, vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
cond_invert = true;
break;
case nir_op_f2b32:
vir_set_pf(c, vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
cond_invert = true;
break;
default:
return false;
}
*out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
return true;
}
/* Finds an ALU instruction that generates our src value that could
* (potentially) be greedily emitted in the consuming instruction.
*/
static struct nir_alu_instr *
ntq_get_alu_parent(nir_src src)
{
if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
return NULL;
nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
if (!instr)
return NULL;
/* If the ALU instr's srcs are non-SSA, then we would have to avoid
* moving emission of the ALU instr down past another write of the
* src.
*/
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
if (!instr->src[i].src.is_ssa)
return NULL;
}
return instr;
}
/* Turns a NIR bool into a condition code to predicate on. */
static enum v3d_qpu_cond
ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
{
struct qreg qsrc = ntq_get_src(c, src, 0);
/* skip if we already have src in the flags */
if (qsrc.file == QFILE_TEMP && c->flags_temp == qsrc.index)
return c->flags_cond;
nir_alu_instr *compare = ntq_get_alu_parent(src);
if (!compare)
goto out;
enum v3d_qpu_cond cond;
if (ntq_emit_comparison(c, compare, &cond))
return cond;
out:
vir_set_pf(c, vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
V3D_QPU_PF_PUSHZ);
return V3D_QPU_COND_IFNA;
}
static struct qreg
ntq_emit_cond_to_bool(struct v3d_compile *c, enum v3d_qpu_cond cond)
{
struct qreg result =
vir_MOV(c, vir_SEL(c, cond,
vir_uniform_ui(c, ~0),
vir_uniform_ui(c, 0)));
c->flags_temp = result.index;
c->flags_cond = cond;
return result;
}
static struct qreg
ntq_emit_cond_to_int(struct v3d_compile *c, enum v3d_qpu_cond cond)
{
struct qreg result =
vir_MOV(c, vir_SEL(c, cond,
vir_uniform_ui(c, 1),
vir_uniform_ui(c, 0)));
c->flags_temp = result.index;
c->flags_cond = cond;
return result;
}
static struct qreg
f2f16_rtz(struct v3d_compile *c, struct qreg f32)
{
/* The GPU doesn't provide a mechanism to modify the f32->f16 rounding
* method and seems to be using RTE by default, so we need to implement
* RTZ rounding in software :-(
*
* The implementation identifies the cases where RTZ applies and
* returns the correct result and for everything else, it just uses
* the default RTE conversion.
*/
static bool _first = true;
if (_first && V3D_DBG(PERF)) {
fprintf(stderr, "Shader uses round-toward-zero f32->f16 "
"conversion which is not supported in hardware.\n");
_first = false;
}
struct qinst *inst;
struct qreg tmp;
struct qreg result = vir_get_temp(c);
struct qreg mantissa32 = vir_AND(c, f32, vir_uniform_ui(c, 0x007fffff));
/* Compute sign bit of result */
struct qreg sign = vir_AND(c, vir_SHR(c, f32, vir_uniform_ui(c, 16)),
vir_uniform_ui(c, 0x8000));
/* Check the cases were RTZ rounding is relevant based on exponent */
struct qreg exp32 = vir_AND(c, vir_SHR(c, f32, vir_uniform_ui(c, 23)),
vir_uniform_ui(c, 0xff));
struct qreg exp16 = vir_ADD(c, exp32, vir_uniform_ui(c, -127 + 15));
/* if (exp16 > 30) */
inst = vir_MIN_dest(c, vir_nop_reg(), exp16, vir_uniform_ui(c, 30));
vir_set_pf(c, inst, V3D_QPU_PF_PUSHC);
inst = vir_OR_dest(c, result, sign, vir_uniform_ui(c, 0x7bff));
vir_set_cond(inst, V3D_QPU_COND_IFA);
/* if (exp16 <= 30) */
inst = vir_OR_dest(c, result,
vir_OR(c, sign,
vir_SHL(c, exp16, vir_uniform_ui(c, 10))),
vir_SHR(c, mantissa32, vir_uniform_ui(c, 13)));
vir_set_cond(inst, V3D_QPU_COND_IFNA);
/* if (exp16 <= 0) */
inst = vir_MIN_dest(c, vir_nop_reg(), exp16, vir_uniform_ui(c, 0));
vir_set_pf(c, inst, V3D_QPU_PF_PUSHC);
tmp = vir_OR(c, mantissa32, vir_uniform_ui(c, 0x800000));
tmp = vir_SHR(c, tmp, vir_SUB(c, vir_uniform_ui(c, 14), exp16));
inst = vir_OR_dest(c, result, sign, tmp);
vir_set_cond(inst, V3D_QPU_COND_IFNA);
/* Cases where RTZ mode is not relevant: use default RTE conversion.
*
* The cases that are not affected by RTZ are:
*
* exp16 < - 10 || exp32 == 0 || exp32 == 0xff
*
* In V3D we can implement this condition as:
*
* !((exp16 >= -10) && !(exp32 == 0) && !(exp32 == 0xff)))
*/
/* exp16 >= -10 */
inst = vir_MIN_dest(c, vir_nop_reg(), exp16, vir_uniform_ui(c, -10));
vir_set_pf(c, inst, V3D_QPU_PF_PUSHC);
/* && !(exp32 == 0) */
inst = vir_MOV_dest(c, vir_nop_reg(), exp32);
vir_set_uf(c, inst, V3D_QPU_UF_ANDNZ);
/* && !(exp32 == 0xff) */
inst = vir_XOR_dest(c, vir_nop_reg(), exp32, vir_uniform_ui(c, 0xff));
vir_set_uf(c, inst, V3D_QPU_UF_ANDNZ);
/* Use regular RTE conversion if condition is False */
inst = vir_FMOV_dest(c, result, f32);
vir_set_pack(inst, V3D_QPU_PACK_L);
vir_set_cond(inst, V3D_QPU_COND_IFNA);
return vir_MOV(c, result);
}
/**
* Takes the result value of a signed integer width conversion from a smaller
* type to a larger type and if needed, it applies sign extension to it.
*/
static struct qreg
sign_extend(struct v3d_compile *c,
struct qreg value,
uint32_t src_bit_size,
uint32_t dst_bit_size)
{
assert(src_bit_size < dst_bit_size);
struct qreg tmp = vir_MOV(c, value);
/* Do we need to sign-extend? */
uint32_t sign_mask = 1 << (src_bit_size - 1);
struct qinst *sign_check =
vir_AND_dest(c, vir_nop_reg(),
tmp, vir_uniform_ui(c, sign_mask));
vir_set_pf(c, sign_check, V3D_QPU_PF_PUSHZ);
/* If so, fill in leading sign bits */
uint32_t extend_bits = ~(((1 << src_bit_size) - 1)) &
((1ull << dst_bit_size) - 1);
struct qinst *extend_inst =
vir_OR_dest(c, tmp, tmp,
vir_uniform_ui(c, extend_bits));
vir_set_cond(extend_inst, V3D_QPU_COND_IFNA);
return tmp;
}
static void
ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
{
/* This should always be lowered to ALU operations for V3D. */
assert(!instr->dest.saturate);
/* Vectors are special in that they have non-scalarized writemasks,
* and just take the first swizzle channel for each argument in order
* into each writemask channel.
*/
if (instr->op == nir_op_vec2 ||
instr->op == nir_op_vec3 ||
instr->op == nir_op_vec4) {
struct qreg srcs[4];
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
srcs[i] = ntq_get_src(c, instr->src[i].src,
instr->src[i].swizzle[0]);
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
ntq_store_dest(c, &instr->dest.dest, i,
vir_MOV(c, srcs[i]));
return;
}
/* General case: We can just grab the one used channel per src. */
struct qreg src[nir_op_infos[instr->op].num_inputs];
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
src[i] = ntq_get_alu_src(c, instr, i);
}
struct qreg result;
switch (instr->op) {
case nir_op_mov:
result = vir_MOV(c, src[0]);
break;
case nir_op_fneg:
result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
break;
case nir_op_ineg:
result = vir_NEG(c, src[0]);
break;
case nir_op_fmul:
result = vir_FMUL(c, src[0], src[1]);
break;
case nir_op_fadd:
result = vir_FADD(c, src[0], src[1]);
break;
case nir_op_fsub:
result = vir_FSUB(c, src[0], src[1]);
break;
case nir_op_fmin:
result = vir_FMIN(c, src[0], src[1]);
break;
case nir_op_fmax:
result = vir_FMAX(c, src[0], src[1]);
break;
case nir_op_f2i32: {
nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
if (src0_alu && src0_alu->op == nir_op_fround_even) {
result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
} else {
result = vir_FTOIZ(c, src[0]);
}
break;
}
case nir_op_f2u32:
result = vir_FTOUZ(c, src[0]);
break;
case nir_op_i2f32:
result = vir_ITOF(c, src[0]);
break;
case nir_op_u2f32:
result = vir_UTOF(c, src[0]);
break;
case nir_op_b2f32:
result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
break;
case nir_op_b2i32:
result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
break;
case nir_op_f2f16:
case nir_op_f2f16_rtne:
assert(nir_src_bit_size(instr->src[0].src) == 32);
result = vir_FMOV(c, src[0]);
vir_set_pack(c->defs[result.index], V3D_QPU_PACK_L);
break;
case nir_op_f2f16_rtz:
assert(nir_src_bit_size(instr->src[0].src) == 32);
result = f2f16_rtz(c, src[0]);
break;
case nir_op_f2f32:
assert(nir_src_bit_size(instr->src[0].src) == 16);
result = vir_FMOV(c, src[0]);
vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
break;
case nir_op_i2i16: {
uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
assert(bit_size == 32 || bit_size == 8);
if (bit_size == 32) {
/* We don't have integer pack/unpack methods for
* converting between 16-bit and 32-bit, so we implement
* the conversion manually by truncating the src.
*/
result = vir_AND(c, src[0], vir_uniform_ui(c, 0xffff));
} else {
struct qreg tmp = vir_AND(c, src[0],
vir_uniform_ui(c, 0xff));
result = vir_MOV(c, sign_extend(c, tmp, bit_size, 16));
}
break;
}
case nir_op_u2u16: {
uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
assert(bit_size == 32 || bit_size == 8);
/* We don't have integer pack/unpack methods for converting
* between 16-bit and 32-bit, so we implement the conversion
* manually by truncating the src. For the 8-bit case, we
* want to make sure we don't copy garbage from any of the
* 24 MSB bits.
*/
if (bit_size == 32)
result = vir_AND(c, src[0], vir_uniform_ui(c, 0xffff));
else
result = vir_AND(c, src[0], vir_uniform_ui(c, 0xff));
break;
}
case nir_op_i2i8:
case nir_op_u2u8:
assert(nir_src_bit_size(instr->src[0].src) == 32 ||
nir_src_bit_size(instr->src[0].src) == 16);
/* We don't have integer pack/unpack methods for converting
* between 8-bit and 32-bit, so we implement the conversion
* manually by truncating the src.
*/
result = vir_AND(c, src[0], vir_uniform_ui(c, 0xff));
break;
case nir_op_u2u32: {
uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
assert(bit_size == 16 || bit_size == 8);
/* we don't have a native 8-bit/16-bit MOV so we copy all 32-bit
* from the src but we make sure to clear any garbage bits that
* may be present in the invalid src bits.
*/
uint32_t mask = (1 << bit_size) - 1;
result = vir_AND(c, src[0], vir_uniform_ui(c, mask));
break;
}
case nir_op_i2i32: {
uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
assert(bit_size == 16 || bit_size == 8);
uint32_t mask = (1 << bit_size) - 1;
struct qreg tmp = vir_AND(c, src[0],
vir_uniform_ui(c, mask));
result = vir_MOV(c, sign_extend(c, tmp, bit_size, 32));
break;
}
case nir_op_iadd:
result = vir_ADD(c, src[0], src[1]);
break;
case nir_op_ushr:
result = vir_SHR(c, src[0], src[1]);
break;
case nir_op_isub:
result = vir_SUB(c, src[0], src[1]);
break;
case nir_op_ishr:
result = vir_ASR(c, src[0], src[1]);
break;
case nir_op_ishl:
result = vir_SHL(c, src[0], src[1]);
break;
case nir_op_imin:
result = vir_MIN(c, src[0], src[1]);
break;
case nir_op_umin:
result = vir_UMIN(c, src[0], src[1]);
break;
case nir_op_imax:
result = vir_MAX(c, src[0], src[1]);
break;
case nir_op_umax:
result = vir_UMAX(c, src[0], src[1]);
break;
case nir_op_iand:
result = vir_AND(c, src[0], src[1]);
break;
case nir_op_ior:
result = vir_OR(c, src[0], src[1]);
break;
case nir_op_ixor:
result = vir_XOR(c, src[0], src[1]);
break;
case nir_op_inot:
result = vir_NOT(c, src[0]);
break;
case nir_op_ufind_msb:
result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
break;
case nir_op_imul:
result = vir_UMUL(c, src[0], src[1]);
break;
case nir_op_seq:
case nir_op_sne:
case nir_op_sge:
case nir_op_slt: {
enum v3d_qpu_cond cond;
ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
assert(ok);
result = vir_MOV(c, vir_SEL(c, cond,
vir_uniform_f(c, 1.0),
vir_uniform_f(c, 0.0)));
c->flags_temp = result.index;
c->flags_cond = cond;
break;
}
case nir_op_i2b32:
case nir_op_f2b32:
case nir_op_feq32:
case nir_op_fneu32:
case nir_op_fge32:
case nir_op_flt32:
case nir_op_ieq32:
case nir_op_ine32:
case nir_op_ige32:
case nir_op_uge32:
case nir_op_ilt32:
case nir_op_ult32: {
enum v3d_qpu_cond cond;
ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
assert(ok);
result = ntq_emit_cond_to_bool(c, cond);
break;
}
case nir_op_b32csel:
result = vir_MOV(c,
vir_SEL(c,
ntq_emit_bool_to_cond(c, instr->src[0].src),
src[1], src[2]));
break;
case nir_op_fcsel:
vir_set_pf(c, vir_MOV_dest(c, vir_nop_reg(), src[0]),
V3D_QPU_PF_PUSHZ);
result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
src[1], src[2]));
break;
case nir_op_frcp:
result = vir_RECIP(c, src[0]);
break;
case nir_op_frsq:
result = vir_RSQRT(c, src[0]);
break;
case nir_op_fexp2:
result = vir_EXP(c, src[0]);
break;
case nir_op_flog2:
result = vir_LOG(c, src[0]);
break;
case nir_op_fceil:
result = vir_FCEIL(c, src[0]);
break;
case nir_op_ffloor:
result = vir_FFLOOR(c, src[0]);
break;
case nir_op_fround_even:
result = vir_FROUND(c, src[0]);
break;
case nir_op_ftrunc:
result = vir_FTRUNC(c, src[0]);
break;
case nir_op_fsin:
result = ntq_fsincos(c, src[0], false);
break;
case nir_op_fcos:
result = ntq_fsincos(c, src[0], true);
break;
case nir_op_fsign:
result = ntq_fsign(c, src[0]);
break;
case nir_op_fabs: {
result = vir_FMOV(c, src[0]);
vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
break;
}
case nir_op_iabs:
result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
break;
case nir_op_fddx:
case nir_op_fddx_coarse:
case nir_op_fddx_fine:
result = vir_FDX(c, src[0]);
break;
case nir_op_fddy:
case nir_op_fddy_coarse:
case nir_op_fddy_fine:
result = vir_FDY(c, src[0]);
break;
case nir_op_uadd_carry:
vir_set_pf(c, vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
V3D_QPU_PF_PUSHC);
result = ntq_emit_cond_to_int(c, V3D_QPU_COND_IFA);
break;
case nir_op_usub_borrow:
vir_set_pf(c, vir_SUB_dest(c, vir_nop_reg(), src[0], src[1]),
V3D_QPU_PF_PUSHC);
result = ntq_emit_cond_to_int(c, V3D_QPU_COND_IFA);
break;
case nir_op_pack_half_2x16_split:
result = vir_VFPACK(c, src[0], src[1]);
break;
case nir_op_unpack_half_2x16_split_x:
result = vir_FMOV(c, src[0]);
vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
break;
case nir_op_unpack_half_2x16_split_y:
result = vir_FMOV(c, src[0]);
vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
break;
case nir_op_fquantize2f16: {
/* F32 -> F16 -> F32 conversion */
struct qreg tmp = vir_FMOV(c, src[0]);
vir_set_pack(c->defs[tmp.index], V3D_QPU_PACK_L);
tmp = vir_FMOV(c, tmp);
vir_set_unpack(c->defs[tmp.index], 0, V3D_QPU_UNPACK_L);
/* Check for denorm */
struct qreg abs_src = vir_FMOV(c, src[0]);
vir_set_unpack(c->defs[abs_src.index], 0, V3D_QPU_UNPACK_ABS);
struct qreg threshold = vir_uniform_f(c, ldexpf(1.0, -14));
vir_set_pf(c, vir_FCMP_dest(c, vir_nop_reg(), abs_src, threshold),
V3D_QPU_PF_PUSHC);
/* Return +/-0 for denorms */
struct qreg zero =
vir_AND(c, src[0], vir_uniform_ui(c, 0x80000000));
result = vir_FMOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, tmp, zero));
break;
}
default:
fprintf(stderr, "unknown NIR ALU inst: ");
nir_print_instr(&instr->instr, stderr);
fprintf(stderr, "\n");
abort();
}
/* We have a scalar result, so the instruction should only have a
* single channel written to.
*/
assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
ntq_store_dest(c, &instr->dest.dest,
ffs(instr->dest.write_mask) - 1, result);
}
/* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
* specifier. They come from a register that's preloaded with 0xffffffff
* (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
* 8 bits are shifted off the bottom and 0xff shifted in from the top.
*/
#define TLB_TYPE_F16_COLOR (3 << 6)
#define TLB_TYPE_I32_COLOR (1 << 6)
#define TLB_TYPE_F32_COLOR (0 << 6)
#define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
#define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
#define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
#define TLB_F16_SWAP_HI_LO (1 << 1)
#define TLB_VEC_SIZE_4_F16 (1 << 0)
#define TLB_VEC_SIZE_2_F16 (0 << 0)
#define TLB_VEC_SIZE_MINUS_1_SHIFT 0
/* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
* flag is set.
*/
#define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
#define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
#define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
#define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
#define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
/* Stencil is a single 32-bit write. */
#define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
static void
vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
{
if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
return;
struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
nir_variable *var = c->output_color_var[rt];
int num_components = glsl_get_vector_elements(var->type);
uint32_t conf = 0xffffff00;
struct qinst *inst;
conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
TLB_SAMPLE_MODE_PER_PIXEL;
conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
if (c->fs_key->swap_color_rb & (1 << rt))
num_components = MAX2(num_components, 3);
assert(num_components != 0);
enum glsl_base_type type = glsl_get_base_type(var->type);
bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
bool is_32b_tlb_format = is_int_format ||
(c->fs_key->f32_color_rb & (1 << rt));
if (is_int_format) {
/* The F32 vs I32 distinction was dropped in 4.2. */
if (c->devinfo->ver < 42)
conf |= TLB_TYPE_I32_COLOR;
else
conf |= TLB_TYPE_F32_COLOR;
conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
} else {
if (c->fs_key->f32_color_rb & (1 << rt)) {
conf |= TLB_TYPE_F32_COLOR;
conf |= ((num_components - 1) <<
TLB_VEC_SIZE_MINUS_1_SHIFT);
} else {
conf |= TLB_TYPE_F16_COLOR;
conf |= TLB_F16_SWAP_HI_LO;
if (num_components >= 3)
conf |= TLB_VEC_SIZE_4_F16;
else
conf |= TLB_VEC_SIZE_2_F16;
}
}
int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
for (int i = 0; i < num_samples; i++) {
struct qreg *color = c->msaa_per_sample_output ?
&c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
&c->outputs[var->data.driver_location * 4];
struct qreg r = color[0];
struct qreg g = color[1];
struct qreg b = color[2];
struct qreg a = color[3];
if (c->fs_key->swap_color_rb & (1 << rt)) {
r = color[2];
b = color[0];
}
if (c->fs_key->sample_alpha_to_one)
a = vir_uniform_f(c, 1.0);
if (is_32b_tlb_format) {
if (i == 0) {
inst = vir_MOV_dest(c, tlbu_reg, r);
inst->uniform =
vir_get_uniform_index(c,
QUNIFORM_CONSTANT,
conf);
} else {
vir_MOV_dest(c, tlb_reg, r);
}
if (num_components >= 2)
vir_MOV_dest(c, tlb_reg, g);
if (num_components >= 3)
vir_MOV_dest(c, tlb_reg, b);
if (num_components >= 4)
vir_MOV_dest(c, tlb_reg, a);
} else {
inst = vir_VFPACK_dest(c, tlb_reg, r, g);
if (conf != ~0 && i == 0) {
inst->dst = tlbu_reg;
inst->uniform =
vir_get_uniform_index(c,
QUNIFORM_CONSTANT,
conf);
}
if (num_components >= 3)
vir_VFPACK_dest(c, tlb_reg, b, a);
}
}
}
static void
emit_frag_end(struct v3d_compile *c)
{
if (c->output_sample_mask_index != -1) {
vir_SETMSF_dest(c, vir_nop_reg(),
vir_AND(c,
vir_MSF(c),
c->outputs[c->output_sample_mask_index]));
}
bool has_any_tlb_color_write = false;
for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
has_any_tlb_color_write = true;
}
if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
struct nir_variable *var = c->output_color_var[0];
struct qreg *color = &c->outputs[var->data.driver_location * 4];
vir_SETMSF_dest(c, vir_nop_reg(),
vir_AND(c,
vir_MSF(c),
vir_FTOC(c, color[3])));
}
struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
/* If the shader has no non-TLB side effects and doesn't write Z
* we can promote it to enabling early_fragment_tests even
* if the user didn't.
*/
if (c->output_position_index == -1 &&
!(c->s->info.num_images || c->s->info.num_ssbos) &&
!c->s->info.fs.uses_discard &&
!c->fs_key->sample_alpha_to_coverage &&
c->output_sample_mask_index == -1 &&
has_any_tlb_color_write) {
c->s->info.fs.early_fragment_tests = true;
}
/* By default, Z buffer writes are implicit using the Z values produced
* from FEP (Z value produced from rasterization). When this is not
* desirable (shader writes Z explicitly, has discards, etc) we need
* to let the hardware know by setting c->writes_z to true, in which
* case we always need to write a Z value from the QPU, even if it is
* just the passthrough Z value produced from FEP.
*
* Also, from the V3D 4.2 spec:
*
* "If a shader performs a Z read the “Fragment shader does Z writes”
* bit in the shader record must be enabled to ensure deterministic
* results"
*
* So if c->reads_z is set we always need to write Z, even if it is
* a passthrough from the Z value produced from FEP.
*/
if (!c->s->info.fs.early_fragment_tests || c->reads_z) {
c->writes_z = true;
uint8_t tlb_specifier = TLB_TYPE_DEPTH;
struct qinst *inst;
if (c->output_position_index != -1) {
/* Shader writes to gl_FragDepth, use that */
inst = vir_MOV_dest(c, tlbu_reg,
c->outputs[c->output_position_index]);
if (c->devinfo->ver >= 42) {
tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
TLB_SAMPLE_MODE_PER_PIXEL);
} else {
tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
}
} else {
/* Shader doesn't write to gl_FragDepth, take Z from
* FEP.
*/
c->writes_z_from_fep = true;
inst = vir_MOV_dest(c, tlbu_reg, vir_nop_reg());
if (c->devinfo->ver >= 42) {
/* The spec says the PER_PIXEL flag is ignored
* for invariant writes, but the simulator
* demands it.
*/
tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
TLB_SAMPLE_MODE_PER_PIXEL);
} else {
tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
}
/* Since (single-threaded) fragment shaders always need
* a TLB write, if we dond't have any we emit a
* passthrouh Z and flag us as potentially discarding,
* so that we can use Z as the required TLB write.
*/
if (!has_any_tlb_color_write)
c->s->info.fs.uses_discard = true;
}
inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
tlb_specifier |
0xffffff00);
inst->is_tlb_z_write = true;
}
/* XXX: Performance improvement: Merge Z write and color writes TLB
* uniform setup
*/
for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
vir_emit_tlb_color_write(c, rt);
}
static inline void
vir_VPM_WRITE_indirect(struct v3d_compile *c,
struct qreg val,
struct qreg vpm_index,
bool uniform_vpm_index)
{
assert(c->devinfo->ver >= 40);
if (uniform_vpm_index)
vir_STVPMV(c, vpm_index, val);
else
vir_STVPMD(c, vpm_index, val);
}
static void
vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
{
if (c->devinfo->ver >= 40) {
vir_VPM_WRITE_indirect(c, val,
vir_uniform_ui(c, vpm_index), true);
} else {
/* XXX: v3d33_vir_vpm_write_setup(c); */
vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
}
}
static void
emit_vert_end(struct v3d_compile *c)
{
/* GFXH-1684: VPM writes need to be complete by the end of the shader.
*/
if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
vir_VPMWT(c);
}
static void
emit_geom_end(struct v3d_compile *c)
{
/* GFXH-1684: VPM writes need to be complete by the end of the shader.
*/
if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
vir_VPMWT(c);
}
static bool
mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components,
nir_intrinsic_instr *low,
nir_intrinsic_instr *high,
void *data)
{
/* TMU general access only supports 32-bit vectors */
if (bit_size > 32)
return false;
if ((bit_size == 8 || bit_size == 16) && num_components > 1)
return false;
if (align_mul % 4 != 0 || align_offset % 4 != 0)
return false;
/* Vector accesses wrap at 16-byte boundaries so we can't vectorize
* if the resulting vector crosses a 16-byte boundary.
*/
assert(util_is_power_of_two_nonzero(align_mul));
align_mul = MIN2(align_mul, 16);
align_offset &= 0xf;
if (16 - align_mul + align_offset + num_components * 4 > 16)
return false;
return true;
}
void
v3d_optimize_nir(struct v3d_compile *c, struct nir_shader *s, bool allow_copies)
{
bool progress;
unsigned lower_flrp =
(s->options->lower_flrp16 ? 16 : 0) |
(s->options->lower_flrp32 ? 32 : 0) |
(s->options->lower_flrp64 ? 64 : 0);
do {
progress = false;
NIR_PASS(progress, s, nir_split_array_vars, nir_var_function_temp);
NIR_PASS(progress, s, nir_shrink_vec_array_vars, nir_var_function_temp);
NIR_PASS(progress, s, nir_opt_deref);
NIR_PASS(progress, s, nir_lower_vars_to_ssa);
if (allow_copies) {
/* Only run this pass if nir_lower_var_copies was not called
* yet. That would lower away any copy_deref instructions and we
* don't want to introduce any more.
*/
NIR_PASS(progress, s, nir_opt_find_array_copies);
}
NIR_PASS(progress, s, nir_opt_copy_prop_vars);
NIR_PASS(progress, s, nir_opt_dead_write_vars);
NIR_PASS(progress, s, nir_opt_combine_stores, nir_var_all);
NIR_PASS(progress, s, nir_remove_dead_variables,
(nir_variable_mode)(nir_var_function_temp |
nir_var_shader_temp |
nir_var_mem_shared),
NULL);
NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
NIR_PASS(progress, s, nir_lower_phis_to_scalar, false);
NIR_PASS(progress, s, nir_copy_prop);
NIR_PASS(progress, s, nir_opt_remove_phis);
NIR_PASS(progress, s, nir_opt_dce);
NIR_PASS(progress, s, nir_opt_dead_cf);
NIR_PASS(progress, s, nir_opt_cse);
NIR_PASS(progress, s, nir_opt_peephole_select, 0, false, false);
NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
NIR_PASS(progress, s, nir_opt_algebraic);
NIR_PASS(progress, s, nir_opt_constant_folding);
NIR_PASS(progress, s, nir_opt_intrinsics);
NIR_PASS(progress, s, nir_opt_idiv_const, 32);
NIR_PASS(progress, s, nir_lower_alu);
if (nir_opt_trivial_continues(s)) {
progress = true;
NIR_PASS(progress, s, nir_copy_prop);
NIR_PASS(progress, s, nir_opt_dce);
}
NIR_PASS(progress, s, nir_opt_conditional_discard);
NIR_PASS(progress, s, nir_opt_remove_phis);
NIR_PASS(progress, s, nir_opt_if, false);
NIR_PASS(progress, s, nir_opt_undef);
if (c && !c->disable_gcm) {
bool local_progress = false;
NIR_PASS(local_progress, s, nir_opt_gcm, false);
c->gcm_progress |= local_progress;
progress |= local_progress;
}
/* Note that vectorization may undo the load/store scalarization
* pass we run for non 32-bit TMU general load/store by
* converting, for example, 2 consecutive 16-bit loads into a
* single 32-bit load. This is fine (and desirable) as long as
* the resulting 32-bit load meets 32-bit alignment requirements,
* which mem_vectorize_callback() should be enforcing.
*/
nir_load_store_vectorize_options vectorize_opts = {
.modes = nir_var_mem_ssbo | nir_var_mem_ubo |
nir_var_mem_push_const | nir_var_mem_shared |
nir_var_mem_global,
.callback = mem_vectorize_callback,
.robust_modes = 0,
};
bool vectorize_progress = false;
/* This requires that we have called
* nir_lower_vars_to_explicit_types / nir_lower_explicit_io
* first, which we may not have done yet if we call here too
* early durign NIR pre-processing. We can detect this because
* in that case we won't have a compile object
*/
if (c) {
NIR_PASS(vectorize_progress, s, nir_opt_load_store_vectorize,
&vectorize_opts);
if (vectorize_progress) {
NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
NIR_PASS(progress, s, nir_lower_pack);
progress = true;
}
}
if (lower_flrp != 0) {
bool lower_flrp_progress = false;
NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
lower_flrp,
false /* always_precise */);
if (lower_flrp_progress) {
NIR_PASS(progress, s, nir_opt_constant_folding);
progress = true;
}
/* Nothing should rematerialize any flrps, so we only
* need to do this lowering once.
*/
lower_flrp = 0;
}
NIR_PASS(progress, s, nir_opt_undef);
NIR_PASS(progress, s, nir_lower_undef_to_zero);
if (c && !c->disable_loop_unrolling &&
s->options->max_unroll_iterations > 0) {
bool local_progress = false;
NIR_PASS(local_progress, s, nir_opt_loop_unroll);
c->unrolled_any_loops |= local_progress;
progress |= local_progress;
}
} while (progress);
nir_move_options sink_opts =
nir_move_const_undef | nir_move_comparisons | nir_move_copies |
nir_move_load_ubo | nir_move_load_ssbo | nir_move_load_uniform;
NIR_PASS(progress, s, nir_opt_sink, sink_opts);
}
static int
driver_location_compare(const nir_variable *a, const nir_variable *b)
{
return a->data.driver_location == b->data.driver_location ?
a->data.location_frac - b->data.location_frac :
a->data.driver_location - b->data.driver_location;
}
static struct qreg
ntq_emit_vpm_read(struct v3d_compile *c,
uint32_t *num_components_queued,
uint32_t *remaining,
uint32_t vpm_index)
{
struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
if (c->devinfo->ver >= 40 ) {
return vir_LDVPMV_IN(c,
vir_uniform_ui(c,
(*num_components_queued)++));
}
if (*num_components_queued != 0) {
(*num_components_queued)--;
return vir_MOV(c, vpm);
}
uint32_t num_components = MIN2(*remaining, 32);
v3d33_vir_vpm_read_setup(c, num_components);
*num_components_queued = num_components - 1;
*remaining -= num_components;
return vir_MOV(c, vpm);
}
static void
ntq_setup_vs_inputs(struct v3d_compile *c)
{
/* Figure out how many components of each vertex attribute the shader
* uses. Each variable should have been split to individual
* components and unused ones DCEed. The vertex fetcher will load
* from the start of the attribute to the number of components we
* declare we need in c->vattr_sizes[].
*
* BGRA vertex attributes are a bit special: since we implement these
* as RGBA swapping R/B components we always need at least 3 components
* if component 0 is read.
*/
nir_foreach_shader_in_variable(var, c->s) {
/* No VS attribute array support. */
assert(MAX2(glsl_get_length(var->type), 1) == 1);
unsigned loc = var->data.driver_location;
int start_component = var->data.location_frac;
int num_components = glsl_get_components(var->type);
c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
start_component + num_components);
/* Handle BGRA inputs */
if (start_component == 0 &&
c->vs_key->va_swap_rb_mask & (1 << var->data.location)) {
c->vattr_sizes[loc] = MAX2(3, c->vattr_sizes[loc]);
}
}
unsigned num_components = 0;
uint32_t vpm_components_queued = 0;
bool uses_iid = BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_INSTANCE_ID) ||
BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_INSTANCE_INDEX);
bool uses_biid = BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_BASE_INSTANCE);
bool uses_vid = BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_VERTEX_ID) ||
BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
num_components += uses_iid;
num_components += uses_biid;
num_components += uses_vid;
for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
num_components += c->vattr_sizes[i];
if (uses_iid) {
c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
&num_components, ~0);
}
if (uses_biid) {
c->biid = ntq_emit_vpm_read(c, &vpm_components_queued,
&num_components, ~0);
}
if (uses_vid) {
c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
&num_components, ~0);
}
/* The actual loads will happen directly in nir_intrinsic_load_input
* on newer versions.
*/
if (c->devinfo->ver >= 40)
return;
for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
(loc + 1) * 4);
for (int i = 0; i < c->vattr_sizes[loc]; i++) {
c->inputs[loc * 4 + i] =
ntq_emit_vpm_read(c,
&vpm_components_queued,
&num_components,
loc * 4 + i);
}
}
if (c->devinfo->ver >= 40) {
assert(vpm_components_queued == num_components);
} else {
assert(vpm_components_queued == 0);
assert(num_components == 0);
}
}
static bool
program_reads_point_coord(struct v3d_compile *c)
{
nir_foreach_shader_in_variable(var, c->s) {
if (util_varying_is_point_coord(var->data.location,
c->fs_key->point_sprite_mask)) {
return true;
}
}
return false;
}
static void
ntq_setup_gs_inputs(struct v3d_compile *c)
{
nir_sort_variables_with_modes(c->s, driver_location_compare,
nir_var_shader_in);
nir_foreach_shader_in_variable(var, c->s) {
/* All GS inputs are arrays with as many entries as vertices
* in the input primitive, but here we only care about the
* per-vertex input type.
*/
assert(glsl_type_is_array(var->type));
const struct glsl_type *type = glsl_get_array_element(var->type);
unsigned var_len = glsl_count_vec4_slots(type, false, false);
unsigned loc = var->data.driver_location;
resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
(loc + var_len) * 4);
if (var->data.compact) {
for (unsigned j = 0; j < var_len; j++) {
unsigned input_idx = c->num_inputs++;
unsigned loc_frac = var->data.location_frac + j;
unsigned loc = var->data.location + loc_frac / 4;
unsigned comp = loc_frac % 4;
c->input_slots[input_idx] =
v3d_slot_from_slot_and_component(loc, comp);
}
continue;
}
for (unsigned j = 0; j < var_len; j++) {
unsigned num_elements =
glsl_type_is_struct(glsl_without_array(type)) ?
4 : glsl_get_vector_elements(type);
for (unsigned k = 0; k < num_elements; k++) {
unsigned chan = var->data.location_frac + k;
unsigned input_idx = c->num_inputs++;
struct v3d_varying_slot slot =
v3d_slot_from_slot_and_component(var->data.location + j, chan);
c->input_slots[input_idx] = slot;
}
}
}
}
static void
ntq_setup_fs_inputs(struct v3d_compile *c)
{
nir_sort_variables_with_modes(c->s, driver_location_compare,
nir_var_shader_in);
nir_foreach_shader_in_variable(var, c->s) {
unsigned var_len = glsl_count_vec4_slots(var->type, false, false);
unsigned loc = var->data.driver_location;
uint32_t inputs_array_size = c->inputs_array_size;
uint32_t inputs_array_required_size = (loc + var_len) * 4;
resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
inputs_array_required_size);
resize_interp_array(c, &c->interp, &inputs_array_size,
inputs_array_required_size);
if (var->data.location == VARYING_SLOT_POS) {
emit_fragcoord_input(c, loc);
} else if (var->data.location == VARYING_SLOT_PRIMITIVE_ID &&
!c->fs_key->has_gs) {
/* If the fragment shader reads gl_PrimitiveID and we
* don't have a geometry shader in the pipeline to write
* it then we program the hardware to inject it as
* an implicit varying. Take it from there.
*/
c->inputs[loc * 4] = c->primitive_id;
} else if (util_varying_is_point_coord(var->data.location,
c->fs_key->point_sprite_mask)) {
c->inputs[loc * 4 + 0] = c->point_x;
c->inputs[loc * 4 + 1] = c->point_y;
} else if (var->data.compact) {
for (int j = 0; j < var_len; j++)
emit_compact_fragment_input(c, loc, var, j);
} else if (glsl_type_is_struct(glsl_without_array(var->type))) {
for (int j = 0; j < var_len; j++) {
emit_fragment_input(c, loc, var, j, 4);
}
} else {
for (int j = 0; j < var_len; j++) {
emit_fragment_input(c, loc, var, j, glsl_get_vector_elements(var->type));
}
}
}
}
static void
ntq_setup_outputs(struct v3d_compile *c)
{
if (c->s->info.stage != MESA_SHADER_FRAGMENT)
return;
nir_foreach_shader_out_variable(var, c->s) {
unsigned array_len = MAX2(glsl_get_length(var->type), 1);
unsigned loc = var->data.driver_location * 4;
assert(array_len == 1);
(void)array_len;
for (int i = 0; i < 4 - var->data.location_frac; i++) {
add_output(c, loc + var->data.location_frac + i,
var->data.location,
var->data.location_frac + i);
}
switch (var->data.location) {
case FRAG_RESULT_COLOR:
c->output_color_var[0] = var;
c->output_color_var[1] = var;
c->output_color_var[2] = var;
c->output_color_var[3] = var;
break;
case FRAG_RESULT_DATA0:
case FRAG_RESULT_DATA1:
case FRAG_RESULT_DATA2:
case FRAG_RESULT_DATA3:
c->output_color_var[var->data.location -
FRAG_RESULT_DATA0] = var;
break;
case FRAG_RESULT_DEPTH:
c->output_position_index = loc;
break;
case FRAG_RESULT_SAMPLE_MASK:
c->output_sample_mask_index = loc;
break;
}
}
}
/**
* Sets up the mapping from nir_register to struct qreg *.
*
* Each nir_register gets a struct qreg per 32-bit component being stored.
*/
static void
ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
{
foreach_list_typed(nir_register, nir_reg, node, list) {
unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
array_len *
nir_reg->num_components);
_mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
for (int i = 0; i < array_len * nir_reg->num_components; i++)
qregs[i] = vir_get_temp(c);
}
}
static void
ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
{
/* XXX perf: Experiment with using immediate loads to avoid having
* these end up in the uniform stream. Watch out for breaking the
* small immediates optimization in the process!
*/
struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
for (int i = 0; i < instr->def.num_components; i++)
qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
_mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
}
static void
ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
unsigned image_index = nir_src_as_uint(instr->src[0]);
bool is_array = nir_intrinsic_image_array(instr);
assert(nir_src_as_uint(instr->src[1]) == 0);
ntq_store_dest(c, &instr->dest, 0,
vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
if (instr->num_components > 1) {
ntq_store_dest(c, &instr->dest, 1,
vir_uniform(c,
instr->num_components == 2 && is_array ?
QUNIFORM_IMAGE_ARRAY_SIZE :
QUNIFORM_IMAGE_HEIGHT,
image_index));
}
if (instr->num_components > 2) {
ntq_store_dest(c, &instr->dest, 2,
vir_uniform(c,
is_array ?
QUNIFORM_IMAGE_ARRAY_SIZE :
QUNIFORM_IMAGE_DEPTH,
image_index));
}
}
static void
vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
int rt = nir_src_as_uint(instr->src[0]);
assert(rt < V3D_MAX_DRAW_BUFFERS);
int sample_index = nir_intrinsic_base(instr) ;
assert(sample_index < V3D_MAX_SAMPLES);
int component = nir_intrinsic_component(instr);
assert(component < 4);
/* We need to emit our TLB reads after we have acquired the scoreboard
* lock, or the GPU will hang. Usually, we do our scoreboard locking on
* the last thread switch to improve parallelism, however, that is only
* guaranteed to happen before the tlb color writes.
*
* To fix that, we make sure we always emit a thread switch before the
* first tlb color read. If that happens to be the last thread switch
* we emit, then everything is fine, but otherwsie, if any code after
* this point needs to emit additional thread switches, then we will
* switch the strategy to locking the scoreboard on the first thread
* switch instead -- see vir_emit_thrsw().
*/
if (!c->emitted_tlb_load) {
if (!c->last_thrsw_at_top_level) {
assert(c->devinfo->ver >= 41);
vir_emit_thrsw(c);
}
c->emitted_tlb_load = true;
}
struct qreg *color_reads_for_sample =
&c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
if (color_reads_for_sample[component].file == QFILE_NULL) {
enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
int num_components =
util_format_get_nr_components(rt_format);
const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
if (swap_rb)
num_components = MAX2(num_components, 3);
nir_variable *var = c->output_color_var[rt];
enum glsl_base_type type = glsl_get_base_type(var->type);
bool is_int_format = type == GLSL_TYPE_INT ||
type == GLSL_TYPE_UINT;
bool is_32b_tlb_format = is_int_format ||
(c->fs_key->f32_color_rb & (1 << rt));
int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
uint32_t conf = 0xffffff00;
conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
TLB_SAMPLE_MODE_PER_PIXEL;
conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
if (is_32b_tlb_format) {
/* The F32 vs I32 distinction was dropped in 4.2. */
conf |= (c->devinfo->ver < 42 && is_int_format) ?
TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
conf |= ((num_components - 1) <<
TLB_VEC_SIZE_MINUS_1_SHIFT);
} else {
conf |= TLB_TYPE_F16_COLOR;
conf |= TLB_F16_SWAP_HI_LO;
if (num_components >= 3)
conf |= TLB_VEC_SIZE_4_F16;
else
conf |= TLB_VEC_SIZE_2_F16;
}
for (int i = 0; i < num_samples; i++) {
struct qreg r, g, b, a;
if (is_32b_tlb_format) {
r = conf != 0xffffffff && i == 0?
vir_TLBU_COLOR_READ(c, conf) :
vir_TLB_COLOR_READ(c);
if (num_components >= 2)
g = vir_TLB_COLOR_READ(c);
if (num_components >= 3)
b = vir_TLB_COLOR_READ(c);
if (num_components >= 4)
a = vir_TLB_COLOR_READ(c);
} else {
struct qreg rg = conf != 0xffffffff && i == 0 ?
vir_TLBU_COLOR_READ(c, conf) :
vir_TLB_COLOR_READ(c);
r = vir_FMOV(c, rg);
vir_set_unpack(c->defs[r.index], 0,
V3D_QPU_UNPACK_L);
g = vir_FMOV(c, rg);
vir_set_unpack(c->defs[g.index], 0,
V3D_QPU_UNPACK_H);
if (num_components > 2) {
struct qreg ba = vir_TLB_COLOR_READ(c);
b = vir_FMOV(c, ba);
vir_set_unpack(c->defs[b.index], 0,
V3D_QPU_UNPACK_L);
a = vir_FMOV(c, ba);
vir_set_unpack(c->defs[a.index], 0,
V3D_QPU_UNPACK_H);
}
}
struct qreg *color_reads =
&c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
color_reads[0] = swap_rb ? b : r;
if (num_components >= 2)
color_reads[1] = g;
if (num_components >= 3)
color_reads[2] = swap_rb ? r : b;
if (num_components >= 4)
color_reads[3] = a;
}
}
assert(color_reads_for_sample[component].file != QFILE_NULL);
ntq_store_dest(c, &instr->dest, 0,
vir_MOV(c, color_reads_for_sample[component]));
}
static bool
ntq_emit_load_unifa(struct v3d_compile *c, nir_intrinsic_instr *instr);
static bool
try_emit_uniform(struct v3d_compile *c,
int offset,
int num_components,
nir_dest *dest,
enum quniform_contents contents)
{
/* Even though ldunif is strictly 32-bit we can still use it
* to load scalar 8-bit/16-bit uniforms so long as their offset
* is 32-bit aligned. In this case, ldunif would still load
* 32-bit into the destination with the 8-bit/16-bit uniform
* data in the LSB and garbage in the MSB, but that is fine
* because we should only be accessing the valid bits of the
* destination.
*
* FIXME: if in the future we improve our register allocator to
* pack 2 16-bit variables in the MSB and LSB of the same
* register then this optimization would not be valid as is,
* since the load clobbers the MSB.
*/
if (offset % 4 != 0)
return false;
/* We need dwords */
offset = offset / 4;
for (int i = 0; i < num_components; i++) {
ntq_store_dest(c, dest, i,
vir_uniform(c, contents, offset + i));
}
return true;
}
static void
ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
/* We scalarize general TMU access for anything that is not 32-bit. */
assert(nir_dest_bit_size(instr->dest) == 32 ||
instr->num_components == 1);
/* Try to emit ldunif if possible, otherwise fallback to general TMU */
if (nir_src_is_const(instr->src[0])) {
int offset = (nir_intrinsic_base(instr) +
nir_src_as_uint(instr->src[0]));
if (try_emit_uniform(c, offset, instr->num_components,
&instr->dest, QUNIFORM_UNIFORM)) {
return;
}
}
if (!ntq_emit_load_unifa(c, instr)) {
ntq_emit_tmu_general(c, instr, false, false);
c->has_general_tmu_load = true;
}
}
static bool
ntq_emit_inline_ubo_load(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
if (c->compiler->max_inline_uniform_buffers <= 0)
return false;
/* On Vulkan we use indices 1..MAX_INLINE_UNIFORM_BUFFERS for inline
* uniform buffers which we want to handle more like push constants
* than regular UBO. OpenGL doesn't implement this feature.
*/
assert(c->key->environment == V3D_ENVIRONMENT_VULKAN);
uint32_t index = nir_src_as_uint(instr->src[0]);
if (index == 0 || index > c->compiler->max_inline_uniform_buffers)
return false;
/* We scalarize general TMU access for anything that is not 32-bit */
assert(nir_dest_bit_size(instr->dest) == 32 ||
instr->num_components == 1);
if (nir_src_is_const(instr->src[1])) {
/* Index 0 is reserved for push constants */
assert(index > 0);
uint32_t inline_index = index - 1;
int offset = nir_src_as_uint(instr->src[1]);
if (try_emit_uniform(c, offset, instr->num_components,
&instr->dest,
QUNIFORM_INLINE_UBO_0 + inline_index)) {
return true;
}
}
/* Fallback to regular UBO load */
return false;
}
static void
ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
/* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset).
*
* Right now the driver sets PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR even
* if we don't support non-uniform offsets because we also set the
* lower_all_io_to_temps option in the NIR compiler. This ensures that
* any indirect indexing on in/out variables is turned into indirect
* indexing on temporary variables instead, that we handle by lowering
* to scratch. If we implement non-uniform offset here we might be able
* to avoid the temp and scratch lowering, which involves copying from
* the input to the temp variable, possibly making code more optimal.
*/
unsigned offset =
nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
/* Emit the LDVPM directly now, rather than at the top
* of the shader like we did for V3D 3.x (which needs
* vpmsetup when not just taking the next offset).
*
* Note that delaying like this may introduce stalls,
* as LDVPMV takes a minimum of 1 instruction but may
* be slower if the VPM unit is busy with another QPU.
*/
int index = 0;
if (BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_INSTANCE_ID)) {
index++;
}
if (BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_BASE_INSTANCE)) {
index++;
}
if (BITSET_TEST(c->s->info.system_values_read,
SYSTEM_VALUE_VERTEX_ID)) {
index++;
}
for (int i = 0; i < offset; i++)
index += c->vattr_sizes[i];
index += nir_intrinsic_component(instr);
for (int i = 0; i < instr->num_components; i++) {
struct qreg vpm_offset = vir_uniform_ui(c, index++);
ntq_store_dest(c, &instr->dest, i,