\input texinfo @c -*- Texinfo -*- @c %**start of header @setfilename make.info @settitle GNU @code{make} @setchapternewpage odd @c %**end of header @c FSF publishers: format makebook.texi instead of using this file directly. @set RCSID $Id$ @set EDITION 0.51 @set VERSION 3.75 Beta @set UPDATED 9 May 1996 @set UPDATE-MONTH May 1996 @comment The ISBN number might need to change on next publication. @set ISBN 1-882114-78-7 @c CHANGE THIS BEFORE PRINTING AGAIN! --roland 9may96 @c finalout @c ISPELL CHECK: done, 10 June 1993 --roland @c Combine the variable and function indices: @syncodeindex vr fn @c Combine the program and concept indices: @syncodeindex pg cp @ifinfo @dircategory The GNU make utility @direntry * GNU make: (make.info). The GNU make utility. @end direntry This file documents the GNU Make utility, which determines automatically which pieces of a large program need to be recompiled, and issues the commands to recompile them. This is Edition @value{EDITION}, last updated @value{UPDATED}, of @cite{The GNU Make Manual}, for @code{make}, Version @value{VERSION}. Copyright (C) 1988, '89, '90, '91, '92, '93, '94, '95, '96, '97 Free Software Foundation, Inc. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. @ignore Permission is granted to process this file through TeX and print the results, provided the printed document carries copying permission notice identical to this one except for the removal of this paragraph (this paragraph not being relevant to the printed manual). @end ignore Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the Free Software Foundation. @end ifinfo @iftex @shorttitlepage GNU Make @end iftex @titlepage @title GNU Make @subtitle A Program for Directing Recompilation @subtitle Edition @value{EDITION}, for @code{make} Version @value{VERSION}. @subtitle @value{UPDATE-MONTH} @author Richard M. Stallman and Roland McGrath @page @vskip 0pt plus 1filll Copyright @copyright{} 1988, '89, '90, '91, '92, '93, '94, '95, '96 Free Software Foundation, Inc. @sp 2 Published by the Free Software Foundation @* 59 Temple Place -- Suite 330, @* Boston, MA 02111-1307 USA @* Printed copies are available for $20 each. @* ISBN @value{ISBN} @* Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the Free Software Foundation. @sp 2 Cover art by Etienne Suvasa. @end titlepage @page @ifinfo @node Top, Overview, , (dir) @top Make The GNU @code{make} utility automatically determines which pieces of a large program need to be recompiled, and issues the commands to recompile them.@refill This is Edition @value{EDITION} of the @cite{GNU Make Manual}, last updated @value{UPDATED} for @code{make} Version @value{VERSION}.@refill This manual describes @code{make} and contains the following chapters:@refill @end ifinfo @menu * Overview:: Overview of @code{make}. * Introduction:: An introduction to @code{make}. * Makefiles:: Makefiles tell @code{make} what to do. * Rules:: Rules describe when a file must be remade. * Commands:: Commands say how to remake a file. * Using Variables:: You can use variables to avoid repetition. * Conditionals:: Use or ignore parts of the makefile based on the values of variables. * Functions:: Many powerful ways to manipulate text. * make Invocation: Running. How to invoke @code{make} on the command line. * Implicit Rules:: Use implicit rules to treat many files alike, based on their file names. * Archives:: How @code{make} can update library archives. * Features:: Features GNU @code{make} has over other @code{make}s. * Missing:: What GNU @code{make} lacks from other @code{make}s. * Makefile Conventions:: Conventions for makefiles in GNU programs. * Quick Reference:: A quick reference for experienced users. * Complex Makefile:: A real example of a straightforward, but nontrivial, makefile. * Concept Index:: Index of Concepts * Name Index:: Index of Functions, Variables, & Directives --- The Detailed Node Listing --- Overview of @code{make} * Preparing:: Preparing and Running Make * Reading:: On Reading this Text * Bugs:: Problems and Bugs An Introduction to Makefiles * Rule Introduction:: What a rule looks like. * Simple Makefile:: A Simple Makefile * How Make Works:: How @code{make} Processes This Makefile * Variables Simplify:: Variables Make Makefiles Simpler * make Deduces:: Letting @code{make} Deduce the Commands * Combine By Dependency:: Another Style of Makefile * Cleanup:: Rules for Cleaning the Directory Writing Makefiles * Makefile Contents:: What makefiles contain. * Makefile Names:: How to name your makefile. * Include:: How one makefile can use another makefile. * MAKEFILES Variable:: The environment can specify extra makefiles. * Remaking Makefiles:: How makefiles get remade. * Overriding Makefiles:: How to override part of one makefile with another makefile. Writing Rules * Rule Example:: An example explained. * Rule Syntax:: General syntax explained. * Wildcards:: Using wildcard characters such as *'. * Directory Search:: Searching other directories for source files. * Phony Targets:: Using a target that is not a real file's name. * Force Targets:: You can use a target without commands or dependencies to mark other targets as phony. * Empty Targets:: When only the date matters and the files are empty. * Special Targets:: Targets with special built-in meanings. * Multiple Targets:: When to make use of several targets in a rule. * Multiple Rules:: How to use several rules with the same target. * Static Pattern:: Static pattern rules apply to multiple targets and can vary the dependencies according to the target name. * Double-Colon:: How to use a special kind of rule to allow several independent rules for one target. * Automatic Dependencies:: How to automatically generate rules giving dependencies from the source files themselves. Using Wildcard Characters in File Names * Wildcard Examples:: Several examples * Wildcard Pitfall:: Problems to avoid. * Wildcard Function:: How to cause wildcard expansion where it does not normally take place. Searching Directories for Dependencies * General Search:: Specifying a search path that applies to every dependency. * Selective Search:: Specifying a search path for a specified class of names. * Search Algorithm:: When and how search paths are applied. * Commands/Search:: How to write shell commands that work together with search paths. * Implicit/Search:: How search paths affect implicit rules. * Libraries/Search:: Directory search for link libraries. Static Pattern Rules * Static Usage:: The syntax of static pattern rules. * Static versus Implicit:: When are they better than implicit rules? Writing the Commands in Rules * Echoing:: How to control when commands are echoed. * Execution:: How commands are executed. * Parallel:: How commands can be executed in parallel. * Errors:: What happens after a command execution error. * Interrupts:: What happens when a command is interrupted. * Recursion:: Invoking @code{make} from makefiles. * Sequences:: Defining canned sequences of commands. * Empty Commands:: Defining useful, do-nothing commands. Recursive Use of @code{make} * MAKE Variable:: The special effects of using @samp{$(MAKE)}. * Variables/Recursion:: How to communicate variables to a sub-@code{make}. * Options/Recursion:: How to communicate options to a sub-@code{make}. * -w Option:: How the @samp{-w} or @samp{--print-directory} option helps debug use of recursive @code{make} commands. How to Use Variables * Reference:: How to use the value of a variable. * Flavors:: Variables come in two flavors. * Advanced:: Advanced features for referencing a variable. * Values:: All the ways variables get their values. * Setting:: How to set a variable in the makefile. * Appending:: How to append more text to the old value of a variable. * Override Directive:: How to set a variable in the makefile even if the user has set it with a command argument. * Defining:: An alternate way to set a variable to a verbatim string. * Environment:: Variable values can come from the environment. * Automatic:: Some special variables have predefined meanings for use with implicit rules. Advanced Features for Reference to Variables * Substitution Refs:: Referencing a variable with substitutions on the value. * Computed Names:: Computing the name of the variable to refer to. Conditional Parts of Makefiles * Conditional Example:: Example of a conditional * Conditional Syntax:: The syntax of conditionals. * Testing Flags:: Conditionals that test flags. Functions for Transforming Text * Syntax of Functions:: How to write a function call. * Text Functions:: General-purpose text manipulation functions. * File Name Functions:: Functions for manipulating file names. * Foreach Function:: Repeat some text with controlled variation. * Origin Function:: Find where a variable got its value. * Shell Function:: Substitute the output of a shell command. How to Run @code{make} * Makefile Arguments:: How to specify which makefile to use. * Goals:: How to use goal arguments to specify which parts of the makefile to use. * Instead of Execution:: How to use mode flags to specify what kind of thing to do with the commands in the makefile other than simply execute them. * Avoiding Compilation:: How to avoid recompiling certain files. * Overriding:: How to override a variable to specify an alternate compiler and other things. * Testing:: How to proceed past some errors, to test compilation. * Options Summary:: Summary of Options Using Implicit Rules * Using Implicit:: How to use an existing implicit rule to get the commands for updating a file. * Catalogue of Rules:: A list of built-in implicit rules. * Implicit Variables:: How to change what predefined rules do. * Chained Rules:: How to use a chain of implicit rules. * Pattern Rules:: How to define new implicit rules. * Last Resort:: How to defining commands for rules which cannot find any. * Suffix Rules:: The old-fashioned style of implicit rule. * Implicit Rule Search:: The precise algorithm for applying implicit rules. Defining and Redefining Pattern Rules * Pattern Intro:: An introduction to pattern rules. * Pattern Examples:: Examples of pattern rules. * Automatic:: How to use automatic variables in the commands of implicit rules. * Pattern Match:: How patterns match. * Match-Anything Rules:: Precautions you should take prior to defining rules that can match any target file whatever. * Canceling Rules:: How to override or cancel built-in rules. Using @code{make} to Update Archive Files * Archive Members:: Archive members as targets. * Archive Update:: The implicit rule for archive member targets. * Archive Pitfalls:: Dangers to watch out for when using archives. * Archive Suffix Rules:: You can write a special kind of suffix rule for updating archives. Implicit Rule for Archive Member Targets * Archive Symbols:: How to update archive symbol directories. @end menu @node Overview, Introduction, Top, Top @comment node-name, next, previous, up @chapter Overview of @code{make} The @code{make} utility automatically determines which pieces of a large program need to be recompiled, and issues commands to recompile them. This manual describes GNU @code{make}, which was implemented by Richard Stallman and Roland McGrath. GNU @code{make} conforms to section 6.2 of @cite{IEEE Standard 1003.2-1992} (POSIX.2). @cindex POSIX @cindex IEEE Standard 1003.2 @cindex standards conformance Our examples show C programs, since they are most common, but you can use @code{make} with any programming language whose compiler can be run with a shell command. Indeed, @code{make} is not limited to programs. You can use it to describe any task where some files must be updated automatically from others whenever the others change. @menu * Preparing:: Preparing and Running Make * Reading:: On Reading this Text * Bugs:: Problems and Bugs @end menu @node Preparing, Reading, , Overview @ifinfo @heading Preparing and Running Make @end ifinfo To prepare to use @code{make}, you must write a file called the @dfn{makefile} that describes the relationships among files in your program and provides commands for updating each file. In a program, typically, the executable file is updated from object files, which are in turn made by compiling source files.@refill Once a suitable makefile exists, each time you change some source files, this simple shell command: @example make @end example @noindent suffices to perform all necessary recompilations. The @code{make} program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the commands recorded in the data base. You can provide command line arguments to @code{make} to control which files should be recompiled, or how. @xref{Running, ,How to Run @code{make}}. @node Reading, Bugs, Preparing, Overview @section How to Read This Manual If you are new to @code{make}, or are looking for a general introduction, read the first few sections of each chapter, skipping the later sections. In each chapter, the first few sections contain introductory or general information and the later sections contain specialized or technical information. @ifinfo The exception is the second chapter, @ref{Introduction, ,An Introduction to Makefiles}, all of which is introductory. @end ifinfo @iftex The exception is @ref{Introduction, ,An Introduction to Makefiles}, all of which is introductory. @end iftex If you are familiar with other @code{make} programs, see @ref{Features, ,Features of GNU @code{make}}, which lists the enhancements GNU @code{make} has, and @ref{Missing, ,Incompatibilities and Missing Features}, which explains the few things GNU @code{make} lacks that others have. For a quick summary, see @ref{Options Summary}, @ref{Quick Reference}, and @ref{Special Targets}. @node Bugs, , Reading, Overview @section Problems and Bugs @cindex reporting bugs @cindex bugs, reporting @cindex problems and bugs, reporting If you have problems with GNU @code{make} or think you've found a bug, please report it to the developers; we cannot promise to do anything but we might well want to fix it. Before reporting a bug, make sure you've actually found a real bug. Carefully reread the documentation and see if it really says you can do what you're trying to do. If it's not clear whether you should be able to do something or not, report that too; it's a bug in the documentation! Before reporting a bug or trying to fix it yourself, try to isolate it to the smallest possible makefile that reproduces the problem. Then send us the makefile and the exact results @code{make} gave you. Also say what you expected to occur; this will help us decide whether the problem was really in the documentation. Once you've got a precise problem, please send electronic mail either through the Internet or via UUCP: @example @group @r{Internet address:} bug-gnu-utils@@prep.ai.mit.edu @r{UUCP path:} mit-eddie!prep.ai.mit.edu!bug-gnu-utils @end group @end example @noindent Please include the version number of @code{make} you are using. You can get this information with the command @samp{make --version}. Be sure also to include the type of machine and operating system you are using. If possible, include the contents of the file @file{config.h} that is generated by the configuration process. @node Introduction, Makefiles, Overview, Top @comment node-name, next, previous, up @chapter An Introduction to Makefiles You need a file called a @dfn{makefile} to tell @code{make} what to do. Most often, the makefile tells @code{make} how to compile and link a program. @cindex makefile In this chapter, we will discuss a simple makefile that describes how to compile and link a text editor which consists of eight C source files and three header files. The makefile can also tell @code{make} how to run miscellaneous commands when explicitly asked (for example, to remove certain files as a clean-up operation). To see a more complex example of a makefile, see @ref{Complex Makefile}. When @code{make} recompiles the editor, each changed C source file must be recompiled. If a header file has changed, each C source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable editor. @cindex recompilation @cindex editor @menu * Rule Introduction:: What a rule looks like. * Simple Makefile:: A Simple Makefile * How Make Works:: How @code{make} Processes This Makefile * Variables Simplify:: Variables Make Makefiles Simpler * make Deduces:: Letting @code{make} Deduce the Commands * Combine By Dependency:: Another Style of Makefile * Cleanup:: Rules for Cleaning the Directory @end menu @node Rule Introduction, Simple Makefile, , Introduction @comment node-name, next, previous, up @section What a Rule Looks Like @cindex rule, introduction to @cindex makefile rule parts @cindex parts of makefile rule A simple makefile consists of rules'' with the following shape: @cindex targets, introduction to @cindex dependencies, introduction to @cindex commands, introduction to @example @group @var{target} @dots{} : @var{dependencies} @dots{} @var{command} @dots{} @dots{} @end group @end example A @dfn{target} is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as @samp{clean} (@pxref{Phony Targets}). A @dfn{dependency} is a file that is used as input to create the target. A target often depends on several files. @cindex tabs in rules A @dfn{command} is an action that @code{make} carries out. A rule may have more than one command, each on its own line. @strong{Please note:} you need to put a tab character at the beginning of every command line! This is an obscurity that catches the unwary. Usually a command is in a rule with dependencies and serves to create a target file if any of the dependencies change. However, the rule that specifies commands for the target need not have dependencies. For example, the rule containing the delete command associated with the target @samp{clean} does not have dependencies. A @dfn{rule}, then, explains how and when to remake certain files which are the targets of the particular rule. @code{make} carries out the commands on the dependencies to create or update the target. A rule can also explain how and when to carry out an action. @xref{Rules, , Writing Rules}. A makefile may contain other text besides rules, but a simple makefile need only contain rules. Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less. @node Simple Makefile, How Make Works, Rule Introduction, Introduction @section A Simple Makefile @cindex simple makefile @cindex makefile, simple Here is a straightforward makefile that describes the way an executable file called @code{edit} depends on eight object files which, in turn, depend on eight C source and three header files. In this example, all the C files include @file{defs.h}, but only those defining editing commands include @file{command.h}, and only low level files that change the editor buffer include @file{buffer.h}. @example @group edit : main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c clean : rm edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o @end group @end example @noindent We split each long line into two lines using backslash-newline; this is like using one long line, but is easier to read. @cindex continuation lines @cindex @code{\} (backslash), for continuation lines @cindex backslash (@code{\}), for continuation lines @cindex quoting newline, in makefile @cindex newline, quoting, in makefile To use this makefile to create the executable file called @file{edit}, type: @example make @end example To use this makefile to delete the executable file and all the object files from the directory, type: @example make clean @end example In the example makefile, the targets include the executable file @samp{edit}, and the object files @samp{main.o} and @samp{kbd.o}. The dependencies are files such as @samp{main.c} and @samp{defs.h}. In fact, each @samp{.o} file is both a target and a dependency. Commands include @w{@samp{cc -c main.c}} and @w{@samp{cc -c kbd.c}}. When a target is a file, it needs to be recompiled or relinked if any of its dependencies change. In addition, any dependencies that are themselves automatically generated should be updated first. In this example, @file{edit} depends on each of the eight object files; the object file @file{main.o} depends on the source file @file{main.c} and on the header file @file{defs.h}. A shell command follows each line that contains a target and dependencies. These shell commands say how to update the target file. A tab character must come at the beginning of every command line to distinguish commands lines from other lines in the makefile. (Bear in mind that @code{make} does not know anything about how the commands work. It is up to you to supply commands that will update the target file properly. All @code{make} does is execute the commands in the rule you have specified when the target file needs to be updated.) @cindex shell command The target @samp{clean} is not a file, but merely the name of an action. Since you normally do not want to carry out the actions in this rule, @samp{clean} is not a dependency of any other rule. Consequently, @code{make} never does anything with it unless you tell it specifically. Note that this rule not only is not a dependency, it also does not have any dependencies, so the only purpose of the rule is to run the specified commands. Targets that do not refer to files but are just actions are called @dfn{phony targets}. @xref{Phony Targets}, for information about this kind of target. @xref{Errors, , Errors in Commands}, to see how to cause @code{make} to ignore errors from @code{rm} or any other command. @cindex @code{clean} target @cindex @code{rm} (shell command) @node How Make Works, Variables Simplify, Simple Makefile, Introduction @comment node-name, next, previous, up @section How @code{make} Processes a Makefile @cindex processing a makefile @cindex makefile, how @code{make} processes By default, @code{make} starts with the first target (not targets whose names start with @samp{.}). This is called the @dfn{default goal}. (@dfn{Goals} are the targets that @code{make} strives ultimately to update. @xref{Goals, , Arguments to Specify the Goals}.) @cindex default goal @cindex goal, default @cindex goal In the simple example of the previous section, the default goal is to update the executable program @file{edit}; therefore, we put that rule first. Thus, when you give the command: @example make @end example @noindent @code{make} reads the makefile in the current directory and begins by processing the first rule. In the example, this rule is for relinking @file{edit}; but before @code{make} can fully process this rule, it must process the rules for the files that @file{edit} depends on, which in this case are the object files. Each of these files is processed according to its own rule. These rules say to update each @samp{.o} file by compiling its source file. The recompilation must be done if the source file, or any of the header files named as dependencies, is more recent than the object file, or if the object file does not exist. The other rules are processed because their targets appear as dependencies of the goal. If some other rule is not depended on by the goal (or anything it depends on, etc.), that rule is not processed, unless you tell @code{make} to do so (with a command such as @w{@code{make clean}}). Before recompiling an object file, @code{make} considers updating its dependencies, the source file and header files. This makefile does not specify anything to be done for them---the @samp{.c} and @samp{.h} files are not the targets of any rules---so @code{make} does nothing for these files. But @code{make} would update automatically generated C programs, such as those made by Bison or Yacc, by their own rules at this time. After recompiling whichever object files need it, @code{make} decides whether to relink @file{edit}. This must be done if the file @file{edit} does not exist, or if any of the object files are newer than it. If an object file was just recompiled, it is now newer than @file{edit}, so @file{edit} is relinked. @cindex relinking Thus, if we change the file @file{insert.c} and run @code{make}, @code{make} will compile that file to update @file{insert.o}, and then link @file{edit}. If we change the file @file{command.h} and run @code{make}, @code{make} will recompile the object files @file{kbd.o}, @file{command.o} and @file{files.o} and then link the file @file{edit}. @node Variables Simplify, make Deduces, How Make Works, Introduction @section Variables Make Makefiles Simpler @cindex variables @cindex simplifying with variables In our example, we had to list all the object files twice in the rule for @file{edit} (repeated here): @example @group edit : main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o @end group @end example @cindex @code{objects} Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. @dfn{Variables} allow a text string to be defined once and substituted in multiple places later (@pxref{Using Variables, ,How to Use Variables}). @cindex @code{OBJECTS} @cindex @code{objs} @cindex @code{OBJS} @cindex @code{obj} @cindex @code{OBJ} It is standard practice for every makefile to have a variable named @code{objects}, @code{OBJECTS}, @code{objs}, @code{OBJS}, @code{obj}, or @code{OBJ} which is a list of all object file names. We would define such a variable @code{objects} with a line like this in the makefile:@refill @example @group objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o @end group @end example @noindent Then, each place we want to put a list of the object file names, we can substitute the variable's value by writing @samp{$(objects)} (@pxref{Using Variables, ,How to Use Variables}). Here is how the complete simple makefile looks when you use a variable for the object files: @example @group objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit :$(objects) cc -o edit $(objects) main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c clean : rm edit$(objects) @end group @end example @node make Deduces, Combine By Dependency, Variables Simplify, Introduction @section Letting @code{make} Deduce the Commands @cindex deducing commands (implicit rules) @cindex implicit rule, introduction to @cindex rule, implicit, introduction to It is not necessary to spell out the commands for compiling the individual C source files, because @code{make} can figure them out: it has an @dfn{implicit rule} for updating a @samp{.o} file from a correspondingly named @samp{.c} file using a @samp{cc -c} command. For example, it will use the command @samp{cc -c main.c -o main.o} to compile @file{main.c} into @file{main.o}. We can therefore omit the commands from the rules for the object files. @xref{Implicit Rules, ,Using Implicit Rules}.@refill When a @samp{.c} file is used automatically in this way, it is also automatically added to the list of dependencies. We can therefore omit the @samp{.c} files from the dependencies, provided we omit the commands. Here is the entire example, with both of these changes, and a variable @code{objects} as suggested above: @example @group objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit$(objects) main.o : defs.h kbd.o : defs.h command.h command.o : defs.h command.h display.o : defs.h buffer.h insert.o : defs.h buffer.h search.o : defs.h buffer.h files.o : defs.h buffer.h command.h utils.o : defs.h .PHONY : clean clean : -rm edit $(objects) @end group @end example @noindent This is how we would write the makefile in actual practice. (The complications associated with @samp{clean} are described elsewhere. See @ref{Phony Targets}, and @ref{Errors, ,Errors in Commands}.) Because implicit rules are so convenient, they are important. You will see them used frequently.@refill @node Combine By Dependency, Cleanup, make Deduces, Introduction @section Another Style of Makefile @cindex combining rules by dependency When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible. In this style of makefile, you group entries by their dependencies instead of by their targets. Here is what one looks like: @example @group objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit :$(objects) cc -o edit $(objects)$(objects) : defs.h kbd.o command.o files.o : command.h display.o insert.o search.o files.o : buffer.h @end group @end example @noindent Here @file{defs.h} is given as a dependency of all the object files; @file{command.h} and @file{buffer.h} are dependencies of the specific object files listed for them. Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place. @node Cleanup, , Combine By Dependency, Introduction @section Rules for Cleaning the Directory @cindex cleaning up @cindex removing, to clean up Compiling a program is not the only thing you might want to write rules for. Makefiles commonly tell how to do a few other things besides compiling a program: for example, how to delete all the object files and executables so that the directory is @samp{clean}. @cindex @code{clean} target Here is how we could write a @code{make} rule for cleaning our example editor: @example @group clean: rm edit $(objects) @end group @end example In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations. We would do this: @example @group .PHONY : clean clean : -rm edit$(objects) @end group @end example @noindent This prevents @code{make} from getting confused by an actual file called @file{clean} and causes it to continue in spite of errors from @code{rm}. (See @ref{Phony Targets}, and @ref{Errors, ,Errors in Commands}.) @noindent A rule such as this should not be placed at the beginning of the makefile, because we do not want it to run by default! Thus, in the example makefile, we want the rule for @code{edit}, which recompiles the editor, to remain the default goal. Since @code{clean} is not a dependency of @code{edit}, this rule will not run at all if we give the command @samp{make} with no arguments. In order to make the rule run, we have to type @samp{make clean}. @xref{Running, ,How to Run @code{make}}. @node Makefiles, Rules, Introduction, Top @chapter Writing Makefiles @cindex makefile, how to write The information that tells @code{make} how to recompile a system comes from reading a data base called the @dfn{makefile}. @menu * Makefile Contents:: What makefiles contain. * Makefile Names:: How to name your makefile. * Include:: How one makefile can use another makefile. * MAKEFILES Variable:: The environment can specify extra makefiles. * Remaking Makefiles:: How makefiles get remade. * Overriding Makefiles:: How to override part of one makefile with another makefile. @end menu @node Makefile Contents, Makefile Names, , Makefiles @section What Makefiles Contain Makefiles contain five kinds of things: @dfn{explicit rules}, @dfn{implicit rules}, @dfn{variable definitions}, @dfn{directives}, and @dfn{comments}. Rules, variables, and directives are described at length in later chapters.@refill @itemize @bullet @cindex rule, explicit, definition of @cindex explicit rule, definition of @item An @dfn{explicit rule} says when and how to remake one or more files, called the rule's targets. It lists the other files that the targets @dfn{depend on}, and may also give commands to use to create or update the targets. @xref{Rules, ,Writing Rules}. @cindex rule, implicit, definition of @cindex implicit rule, definition of @item An @dfn{implicit rule} says when and how to remake a class of files based on their names. It describes how a target may depend on a file with a name similar to the target and gives commands to create or update such a target. @xref{Implicit Rules, ,Using Implicit Rules}. @cindex variable definition @item A @dfn{variable definition} is a line that specifies a text string value for a variable that can be substituted into the text later. The simple makefile example shows a variable definition for @code{objects} as a list of all object files (@pxref{Variables Simplify, , Variables Make Makefiles Simpler}). @cindex directive @item A @dfn{directive} is a command for @code{make} to do something special while reading the makefile. These include: @itemize @bullet @item Reading another makefile (@pxref{Include, ,Including Other Makefiles}). @item Deciding (based on the values of variables) whether to use or ignore a part of the makefile (@pxref{Conditionals, ,Conditional Parts of Makefiles}). @item Defining a variable from a verbatim string containing multiple lines (@pxref{Defining, ,Defining Variables Verbatim}). @end itemize @cindex comments, in makefile @cindex @code{#} (comments), in makefile @item @samp{#} in a line of a makefile starts a @dfn{comment}. It and the rest of the line are ignored, except that a trailing backslash not escaped by another backslash will continue the comment across multiple lines. Comments may appear on any of the lines in the makefile, except within a @code{define} directive, and perhaps within commands (where the shell decides what is a comment). A line containing just a comment (with perhaps spaces before it) is effectively blank, and is ignored.@refill @end itemize @node Makefile Names, Include, Makefile Contents, Makefiles @section What Name to Give Your Makefile @cindex makefile name @cindex name of makefile @cindex default makefile name @cindex file name of makefile @c following paragraph rewritten to avoid overfull hbox By default, when @code{make} looks for the makefile, it tries the following names, in order: @file{GNUmakefile}, @file{makefile} and @file{Makefile}.@refill @findex Makefile @findex GNUmakefile @findex makefile @cindex @code{README} Normally you should call your makefile either @file{makefile} or @file{Makefile}. (We recommend @file{Makefile} because it appears prominently near the beginning of a directory listing, right near other important files such as @file{README}.) The first name checked, @file{GNUmakefile}, is not recommended for most makefiles. You should use this name if you have a makefile that is specific to GNU @code{make}, and will not be understood by other versions of @code{make}. Other @code{make} programs look for @file{makefile} and @file{Makefile}, but not @file{GNUmakefile}. If @code{make} finds none of these names, it does not use any makefile. Then you must specify a goal with a command argument, and @code{make} will attempt to figure out how to remake it using only its built-in implicit rules. @xref{Implicit Rules, ,Using Implicit Rules}. @cindex @code{-f} @cindex @code{--file} @cindex @code{--makefile} If you want to use a nonstandard name for your makefile, you can specify the makefile name with the @samp{-f} or @samp{--file} option. The arguments @w{@samp{-f @var{name}}} or @w{@samp{--file=@var{name}}} tell @code{make} to read the file @var{name} as the makefile. If you use more than one @samp{-f} or @samp{--file} option, you can specify several makefiles. All the makefiles are effectively concatenated in the order specified. The default makefile names @file{GNUmakefile}, @file{makefile} and @file{Makefile} are not checked automatically if you specify @samp{-f} or @samp{--file}.@refill @cindex specifying makefile name @cindex makefile name, how to specify @cindex name of makefile, how to specify @cindex file name of makefile, how to specify @node Include, MAKEFILES Variable, Makefile Names, Makefiles @section Including Other Makefiles @cindex including other makefiles @cindex makefile, including @findex include The @code{include} directive tells @code{make} to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this: @example include @var{filenames}@dots{} @end example @noindent @var{filenames} can contain shell file name patterns. @cindex shell file name pattern (in @code{include}) @cindex shell wildcards (in @code{include}) @cindex wildcard, in @code{include} Extra spaces are allowed and ignored at the beginning of the line, but a tab is not allowed. (If the line begins with a tab, it will be considered a command line.) Whitespace is required between @code{include} and the file names, and between file names; extra whitespace is ignored there and at the end of the directive. A comment starting with @samp{#} is allowed at the end of the line. If the file names contain any variable or function references, they are expanded. @xref{Using Variables, ,How to Use Variables}. For example, if you have three @file{.mk} files, @file{a.mk}, @file{b.mk}, and @file{c.mk}, and @code{$(bar)} expands to @code{bish bash}, then the following expression @example include foo *.mk$(bar) @end example is equivalent to @example include foo a.mk b.mk c.mk bish bash @end example When @code{make} processes an @code{include} directive, it suspends reading of the containing makefile and reads from each listed file in turn. When that is finished, @code{make} resumes reading the makefile in which the directive appears. One occasion for using @code{include} directives is when several programs, handled by individual makefiles in various directories, need to use a common set of variable definitions (@pxref{Setting, ,Setting Variables}) or pattern rules (@pxref{Pattern Rules, ,Defining and Redefining Pattern Rules}). Another such occasion is when you want to generate dependencies from source files automatically; the dependencies can be put in a file that is included by the main makefile. This practice is generally cleaner than that of somehow appending the dependencies to the end of the main makefile as has been traditionally done with other versions of @code{make}. @xref{Automatic Dependencies}. @cindex dependencies, automatic generation @cindex automatic generation of dependencies @cindex generating dependencies automatically @cindex @code{-I} @cindex @code{--include-dir} @cindex included makefiles, default directries @cindex default directries for included makefiles @findex /usr/gnu/include @findex /usr/local/include @findex /usr/include If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched. First, any directories you have specified with the @samp{-I} or @samp{--include-dir} option are searched (@pxref{Options Summary, ,Summary of Options}). Then the following directories (if they exist) are searched, in this order: @file{@var{prefix}/include} (normally @file{/usr/local/include} @footnote{GNU Make compiled for MS-DOS and MS-Windows behaves as if @var{prefix} has been defined to be the root of the DJGPP tree hierarchy.}) @file{/usr/gnu/include}, @file{/usr/local/include}, @file{/usr/include}. If an included makefile cannot be found in any of these directories, a warning message is generated, but it is not an immediately fatal error; processing of the makefile containing the @code{include} continues. Once it has finished reading makefiles, @code{make} will try to remake any that are out of date or don't exist. @xref{Remaking Makefiles, ,How Makefiles Are Remade}. Only after it has tried to find a way to remake a makefile and failed, will @code{make} diagnose the missing makefile as a fatal error. If you want @code{make} to simply ignore a makefile which does not exist and cannot be remade, with no error message, use the @w{@code{-include}} directive instead of @code{include}, like this: @example -include @var{filenames}@dots{} @end example This is acts like @code{include} in every way except that there is no error (not even a warning) if any of the @var{filenames} do not exist. For compatibility with some other @code{make} implementations, @code{sinclude} is another name for @w{@code{-include}}. @node MAKEFILES Variable, Remaking Makefiles, Include, Makefiles @section The Variable @code{MAKEFILES} @cindex makefile, and @code{MAKEFILES} variable @cindex including (@code{MAKEFILES} variable) @vindex MAKEFILES If the environment variable @code{MAKEFILES} is defined, @code{make} considers its value as a list of names (separated by whitespace) of additional makefiles to be read before the others. This works much like the @code{include} directive: various directories are searched for those files (@pxref{Include, ,Including Other Makefiles}). In addition, the default goal is never taken from one of these makefiles and it is not an error if the files listed in @code{MAKEFILES} are not found.@refill @cindex recursion, and @code{MAKEFILES} variable The main use of @code{MAKEFILES} is in communication between recursive invocations of @code{make} (@pxref{Recursion, ,Recursive Use of @code{make}}). It usually is not desirable to set the environment variable before a top-level invocation of @code{make}, because it is usually better not to mess with a makefile from outside. However, if you are running @code{make} without a specific makefile, a makefile in @code{MAKEFILES} can do useful things to help the built-in implicit rules work better, such as defining search paths (@pxref{Directory Search}). Some users are tempted to set @code{MAKEFILES} in the environment automatically on login, and program makefiles to expect this to be done. This is a very bad idea, because such makefiles will fail to work if run by anyone else. It is much better to write explicit @code{include} directives in the makefiles. @xref{Include, , Including Other Makefiles}. @node Remaking Makefiles, Overriding Makefiles, MAKEFILES Variable, Makefiles @section How Makefiles Are Remade @cindex updating makefiles @cindex remaking makefiles @cindex makefile, remaking of Sometimes makefiles can be remade from other files, such as RCS or SCCS files. If a makefile can be remade from other files, you probably want @code{make} to get an up-to-date version of the makefile to read in. To this end, after reading in all makefiles, @code{make} will consider each as a goal target and attempt to update it. If a makefile has a rule which says how to update it (found either in that very makefile or in another one) or if an implicit rule applies to it (@pxref{Implicit Rules, ,Using Implicit Rules}), it will be updated if necessary. After all makefiles have been checked, if any have actually been changed, @code{make} starts with a clean slate and reads all the makefiles over again. (It will also attempt to update each of them over again, but normally this will not change them again, since they are already up to date.)@refill If the makefiles specify a double-colon rule to remake a file with commands but no dependencies, that file will always be remade (@pxref{Double-Colon}). In the case of makefiles, a makefile that has a double-colon rule with commands but no dependencies will be remade every time @code{make} is run, and then again after @code{make} starts over and reads the makefiles in again. This would cause an infinite loop: @code{make} would constantly remake the makefile, and never do anything else. So, to avoid this, @code{make} will @strong{not} attempt to remake makefiles which are specified as double-colon targets but have no dependencies.@refill If you do not specify any makefiles to be read with @samp{-f} or @samp{--file} options, @code{make} will try the default makefile names; @pxref{Makefile Names, ,What Name to Give Your Makefile}. Unlike makefiles explicitly requested with @samp{-f} or @samp{--file} options, @code{make} is not certain that these makefiles should exist. However, if a default makefile does not exist but can be created by running @code{make} rules, you probably want the rules to be run so that the makefile can be used. Therefore, if none of the default makefiles exists, @code{make} will try to make each of them in the same order in which they are searched for (@pxref{Makefile Names, ,What Name to Give Your Makefile}) until it succeeds in making one, or it runs out of names to try. Note that it is not an error if @code{make} cannot find or make any makefile; a makefile is not always necessary.@refill When you use the @samp{-t} or @samp{--touch} option (@pxref{Instead of Execution, ,Instead of Executing the Commands}), you would not want to use an out-of-date makefile to decide which targets to touch. So the @samp{-t} option has no effect on updating makefiles; they are really updated even if @samp{-t} is specified. Likewise, @samp{-q} (or @samp{--question}) and @samp{-n} (or @samp{--just-print}) do not prevent updating of makefiles, because an out-of-date makefile would result in the wrong output for other targets. Thus, @samp{make -f mfile -n foo} will update @file{mfile}, read it in, and then print the commands to update @file{foo} and its dependencies without running them. The commands printed for @file{foo} will be those specified in the updated contents of @file{mfile}. However, on occasion you might actually wish to prevent updating of even the makefiles. You can do this by specifying the makefiles as goals in the command line as well as specifying them as makefiles. When the makefile name is specified explicitly as a goal, the options @samp{-t} and so on do apply to them. Thus, @samp{make -f mfile -n mfile foo} would read the makefile @file{mfile}, print the commands needed to update it without actually running them, and then print the commands needed to update @file{foo} without running them. The commands for @file{foo} will be those specified by the existing contents of @file{mfile}. @node Overriding Makefiles, , Remaking Makefiles, Makefiles @section Overriding Part of Another Makefile @cindex overriding makefiles @cindex makefile, overriding Sometimes it is useful to have a makefile that is mostly just like another makefile. You can often use the @samp{include} directive to include one in the other, and add more targets or variable definitions. However, if the two makefiles give different commands for the same target, @code{make} will not let you just do this. But there is another way. @cindex match-anything rule, used to override In the containing makefile (the one that wants to include the other), you can use a match-anything pattern rule to say that to remake any target that cannot be made from the information in the containing makefile, @code{make} should look in another makefile. @xref{Pattern Rules}, for more information on pattern rules. For example, if you have a makefile called @file{Makefile} that says how to make the target @samp{foo} (and other targets), you can write a makefile called @file{GNUmakefile} that contains: @example foo: frobnicate > foo %: force @@$(MAKE) -f Makefile$@@ force: ; @end example If you say @samp{make foo}, @code{make} will find @file{GNUmakefile}, read it, and see that to make @file{foo}, it needs to run the command @samp{frobnicate > foo}. If you say @samp{make bar}, @code{make} will find no way to make @file{bar} in @file{GNUmakefile}, so it will use the commands from the pattern rule: @samp{make -f Makefile bar}. If @file{Makefile} provides a rule for updating @file{bar}, @code{make} will apply the rule. And likewise for any other target that @file{GNUmakefile} does not say how to make. The way this works is that the pattern rule has a pattern of just @samp{%}, so it matches any target whatever. The rule specifies a dependency @file{force}, to guarantee that the commands will be run even if the target file already exists. We give @file{force} target empty commands to prevent @code{make} from searching for an implicit rule to build it---otherwise it would apply the same match-anything rule to @file{force} itself and create a dependency loop! @node Rules, Commands, Makefiles, Top @chapter Writing Rules @cindex writing rules @cindex rule, how to write @cindex target @cindex dependency A @dfn{rule} appears in the makefile and says when and how to remake certain files, called the rule's @dfn{targets} (most often only one per rule). It lists the other files that are the @dfn{dependencies} of the target, and @dfn{commands} to use to create or update the target. @cindex default goal @cindex goal, default The order of rules is not significant, except for determining the @dfn{default goal}: the target for @code{make} to consider, if you do not otherwise specify one. The default goal is the target of the first rule in the first makefile. If the first rule has multiple targets, only the first target is taken as the default. There are two exceptions: a target starting with a period is not a default unless it contains one or more slashes, @samp{/}, as well; and, a target that defines a pattern rule has no effect on the default goal. (@xref{Pattern Rules, ,Defining and Redefining Pattern Rules}.) Therefore, we usually write the makefile so that the first rule is the one for compiling the entire program or all the programs described by the makefile (often with a target called @samp{all}). @xref{Goals, ,Arguments to Specify the Goals}. @menu * Rule Example:: An example explained. * Rule Syntax:: General syntax explained. * Wildcards:: Using wildcard characters such as *'. * Directory Search:: Searching other directories for source files. * Phony Targets:: Using a target that is not a real file's name. * Force Targets:: You can use a target without commands or dependencies to mark other targets as phony. * Empty Targets:: When only the date matters and the files are empty. * Special Targets:: Targets with special built-in meanings. * Multiple Targets:: When to make use of several targets in a rule. * Multiple Rules:: How to use several rules with the same target. * Static Pattern:: Static pattern rules apply to multiple targets and can vary the dependencies according to the target name. * Double-Colon:: How to use a special kind of rule to allow several independent rules for one target. * Automatic Dependencies:: How to automatically generate rules giving dependencies from the source files themselves. @end menu @ifinfo @node Rule Example, Rule Syntax, , Rules @section Rule Example Here is an example of a rule: @example foo.o : foo.c defs.h # module for twiddling the frobs cc -c -g foo.c @end example Its target is @file{foo.o} and its dependencies are @file{foo.c} and @file{defs.h}. It has one command, which is @samp{cc -c -g foo.c}. The command line starts with a tab to identify it as a command. This rule says two things: @itemize @bullet @item How to decide whether @file{foo.o} is out of date: it is out of date if it does not exist, or if either @file{foo.c} or @file{defs.h} is more recent than it. @item How to update the file @file{foo.o}: by running @code{cc} as stated. The command does not explicitly mention @file{defs.h}, but we presume that @file{foo.c} includes it, and that that is why @file{defs.h} was added to the dependencies. @end itemize @end ifinfo @node Rule Syntax, Wildcards, Rule Example, Rules @section Rule Syntax @cindex rule syntax @cindex syntax of rules In general, a rule looks like this: @example @var{targets} : @var{dependencies} @var{command} @dots{} @end example @noindent or like this: @example @var{targets} : @var{dependencies} ; @var{command} @var{command} @dots{} @end example @cindex targets @cindex rule targets The @var{targets} are file names, separated by spaces. Wildcard characters may be used (@pxref{Wildcards, ,Using Wildcard Characters in File Names}) and a name of the form @file{@var{a}(@var{m})} represents member @var{m} in archive file @var{a} (@pxref{Archive Members, ,Archive Members as Targets}). Usually there is only one target per rule, but occasionally there is a reason to have more (@pxref{Multiple Targets, , Multiple Targets in a Rule}).@refill @cindex commands @cindex tab character (in commands) The @var{command} lines start with a tab character. The first command may appear on the line after the dependencies, with a tab character, or may appear on the same line, with a semicolon. Either way, the effect is the same. @xref{Commands, ,Writing the Commands in Rules}. @cindex dollar sign (@code{$}), in rules @cindex @code{$}, in rules @cindex rule, and @code{$} Because dollar signs are used to start variable references, if you really want a dollar sign in a rule you must write two of them, @samp{$$} (@pxref{Using Variables, ,How to Use Variables}). You may split a long line by inserting a backslash followed by a newline, but this is not required, as @code{make} places no limit on the length of a line in a makefile. A rule tells @code{make} two things: when the targets are out of date, and how to update them when necessary. @cindex dependencies @cindex rule dependencies The criterion for being out of date is specified in terms of the @var{dependencies}, which consist of file names separated by spaces. (Wildcards and archive members (@pxref{Archives}) are allowed here too.) A target is out of date if it does not exist or if it is older than any of the dependencies (by comparison of last-modification times). The idea is that the contents of the target file are computed based on information in the dependencies, so if any of the dependencies changes, the contents of the existing target file are no longer necessarily valid. How to update is specified by @var{commands}. These are lines to be executed by the shell (normally @samp{sh}), but with some extra features (@pxref{Commands, ,Writing the Commands in Rules}). @node Wildcards, Directory Search, Rule Syntax, Rules @section Using Wildcard Characters in File Names @cindex wildcard @cindex file name with wildcards @cindex globbing (wildcards) @cindex @code{*} (wildcard character) @cindex @code{?} (wildcard character) @cindex @code{[@dots{}]} (wildcard characters) A single file name can specify many files using @dfn{wildcard characters}. The wildcard characters in @code{make} are @samp{*}, @samp{?} and @samp{[@dots{}]}, the same as in the Bourne shell. For example, @file{*.c} specifies a list of all the files (in the working directory) whose names end in @samp{.c}.@refill @cindex @code{~} (tilde) @cindex tilde (@code{~}) @cindex home directory The character @samp{~} at the beginning of a file name also has special significance. If alone, or followed by a slash, it represents your home directory. For example @file{~/bin} expands to @file{/home/you/bin}. If the @samp{~} is followed by a word, the string represents the home directory of the user named by that word. For example @file{~john/bin} expands to @file{/home/john/bin}. On systems which don't have a home directory for each user (such as MS-DOS or MS-Windows), this functionality can be simulated by setting the environment variable @var{HOME}.@refill Wildcard expansion happens automatically in targets, in dependencies, and in commands (where the shell does the expansion). In other contexts, wildcard expansion happens only if you request it explicitly with the @code{wildcard} function. The special significance of a wildcard character can be turned off by preceding it with a backslash. Thus, @file{foo\*bar} would refer to a specific file whose name consists of @samp{foo}, an asterisk, and @samp{bar}.@refill @menu * Wildcard Examples:: Several examples * Wildcard Pitfall:: Problems to avoid. * Wildcard Function:: How to cause wildcard expansion where it does not normally take place. @end menu @node Wildcard Examples, Wildcard Pitfall, , Wildcards @subsection Wildcard Examples Wildcards can be used in the commands of a rule, where they are expanded by the shell. For example, here is a rule to delete all the object files: @example @group clean: rm -f *.o @end group @end example @cindex @code{rm} (shell command) Wildcards are also useful in the dependencies of a rule. With the following rule in the makefile, @samp{make print} will print all the @samp{.c} files that have changed since the last time you printed them: @example print: *.c lpr -p$? touch print @end example @cindex @code{print} target @cindex @code{lpr} (shell command) @cindex @code{touch} (shell command) @noindent This rule uses @file{print} as an empty target file; see @ref{Empty Targets, ,Empty Target Files to Record Events}. (The automatic variable @samp{$?} is used to print only those files that have changed; see @ref{Automatic, ,Automatic Variables}.)@refill Wildcard expansion does not happen when you define a variable. Thus, if you write this: @example objects = *.o @end example @noindent then the value of the variable @code{objects} is the actual string @samp{*.o}. However, if you use the value of @code{objects} in a target, dependency or command, wildcard expansion will take place at that time. To set @code{objects} to the expansion, instead use: @example objects :=$(wildcard *.o) @end example @noindent @xref{Wildcard Function}. @node Wildcard Pitfall, Wildcard Function, Wildcard Examples, Wildcards @subsection Pitfalls of Using Wildcards @cindex wildcard pitfalls @cindex pitfalls of wildcards @cindex mistakes with wildcards @cindex errors with wildcards @cindex problems with wildcards Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend. Suppose you would like to say that the executable file @file{foo} is made from all the object files in the directory, and you write this: @example objects = *.o foo : $(objects) cc -o foo$(CFLAGS) $(objects) @end example @noindent The value of @code{objects} is the actual string @samp{*.o}. Wildcard expansion happens in the rule for @file{foo}, so that each @emph{existing} @samp{.o} file becomes a dependency of @file{foo} and will be recompiled if necessary. But what if you delete all the @samp{.o} files? When a wildcard matches no files, it is left as it is, so then @file{foo} will depend on the oddly-named file @file{*.o}. Since no such file is likely to exist, @code{make} will give you an error saying it cannot figure out how to make @file{*.o}. This is not what you want! Actually it is possible to obtain the desired result with wildcard expansion, but you need more sophisticated techniques, including the @code{wildcard} function and string substitution. @ifinfo @xref{Wildcard Function, ,The Function @code{wildcard}}. @end ifinfo @iftex These are described in the following section. @end iftex @cindex wildcards and MS-DOS/MS-Windows backslashes @cindex backslashes in pathnames and wildcard expansion Microsoft operating systems (MS-DOS and MS-Windows) use backslashes to separate directories in pathnames, like so: @example c:\foo\bar\baz.c @end example This is equivalent to the Unix-style @file{c:/foo/bar/baz.c} (the @file{c:} part is the so-called drive letter). When @code{make} runs on these systems, it supports backslashes as well as the Unix-style forward slashes in pathnames. However, this support does @emph{not} include the wildcard expansion, where backslash is a quote character. Therefore, you @emph{must} use Unix-style slashes in these cases. @node Wildcard Function, , Wildcard Pitfall, Wildcards @subsection The Function @code{wildcard} @findex wildcard Wildcard expansion happens automatically in rules. But wildcard expansion does not normally take place when a variable is set, or inside the arguments of a function. If you want to do wildcard expansion in such places, you need to use the @code{wildcard} function, like this: @example$(wildcard @var{pattern}@dots{}) @end example @noindent This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns. If no existing file name matches a pattern, then that pattern is omitted from the output of the @code{wildcard} function. Note that this is different from how unmatched wildcards behave in rules, where they are used verbatim rather than ignored (@pxref{Wildcard Pitfall}). One use of the @code{wildcard} function is to get a list of all the C source files in a directory, like this: @example $(wildcard *.c) @end example We can change the list of C source files into a list of object files by replacing the @samp{.c} suffix with @samp{.o} in the result, like this: @example$(patsubst %.c,%.o,$(wildcard *.c)) @end example @noindent (Here we have used another function, @code{patsubst}. @xref{Text Functions, ,Functions for String Substitution and Analysis}.)@refill Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows: @example objects :=$(patsubst %.c,%.o,$(wildcard *.c)) foo :$(objects) cc -o foo $(objects) @end example @noindent (This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files. @xref{Flavors, ,The Two Flavors of Variables}, for an explanation of @samp{:=}, which is a variant of @samp{=}.) @node Directory Search, Phony Targets, Wildcards, Rules @section Searching Directories for Dependencies @vindex VPATH @findex vpath @cindex vpath @cindex search path for dependencies (@code{VPATH}) @cindex directory search (@code{VPATH}) For large systems, it is often desirable to put sources in a separate directory from the binaries. The @dfn{directory search} features of @code{make} facilitate this by searching several directories automatically to find a dependency. When you redistribute the files among directories, you do not need to change the individual rules, just the search paths. @menu * General Search:: Specifying a search path that applies to every dependency. * Selective Search:: Specifying a search path for a specified class of names. * Search Algorithm:: When and how search paths are applied. * Commands/Search:: How to write shell commands that work together with search paths. * Implicit/Search:: How search paths affect implicit rules. * Libraries/Search:: Directory search for link libraries. @end menu @node General Search, Selective Search, , Directory Search @subsection @code{VPATH}: Search Path for All Dependencies @vindex VPATH The value of the @code{make} variable @code{VPATH} specifies a list of directories that @code{make} should search. Most often, the directories are expected to contain dependency files that are not in the current directory; however, @code{VPATH} specifies a search list that @code{make} applies for all files, including files which are targets of rules. Thus, if a file that is listed as a target or dependency does not exist in the current directory, @code{make} searches the directories listed in @code{VPATH} for a file with that name. If a file is found in one of them, that file may become the dependency (see below). Rules may then specify the names of files in the dependency list as if they all existed in the current directory. @xref{Commands/Search, ,Writing Shell Commands with Directory Search}. In the @code{VPATH} variable, directory names are separated by colons or blanks. The order in which directories are listed is the order followed by @code{make} in its search. (On MS-DOS and MS-Windows, semi-colons are used as separators of directory names in @code{VPATH}, since the colon can be used in the pathname itself, after the drive letter.) For example, @example VPATH = src:../headers @end example @noindent specifies a path containing two directories, @file{src} and @file{../headers}, which @code{make} searches in that order. With this value of @code{VPATH}, the following rule, @example foo.o : foo.c @end example @noindent is interpreted as if it were written like this: @example foo.o : src/foo.c @end example @noindent assuming the file @file{foo.c} does not exist in the current directory but is found in the directory @file{src}. @node Selective Search, Search Algorithm, General Search, Directory Search @subsection The @code{vpath} Directive @findex vpath Similar to the @code{VPATH} variable, but more selective, is the @code{vpath} directive (note lower case), which allows you to specify a search path for a particular class of file names: those that match a particular pattern. Thus you can supply certain search directories for one class of file names and other directories (or none) for other file names. There are three forms of the @code{vpath} directive: @table @code @item vpath @var{pattern} @var{directories} Specify the search path @var{directories} for file names that match @var{pattern}. The search path, @var{directories}, is a list of directories to be searched, separated by colons (semi-colons on MS-DOS and MS-Windows) or blanks, just like the search path used in the @code{VPATH} variable. @item vpath @var{pattern} Clear out the search path associated with @var{pattern}. @c Extra blank line makes sure this gets two lines. @item vpath Clear all search paths previously specified with @code{vpath} directives. @end table A @code{vpath} pattern is a string containing a @samp{%} character. The string must match the file name of a dependency that is being searched for, the @samp{%} character matching any sequence of zero or more characters (as in pattern rules; @pxref{Pattern Rules, ,Defining and Redefining Pattern Rules}). For example, @code{%.h} matches files that end in @code{.h}. (If there is no @samp{%}, the pattern must match the dependency exactly, which is not useful very often.) @cindex @code{%}, quoting in @code{vpath} @cindex @code{%}, quoting with @code{\} (backslash) @cindex @code{\} (backslash), to quote @code{%} @cindex backslash (@code{\}), to quote @code{%} @cindex quoting @code{%}, in @code{vpath} @samp{%} characters in a @code{vpath} directive's pattern can be quoted with preceding backslashes (@samp{\}). Backslashes that would otherwise quote @samp{%} characters can be quoted with more backslashes. Backslashes that quote @samp{%} characters or other backslashes are removed from the pattern before it is compared to file names. Backslashes that are not in danger of quoting @samp{%} characters go unmolested.@refill When a dependency fails to exist in the current directory, if the @var{pattern} in a @code{vpath} directive matches the name of the dependency file, then the @var{directories} in that directive are searched just like (and before) the directories in the @code{VPATH} variable. For example, @example vpath %.h ../headers @end example @noindent tells @code{make} to look for any dependency whose name ends in @file{.h} in the directory @file{../headers} if the file is not found in the current directory. If several @code{vpath} patterns match the dependency file's name, then @code{make} processes each matching @code{vpath} directive one by one, searching all the directories mentioned in each directive. @code{make} handles multiple @code{vpath} directives in the order in which they appear in the makefile; multiple directives with the same pattern are independent of each other. @need 750 Thus, @example @group vpath %.c foo vpath % blish vpath %.c bar @end group @end example @noindent will look for a file ending in @samp{.c} in @file{foo}, then @file{blish}, then @file{bar}, while @example @group vpath %.c foo:bar vpath % blish @end group @end example @noindent will look for a file ending in @samp{.c} in @file{foo}, then @file{bar}, then @file{blish}. @node Search Algorithm, Commands/Search, Selective Search, Directory Search @subsection How Directory Searches are Performed @cindex algorithm for directory search @cindex directory search algorithm When a dependency is found through directory search, regardless of type (general or selective), the pathname located may not be the one that @code{make} actually provides you in the dependency list. Sometimes the path discovered through directory search is thrown away. The algorithm @code{make} uses to decide whether to keep or abandon a path found via directory search is as follows: @enumerate @item If a target file does not exist at the path specified in the makefile, directory search is performed. @item If the directory search is successful, that path is kept and this file is tentatively stored as the target. @item All dependencies of this target are examined using this same method. @item After processing the dependencies, the target may or may not need to be rebuilt: @enumerate a @item If the target does @emph{not} need to be rebuilt, the path to the file found during directory search is used for any dependency lists which contain this target. In short, if @code{make} doesn't need to rebuild the target then you use the path found via directory search. @item If the target @emph{does} need to be rebuilt (is out-of-date), the pathname found during directory search is @emph{thrown away}, and the target is rebuilt using the file name specified in the makefile. In short, if @code{make} must rebuild, then the target is rebuilt locally, not in the directory found via directory search. @end enumerate @end enumerate This algorithm may seem complex, but in practice it is quite often exactly what you want. @cindex traditional directory search @cindex directory search, traditional Other versions of @code{make} use a simpler algorithm: if the file does not exist, and it is found via directory search, then that pathname is always used whether or not the target needs to be built. Thus, if the target is rebuilt it is created at the pathname discovered during directory search. @vindex GPATH If, in fact, this is the behavior you want for some or all of your directories, you can use the @code{GPATH} variable to indicate this to @code{make}. @code{GPATH} has the same syntax and format as @code{VPATH} (that is, a space- or colon-delimited list of pathnames). If an out-of-date target is found by directory search in a directory that also appears in @code{GPATH}, then that pathname is not thrown away. The target is rebuilt using the expanded path. @node Commands/Search, Implicit/Search, Search Algorithm, Directory Search @subsection Writing Shell Commands with Directory Search @cindex shell command, and directory search @cindex directory search (@code{VPATH}), and shell commands When a dependency is found in another directory through directory search, this cannot change the commands of the rule; they will execute as written. Therefore, you must write the commands with care so that they will look for the dependency in the directory where @code{make} finds it. This is done with the @dfn{automatic variables} such as @samp{$^} (@pxref{Automatic, ,Automatic Variables}). For instance, the value of @samp{$^} is a list of all the dependencies of the rule, including the names of the directories in which they were found, and the value of @samp{$@@} is the target. Thus:@refill @example foo.o : foo.c cc -c $(CFLAGS)$^ -o $@@ @end example @noindent (The variable @code{CFLAGS} exists so you can specify flags for C compilation by implicit rules; we use it here for consistency so it will affect all C compilations uniformly; @pxref{Implicit Variables, ,Variables Used by Implicit Rules}.) Often the dependencies include header files as well, which you do not want to mention in the commands. The automatic variable @samp{$<} is just the first dependency: @example VPATH = src:../headers foo.o : foo.c defs.h hack.h cc -c $(CFLAGS)$< -o $@@ @end example @node Implicit/Search, Libraries/Search, Commands/Search, Directory Search @subsection Directory Search and Implicit Rules @cindex @code{VPATH}, and implicit rules @cindex directory search (@code{VPATH}), and implicit rules @cindex search path for dependencies (@code{VPATH}), and implicit rules @cindex implicit rule, and directory search @cindex implicit rule, and @code{VPATH} @cindex rule, implicit, and directory search @cindex rule, implicit, and @code{VPATH} The search through the directories specified in @code{VPATH} or with @code{vpath} also happens during consideration of implicit rules (@pxref{Implicit Rules, ,Using Implicit Rules}). For example, when a file @file{foo.o} has no explicit rule, @code{make} considers implicit rules, such as the built-in rule to compile @file{foo.c} if that file exists. If such a file is lacking in the current directory, the appropriate directories are searched for it. If @file{foo.c} exists (or is mentioned in the makefile) in any of the directories, the implicit rule for C compilation is applied. The commands of implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort. @node Libraries/Search, , Implicit/Search, Directory Search @subsection Directory Search for Link Libraries @cindex link libraries, and directory search @cindex libraries for linking, directory search @cindex directory search (@code{VPATH}), and link libraries @cindex @code{VPATH}, and link libraries @cindex search path for dependencies (@code{VPATH}), and link libraries @cindex @code{-l} (library search) Directory search applies in a special way to libraries used with the linker. This special feature comes into play when you write a dependency whose name is of the form @samp{-l@var{name}}. (You can tell something strange is going on here because the dependency is normally the name of a file, and the @emph{file name} of the library looks like @file{lib@var{name}.a}, not like @samp{-l@var{name}}.)@refill When a dependency's name has the form @samp{-l@var{name}}, @code{make} handles it specially by searching for the file @file{lib@var{name}.a} in the current directory, in directories specified by matching @code{vpath} search paths and the @code{VPATH} search path, and then in the directories @file{/lib}, @file{/usr/lib}, and @file{@var{prefix}/lib} (normally @file{/usr/local/lib}, but MS-DOS/MS-Windows versions of @code{make} behave as if @var{prefix} is defined to be the root of the DJGPP installation tree). For example, @example @group foo : foo.c -lcurses cc$^ -o $@@ @end group @end example @noindent would cause the command @samp{cc foo.c /usr/lib/libcurses.a -o foo} to be executed when @file{foo} is older than @file{foo.c} or than @file{/usr/lib/libcurses.a}.@refill @node Phony Targets, Force Targets, Directory Search, Rules @section Phony Targets @cindex phony targets @cindex targets, phony @cindex targets without a file A phony target is one that is not really the name of a file. It is just a name for some commands to be executed when you make an explicit request. There are two reasons to use a phony target: to avoid a conflict with a file of the same name, and to improve performance. If you write a rule whose commands will not create the target file, the commands will be executed every time the target comes up for remaking. Here is an example: @example @group clean: rm *.o temp @end group @end example @noindent Because the @code{rm} command does not create a file named @file{clean}, probably no such file will ever exist. Therefore, the @code{rm} command will be executed every time you say @samp{make clean}. @cindex @code{rm} (shell command) @findex .PHONY The phony target will cease to work if anything ever does create a file named @file{clean} in this directory. Since it has no dependencies, the file @file{clean} would inevitably be considered up to date, and its commands would not be executed. To avoid this problem, you can explicitly declare the target to be phony, using the special target @code{.PHONY} (@pxref{Special Targets, ,Special Built-in Target Names}) as follows: @example .PHONY : clean @end example @noindent Once this is done, @samp{make clean} will run the commands regardless of whether there is a file named @file{clean}. Since it knows that phony targets do not name actual files that could be remade from other files, @code{make} skips the implicit rule search for phony targets (@pxref{Implicit Rules}). This is why declaring a target phony is good for performance, even if you are not worried about the actual file existing. Thus, you first write the line that states that @code{clean} is a phony target, then you write the rule, like this: @example @group .PHONY: clean clean: rm *.o temp @end group @end example A phony target should not be a dependency of a real target file; if it is, its commands are run every time @code{make} goes to update that file. As long as a phony target is never a dependency of a real target, the phony target commands will be executed only when the phony target is a specified goal (@pxref{Goals, ,Arguments to Specify the Goals}). Phony targets can have dependencies. When one directory contains multiple programs, it is most convenient to describe all of the programs in one makefile @file{./Makefile}. Since the target remade by default will be the first one in the makefile, it is common to make this a phony target named @samp{all} and give it, as dependencies, all the individual programs. For example: @example all : prog1 prog2 prog3 .PHONY : all prog1 : prog1.o utils.o cc -o prog1 prog1.o utils.o prog2 : prog2.o cc -o prog2 prog2.o prog3 : prog3.o sort.o utils.o cc -o prog3 prog3.o sort.o utils.o @end example @noindent Now you can say just @samp{make} to remake all three programs, or specify as arguments the ones to remake (as in @samp{make prog1 prog3}). When one phony target is a dependency of another, it serves as a subroutine of the other. For example, here @samp{make cleanall} will delete the object files, the difference files, and the file @file{program}: @example .PHONY: cleanall cleanobj cleandiff cleanall : cleanobj cleandiff rm program cleanobj : rm *.o cleandiff : rm *.diff @end example @node Force Targets, Empty Targets, Phony Targets, Rules @section Rules without Commands or Dependencies @cindex force targets @cindex targets, force @cindex @code{FORCE} @cindex rule, no commands or dependencies If a rule has no dependencies or commands, and the target of the rule is a nonexistent file, then @code{make} imagines this target to have been updated whenever its rule is run. This implies that all targets depending on this one will always have their commands run. An example will illustrate this: @example @group clean: FORCE rm$(objects) FORCE: @end group @end example Here the target @samp{FORCE} satisfies the special conditions, so the target @file{clean} that depends on it is forced to run its commands. There is nothing special about the name @samp{FORCE}, but that is one name commonly used this way. As you can see, using @samp{FORCE} this way has the same results as using @samp{.PHONY: clean}. Using @samp{.PHONY} is more explicit and more efficient. However, other versions of @code{make} do not support @samp{.PHONY}; thus @samp{FORCE} appears in many makefiles. @xref{Phony Targets}. @node Empty Targets, Special Targets, Force Targets, Rules @section Empty Target Files to Record Events @cindex empty targets @cindex targets, empty @cindex recording events with empty targets The @dfn{empty target} is a variant of the phony target; it is used to hold commands for an action that you request explicitly from time to time. Unlike a phony target, this target file can really exist; but the file's contents do not matter, and usually are empty. The purpose of the empty target file is to record, with its last-modification time, when the rule's commands were last executed. It does so because one of the commands is a @code{touch} command to update the target file. The empty target file must have some dependencies. When you ask to remake the empty target, the commands are executed if any dependency is more recent than the target; in other words, if a dependency has changed since the last time you remade the target. Here is an example: @example print: foo.c bar.c lpr -p $? touch print @end example @cindex @code{print} target @cindex @code{lpr} (shell command) @cindex @code{touch} (shell command) @noindent With this rule, @samp{make print} will execute the @code{lpr} command if either source file has changed since the last @samp{make print}. The automatic variable @samp{$?} is used to print only those files that have changed (@pxref{Automatic, ,Automatic Variables}). @node Special Targets, Multiple Targets, Empty Targets, Rules @section Special Built-in Target Names @cindex special targets @cindex built-in special targets @cindex targets, built-in special Certain names have special meanings if they appear as targets. @table @code @findex .PHONY @item .PHONY The dependencies of the special target @code{.PHONY} are considered to be phony targets. When it is time to consider such a target, @code{make} will run its commands unconditionally, regardless of whether a file with that name exists or what its last-modification time is. @xref{Phony Targets, ,Phony Targets}. @findex .SUFFIXES @item .SUFFIXES The dependencies of the special target @code{.SUFFIXES} are the list of suffixes to be used in checking for suffix rules. @xref{Suffix Rules, , Old-Fashioned Suffix Rules}. @findex .DEFAULT @item .DEFAULT The commands specified for @code{.DEFAULT} are used for any target for which no rules are found (either explicit rules or implicit rules). @xref{Last Resort}. If @code{.DEFAULT} commands are specified, every file mentioned as a dependency, but not as a target in a rule, will have these commands executed on its behalf. @xref{Implicit Rule Search, ,Implicit Rule Search Algorithm}. @findex .PRECIOUS @item .PRECIOUS @cindex precious targets @cindex preserving with @code{.PRECIOUS} The targets which @code{.PRECIOUS} depends on are given the following special treatment: if @code{make} is killed or interrupted during the execution of their commands, the target is not deleted. @xref{Interrupts, ,Interrupting or Killing @code{make}}. Also, if the target is an intermediate file, it will not be deleted after it is no longer needed, as is normally done. @xref{Chained Rules, ,Chains of Implicit Rules}. You can also list the target pattern of an implicit rule (such as @samp{%.o}) as a dependency file of the special target @code{.PRECIOUS} to preserve intermediate files created by rules whose target patterns match that file's name. @findex .INTERMEDIATE @item .INTERMEDIATE @cindex intermediate targets, explicit The targets which @code{.INTERMEDIATE} depends on are treated as intermediate files. @xref{Chained Rules, ,Chains of Implicit Rules}. @code{.INTERMEDIATE} with no dependencies marks all file targets mentioned in the makefile as intermediate. @findex .SECONDARY @item .SECONDARY @cindex secondary targets @cindex preserving with @code{.SECONDARY} The targets which @code{.SECONDARY} depends on are treated as intermediate files, except that they are never automatically deleted. @xref{Chained Rules, ,Chains of Implicit Rules}. @code{.SECONDARY} with no dependencies marks all file targets mentioned in the makefile as secondary. @findex .IGNORE @item .IGNORE If you specify dependencies for @code{.IGNORE}, then @code{make} will ignore errors in execution of the commands run for those particular files. The commands for @code{.IGNORE} are not meaningful. If mentioned as a target with no dependencies, @code{.IGNORE} says to ignore errors in execution of commands for all files. This usage of @samp{.IGNORE} is supported only for historical compatibility. Since this affects every command in the makefile, it is not very useful; we recommend you use the more selective ways to ignore errors in specific commands. @xref{Errors, ,Errors in Commands}. @findex .SILENT @item .SILENT If you specify dependencies for @code{.SILENT}, then @code{make} will not the print commands to remake those particular files before executing them. The commands for @code{.SILENT} are not meaningful. If mentioned as a target with no dependencies, @code{.SILENT} says not to print any commands before executing them. This usage of @samp{.SILENT} is supported only for historical compatibility. We recommend you use the more selective ways to silence specific commands. @xref{Echoing, ,Command Echoing}. If you want to silence all commands for a particular run of @code{make}, use the @samp{-s} or @w{@samp{--silent}} option (@pxref{Options Summary}). @findex .EXPORT_ALL_VARIABLES @item .EXPORT_ALL_VARIABLES Simply by being mentioned as a target, this tells @code{make} to export all variables to child processes by default. @xref{Variables/Recursion, ,Communicating Variables to a Sub-@code{make}}. @end table Any defined implicit rule suffix also counts as a special target if it appears as a target, and so does the concatenation of two suffixes, such as @samp{.c.o}. These targets are suffix rules, an obsolete way of defining implicit rules (but a way still widely used). In principle, any target name could be special in this way if you break it in two and add both pieces to the suffix list. In practice, suffixes normally begin with @samp{.}, so these special target names also begin with @samp{.}. @xref{Suffix Rules, ,Old-Fashioned Suffix Rules}. @node Multiple Targets, Multiple Rules, Special Targets, Rules @section Multiple Targets in a Rule @cindex multiple targets @cindex several targets in a rule @cindex targets, multiple @cindex rule, with multiple targets A rule with multiple targets is equivalent to writing many rules, each with one target, and all identical aside from that. The same commands apply to all the targets, but their effects may vary because you can substitute the actual target name into the command using @samp{$@@}. The rule contributes the same dependencies to all the targets also. This is useful in two cases. @itemize @bullet @item You want just dependencies, no commands. For example: @example kbd.o command.o files.o: command.h @end example @noindent gives an additional dependency to each of the three object files mentioned. @item Similar commands work for all the targets. The commands do not need to be absolutely identical, since the automatic variable @samp{$@@} can be used to substitute the particular target to be remade into the commands (@pxref{Automatic, ,Automatic Variables}). For example: @example @group bigoutput littleoutput : text.g generate text.g -$(subst output,,$@@) > $@@ @end group @end example @findex subst @noindent is equivalent to @example bigoutput : text.g generate text.g -big > bigoutput littleoutput : text.g generate text.g -little > littleoutput @end example @noindent Here we assume the hypothetical program @code{generate} makes two types of output, one if given @samp{-big} and one if given @samp{-little}. @xref{Text Functions, ,Functions for String Substitution and Analysis}, for an explanation of the @code{subst} function. @end itemize Suppose you would like to vary the dependencies according to the target, much as the variable @samp{$@@} allows you to vary the commands. You cannot do this with multiple targets in an ordinary rule, but you can do it with a @dfn{static pattern rule}. @xref{Static Pattern, ,Static Pattern Rules}. @node Multiple Rules, Static Pattern, Multiple Targets, Rules @section Multiple Rules for One Target @cindex multiple rules for one target @cindex several rules for one target @cindex rule, multiple for one target @cindex target, multiple rules for one One file can be the target of several rules. All the dependencies mentioned in all the rules are merged into one list of dependencies for the target. If the target is older than any dependency from any rule, the commands are executed. There can only be one set of commands to be executed for a file. If more than one rule gives commands for the same file, @code{make} uses the last set given and prints an error message. (As a special case, if the file's name begins with a dot, no error message is printed. This odd behavior is only for compatibility with other implementations of @code{make}.) There is no reason to write your makefiles this way; that is why @code{make} gives you an error message.@refill An extra rule with just dependencies can be used to give a few extra dependencies to many files at once. For example, one usually has a variable named @code{objects} containing a list of all the compiler output files in the system being made. An easy way to say that all of them must be recompiled if @file{config.h} changes is to write the following: @example objects = foo.o bar.o foo.o : defs.h bar.o : defs.h test.h $(objects) : config.h @end example This could be inserted or taken out without changing the rules that really specify how to make the object files, making it a convenient form to use if you wish to add the additional dependency intermittently. Another wrinkle is that the additional dependencies could be specified with a variable that you set with a command argument to @code{make} (@pxref{Overriding, ,Overriding Variables}). For example, @example @group extradeps=$(objects) : $(extradeps) @end group @end example @noindent means that the command @samp{make extradeps=foo.h} will consider @file{foo.h} as a dependency of each object file, but plain @samp{make} will not. If none of the explicit rules for a target has commands, then @code{make} searches for an applicable implicit rule to find some commands @pxref{Implicit Rules, ,Using Implicit Rules}). @node Static Pattern, Double-Colon, Multiple Rules, Rules @section Static Pattern Rules @cindex static pattern rule @cindex rule, static pattern @cindex pattern rules, static (not implicit) @cindex varying dependencies @cindex dependencies, varying (static pattern) @dfn{Static pattern rules} are rules which specify multiple targets and construct the dependency names for each target based on the target name. They are more general than ordinary rules with multiple targets because the targets do not have to have identical dependencies. Their dependencies must be @emph{analogous}, but not necessarily @emph{identical}. @menu * Static Usage:: The syntax of static pattern rules. * Static versus Implicit:: When are they better than implicit rules? @end menu @node Static Usage, Static versus Implicit, , Static Pattern @subsection Syntax of Static Pattern Rules @cindex static pattern rule, syntax of @cindex pattern rules, static, syntax of Here is the syntax of a static pattern rule: @example @var{targets} @dots{}: @var{target-pattern}: @var{dep-patterns} @dots{} @var{commands} @dots{} @end example @noindent The @var{targets} list specifies the targets that the rule applies to. The targets can contain wildcard characters, just like the targets of ordinary rules (@pxref{Wildcards, ,Using Wildcard Characters in File Names}). @cindex target pattern, static (not implicit) @cindex stem The @var{target-pattern} and @var{dep-patterns} say how to compute the dependencies of each target. Each target is matched against the @var{target-pattern} to extract a part of the target name, called the @dfn{stem}. This stem is substituted into each of the @var{dep-patterns} to make the dependency names (one from each @var{dep-pattern}). Each pattern normally contains the character @samp{%} just once. When the @var{target-pattern} matches a target, the @samp{%} can match any part of the target name; this part is called the @dfn{stem}. The rest of the pattern must match exactly. For example, the target @file{foo.o} matches the pattern @samp{%.o}, with @samp{foo} as the stem. The targets @file{foo.c} and @file{foo.out} do not match that pattern.@refill @cindex dependency pattern, static (not implicit) The dependency names for each target are made by substituting the stem for the @samp{%} in each dependency pattern. For example, if one dependency pattern is @file{%.c}, then substitution of the stem @samp{foo} gives the dependency name @file{foo.c}. It is legitimate to write a dependency pattern that does not contain @samp{%}; then this dependency is the same for all targets. @cindex @code{%}, quoting in static pattern @cindex @code{%}, quoting with @code{\} (backslash) @cindex @code{\} (backslash), to quote @code{%} @cindex backslash (@code{\}), to quote @code{%} @cindex quoting @code{%}, in static pattern @samp{%} characters in pattern rules can be quoted with preceding backslashes (@samp{\}). Backslashes that would otherwise quote @samp{%} characters can be quoted with more backslashes. Backslashes that quote @samp{%} characters or other backslashes are removed from the pattern before it is compared to file names or has a stem substituted into it. Backslashes that are not in danger of quoting @samp{%} characters go unmolested. For example, the pattern @file{the\%weird\\%pattern\\} has @samp{the%weird\} preceding the operative @samp{%} character, and @samp{pattern\\} following it. The final two backslashes are left alone because they cannot affect any @samp{%} character.@refill Here is an example, which compiles each of @file{foo.o} and @file{bar.o} from the corresponding @file{.c} file: @example @group objects = foo.o bar.o all:$(objects) $(objects): %.o: %.c$(CC) -c $(CFLAGS)$< -o $@@ @end group @end example @noindent Here @samp{$<} is the automatic variable that holds the name of the dependency and @samp{$@@} is the automatic variable that holds the name of the target; see @ref{Automatic, , Automatic Variables}. Each target specified must match the target pattern; a warning is issued for each target that does not. If you have a list of files, only some of which will match the pattern, you can use the @code{filter} function to remove nonmatching file names (@pxref{Text Functions, ,Functions for String Substitution and Analysis}): @example files = foo.elc bar.o lose.o$(filter %.o,$(files)): %.o: %.c$(CC) -c $(CFLAGS)$< -o $@@$(filter %.elc,$(files)): %.elc: %.el emacs -f batch-byte-compile$< @end example @noindent In this example the result of @samp{$(filter %.o,$(files))} is @file{bar.o lose.o}, and the first static pattern rule causes each of these object files to be updated by compiling the corresponding C source file. The result of @w{@samp{$(filter %.elc,$(files))}} is @file{foo.elc}, so that file is made from @file{foo.el}.@refill Another example shows how to use @code{$*} in static pattern rules: @vindex$*@r{, and static pattern} @example @group bigoutput littleoutput : %output : text.g generate text.g -$* >$@@ @end group @end example @noindent When the @code{generate} command is run, @code{$*} will expand to the stem, either @samp{big} or @samp{little}. @node Static versus Implicit, , Static Usage, Static Pattern @subsection Static Pattern Rules versus Implicit Rules @cindex rule, static pattern versus implicit @cindex static pattern rule, versus implicit A static pattern rule has much in common with an implicit rule defined as a pattern rule (@pxref{Pattern Rules, ,Defining and Redefining Pattern Rules}). Both have a pattern for the target and patterns for constructing the names of dependencies. The difference is in how @code{make} decides @emph{when} the rule applies. An implicit rule @emph{can} apply to any target that matches its pattern, but it @emph{does} apply only when the target has no commands otherwise specified, and only when the dependencies can be found. If more than one implicit rule appears applicable, only one applies; the choice depends on the order of rules. By contrast, a static pattern rule applies to the precise list of targets that you specify in the rule. It cannot apply to any other target and it invariably does apply to each of the targets specified. If two conflicting rules apply, and both have commands, that's an error. The static pattern rule can be better than an implicit rule for these reasons: @itemize @bullet @item You may wish to override the usual implicit rule for a few files whose names cannot be categorized syntactically but can be given in an explicit list. @item If you cannot be sure of the precise contents of the directories you are using, you may not be sure which other irrelevant files might lead @code{make} to use the wrong implicit rule. The choice might depend on the order in which the implicit rule search is done. With static pattern rules, there is no uncertainty: each rule applies to precisely the targets specified. @end itemize @node Double-Colon, Automatic Dependencies, Static Pattern, Rules @section Double-Colon Rules @cindex double-colon rules @cindex rule, double-colon (@code{::}) @cindex multiple rules for one target (@code{::}) @cindex @code{::} rules (double-colon) @dfn{Double-colon} rules are rules written with @samp{::} instead of @samp{:} after the target names. They are handled differently from ordinary rules when the same target appears in more than one rule. When a target appears in multiple rules, all the rules must be the same type: all ordinary, or all double-colon. If they are double-colon, each of them is independent of the others. Each double-colon rule's commands are executed if the target is older than any dependencies of that rule. This can result in executing none, any, or all of the double-colon rules. Double-colon rules with the same target are in fact completely separate from one another. Each double-colon rule is processed individually, just as rules with different targets are processed. The double-colon rules for a target are executed in the order they appear in the makefile. However, the cases where double-colon rules really make sense are those where the order of executing the commands would not matter. Double-colon rules are somewhat obscure and not often very useful; they provide a mechanism for cases in which the method used to update a target differs depending on which dependency files caused the update, and such cases are rare. Each double-colon rule should specify commands; if it does not, an implicit rule will be used if one applies. @xref{Implicit Rules, ,Using Implicit Rules}. @node Automatic Dependencies, , Double-Colon, Rules @section Generating Dependencies Automatically @cindex dependencies, automatic generation @cindex automatic generation of dependencies @cindex generating dependencies automatically In the makefile for a program, many of the rules you need to write often say only that some object file depends on some header file. For example, if @file{main.c} uses @file{defs.h} via an @code{#include}, you would write: @example main.o: defs.h @end example @noindent You need this rule so that @code{make} knows that it must remake @file{main.o} whenever @file{defs.h} changes. You can see that for a large program you would have to write dozens of such rules in your makefile. And, you must always be very careful to update the makefile every time you add or remove an @code{#include}. @cindex @code{#include} @cindex @code{-M} (to compiler) To avoid this hassle, most modern C compilers can write these rules for you, by looking at the @code{#include} lines in the source files. Usually this is done with the @samp{-M} option to the compiler. For example, the command: @example cc -M main.c @end example @noindent generates the output: @example main.o : main.c defs.h @end example @noindent Thus you no longer have to write all those rules yourself. The compiler will do it for you. Note that such a dependency constitutes mentioning @file{main.o} in a makefile, so it can never be considered an intermediate file by implicit rule search. This means that @code{make} won't ever remove the file after using it; @pxref{Chained Rules, ,Chains of Implicit Rules}. @cindex @code{make depend} With old @code{make} programs, it was traditional practice to use this compiler feature to generate dependencies on demand with a command like @samp{make depend}. That command would create a file @file{depend} containing all the automatically-generated dependencies; then the makefile could use @code{include} to read them in (@pxref{Include}). In GNU @code{make}, the feature of remaking makefiles makes this practice obsolete---you need never tell @code{make} explicitly to regenerate the dependencies, because it always regenerates any makefile that is out of date. @xref{Remaking Makefiles}. The practice we recommend for automatic dependency generation is to have one makefile corresponding to each source file. For each source file @file{@var{name}.c} there is a makefile @file{@var{name}.d} which lists what files the object file @file{@var{name}.o} depends on. That way only the source files that have changed need to be rescanned to produce the new dependencies. Here is the pattern rule to generate a file of dependencies (i.e., a makefile) called @file{@var{name}.d} from a C source file called @file{@var{name}.c}: @smallexample @group %.d: %.c$(SHELL) -ec '$(CC) -M$(CPPFLAGS) $< \ | sed '\''s/$$*$$\.o[ :]*/\1.o$@@ : /g'\'' > $@@; \ [ -s$@@ ] || rm -f $@@' @end group @end smallexample @noindent @xref{Pattern Rules}, for information on defining pattern rules. The @samp{-e} flag to the shell makes it exit immediately if the @code{$(CC)} command fails (exits with a nonzero status). Normally the shell exits with the status of the last command in the pipeline (@code{sed} in this case), so @code{make} would not notice a nonzero status from the compiler. @cindex @code{-e} (shell flag) @cindex @code{-MM} (to GNU compiler) With the GNU C compiler, you may wish to use the @samp{-MM} flag instead of @samp{-M}. This omits dependencies on system header files. @xref{Preprocessor Options, , Options Controlling the Preprocessor, gcc.info, Using GNU CC}, for details. @cindex @code{sed} (shell command) The purpose of the @code{sed} command is to translate (for example): @example main.o : main.c defs.h @end example @noindent into: @example main.o main.d : main.c defs.h @end example @noindent @cindex @code{.d} This makes each @samp{.d} file depend on all the source and header files that the corresponding @samp{.o} file depends on. @code{make} then knows it must regenerate the dependencies whenever any of the source or header files changes. Once you've defined the rule to remake the @samp{.d} files, you then use the @code{include} directive to read them all in. @xref{Include}. For example: @example @group sources = foo.c bar.c include $(sources:.c=.d) @end group @end example @noindent (This example uses a substitution variable reference to translate the list of source files @samp{foo.c bar.c} into a list of dependency makefiles, @samp{foo.d bar.d}. @xref{Substitution Refs}, for full information on substitution references.) Since the @samp{.d} files are makefiles like any others, @code{make} will remake them as necessary with no further work from you. @xref{Remaking Makefiles}. @node Commands, Using Variables, Rules, Top @chapter Writing the Commands in Rules @cindex commands, how to write @cindex rule commands @cindex writing rule commands The commands of a rule consist of shell command lines to be executed one by one. Each command line must start with a tab, except that the first command line may be attached to the target-and-dependencies line with a semicolon in between. Blank lines and lines of just comments may appear among the command lines; they are ignored. (But beware, an apparently blank'' line that begins with a tab is @emph{not} blank! It is an empty command; @pxref{Empty Commands}.) Users use many different shell programs, but commands in makefiles are always interpreted by @file{/bin/sh} unless the makefile specifies otherwise. @xref{Execution, ,Command Execution}. @cindex comments, in commands @cindex commands, comments in @cindex @code{#} (comments), in commands The shell that is in use determines whether comments can be written on command lines, and what syntax they use. When the shell is @file{/bin/sh}, a @samp{#} starts a comment that extends to the end of the line. The @samp{#} does not have to be at the beginning of a line. Text on a line before a @samp{#} is not part of the comment. @menu * Echoing:: How to control when commands are echoed. * Execution:: How commands are executed. * Parallel:: How commands can be executed in parallel. * Errors:: What happens after a command execution error. * Interrupts:: What happens when a command is interrupted. * Recursion:: Invoking @code{make} from makefiles. * Sequences:: Defining canned sequences of commands. * Empty Commands:: Defining useful, do-nothing commands. @end menu @node Echoing, Execution, , Commands @section Command Echoing @cindex echoing of commands @cindex silent operation @cindex @code{@@} (in commands) @cindex commands, echoing @cindex printing of commands Normally @code{make} prints each command line before it is executed. We call this @dfn{echoing} because it gives the appearance that you are typing the commands yourself. When a line starts with @samp{@@}, the echoing of that line is suppressed. The @samp{@@} is discarded before the command is passed to the shell. Typically you would use this for a command whose only effect is to print something, such as an @code{echo} command to indicate progress through the makefile: @example @@echo About to make distribution files @end example @cindex @code{-n} @cindex @code{--just-print} @cindex @code{--dry-run} @cindex @code{--recon} When @code{make} is given the flag @samp{-n} or @samp{--just-print}, echoing is all that happens, no execution. @xref{Options Summary, ,Summary of Options}. In this case and only this case, even the commands starting with @samp{@@} are printed. This flag is useful for finding out which commands @code{make} thinks are necessary without actually doing them. @cindex @code{-s} @cindex @code{--silent} @cindex @code{--quiet} @findex .SILENT The @samp{-s} or @samp{--silent} flag to @code{make} prevents all echoing, as if all commands started with @samp{@@}. A rule in the makefile for the special target @code{.SILENT} without dependencies has the same effect (@pxref{Special Targets, ,Special Built-in Target Names}). @code{.SILENT} is essentially obsolete since @samp{@@} is more flexible.@refill @node Execution, Parallel, Echoing, Commands @section Command Execution @cindex commands, execution @cindex execution, of commands @cindex shell command, execution @vindex SHELL @r{(command execution)} When it is time to execute commands to update a target, they are executed by making a new subshell for each line. (In practice, @code{make} may take shortcuts that do not affect the results.) @cindex @code{cd} (shell command) @strong{Please note:} this implies that shell commands such as @code{cd} that set variables local to each process will not affect the following command lines. @footnote{On MS-DOS, the value of current working directory is @strong{global}, so changing it @emph{will} affect the following command lines on those systems.} If you want to use @code{cd} to affect the next command, put the two on a single line with a semicolon between them. Then @code{make} will consider them a single command and pass them, together, to a shell which will execute them in sequence. For example: @example foo : bar/lose cd bar; gobble lose > ../foo @end example @cindex commands, backslash (@code{\}) in @cindex commands, quoting newlines in @cindex backslash (@code{\}), in commands @cindex @code{\} (backslash), in commands @cindex quoting newline, in commands @cindex newline, quoting, in commands If you would like to split a single shell command into multiple lines of text, you must use a backslash at the end of all but the last subline. Such a sequence of lines is combined into a single line, by deleting the backslash-newline sequences, before passing it to the shell. Thus, the following is equivalent to the preceding example: @example @group foo : bar/lose cd bar; \ gobble lose > ../foo @end group @end example @vindex SHELL The program used as the shell is taken from the variable @code{SHELL}. By default, the program @file{/bin/sh} is used. @vindex COMSPEC On MS-DOS, if @code{SHELL} is not set, the value of the variable @code{COMSPEC} (which is always set) is used instead. @cindex @code{SHELL}, MS-DOS specifics The processing of lines that set the variable @code{SHELL} in Makefiles is different on MS-DOS. The stock shell, @file{command.com}, is ridiculously limited in its functionality and many users of @code{make} tend to install a replacement shell. Therefore, on MS-DOS, @code{make} examines the value of @code{SHELL}, and changes its behavior based on whether it points to a Unix-style or DOS-style shell. This allows reasonable functionality even if @code{SHELL} points to @file{command.com}. If @code{SHELL} points to a Unix-style shell, @code{make} on MS-DOS additionally checks whether that shell can indeed be found; if not, it ignores the line that sets @code{SHELL}. In MS-DOS, GNU @code{make} searches for the shell in the following places: @enumerate @item In the precise place pointed to by the value of @code{SHELL}. For example, if the makefile specifies @samp{SHELL = /bin/sh}, @code{make} will look in the directory @file{/bin} on the current drive. @item In the current directory. @item In each of the directories in the @code{PATH} variable, in order. @end enumerate In every directory it examines, @code{make} will first look for the specific file (@file{sh} in the example above). If this is not found, it will also look in that directory for that file with one of the known extensions which identify executable files. For example @file{.exe}, @file{.com}, @file{.bat}, @file{.btm}, @file{.sh}, and some others. If any of these attempts is successful, the value of @code{SHELL} will be set to the full pathname of the shell as found. However, if none of these is found, the value of @code{SHELL} will not be changed, and thus the line that sets it will be effectively ignored. This is so @code{make} will only support features specific to a Unix-style shell if such a shell is actually installed on the system where @code{make} runs. Note that this extended search for the shell is limited to the cases where @code{SHELL} is set from the Makefile; if it is set in the environment or command line, you are expected to set it to the full pathname of the shell, exactly as things are on Unix. The effect of the above DOS-specific processing is that a Makefile that says @samp{SHELL = /bin/sh} (as many Unix makefiles do), will work on MS-DOS unaltered if you have e.g. @file{sh.exe} installed in some directory along your @code{PATH}. @cindex environment, @code{SHELL} in Unlike most variables, the variable @code{SHELL} is never set from the environment. This is because the @code{SHELL} environment variable is used to specify your personal choice of shell program for interactive use. It would be very bad for personal choices like this to affect the functioning of makefiles. @xref{Environment, ,Variables from the Environment}. However, on MS-DOS and MS-Windows the value of @code{SHELL} in the environment @strong{is} used, since on those systems most users do not set this variable, and therefore it is most likely set specifically to be used by @code{make}. On MS-DOS, if the setting of @code{SHELL} is not suitable for @code{make}, you can set the variable @code{MAKESHELL} to the shell that @code{make} should use; this will override the value of @code{SHELL}. @node Parallel, Errors, Execution, Commands @section Parallel Execution @cindex commands, execution in parallel @cindex parallel execution @cindex execution, in parallel @cindex job slots @cindex @code{-j} @cindex @code{--jobs} GNU @code{make} knows how to execute several commands at once. Normally, @code{make} will execute only one command at a time, waiting for it to finish before executing the next. However, the @samp{-j} or @samp{--jobs} option tells @code{make} to execute many commands simultaneously.@refill On MS-DOS, the @samp{-j} option has no effect, since that system doesn't support multi-processing. If the @samp{-j} option is followed by an integer, this is the number of commands to execute at once; this is called the number of @dfn{job slots}. If there is nothing looking like an integer after the @samp{-j} option, there is no limit on the number of job slots. The default number of job slots is one, which means serial execution (one thing at a time). One unpleasant consequence of running several commands simultaneously is that output from all of the commands comes when the commands send it, so messages from different commands may be interspersed. Another problem is that two processes cannot both take input from the same device; so to make sure that only one command tries to take input from the terminal at once, @code{make} will invalidate the standard input streams of all but one running command. This means that attempting to read from standard input will usually be a fatal error (a @samp{Broken pipe} signal) for most child processes if there are several. @cindex broken pipe @cindex standard input It is unpredictable which command will have a valid standard input stream (which will come from the terminal, or wherever you redirect the standard input of @code{make}). The first command run will always get it first, and the first command started after that one finishes will get it next, and so on. We will change how this aspect of @code{make} works if we find a better alternative. In the mean time, you should not rely on any command using standard input at all if you are using the parallel execution feature; but if you are not using this feature, then standard input works normally in all commands. If a command fails (is killed by a signal or exits with a nonzero status), and errors are not ignored for that command (@pxref{Errors, ,Errors in Commands}), the remaining command lines to remake the same target will not be run. If a command fails and the @samp{-k} or @samp{--keep-going} option was not given (@pxref{Options Summary, ,Summary of Options}), @code{make} aborts execution. If make terminates for any reason (including a signal) with child processes running, it waits for them to finish before actually exiting.@refill @cindex load average @cindex limiting jobs based on load @cindex jobs, limiting based on load @cindex @code{-l} (load average) @cindex @code{--max-load} @cindex @code{--load-average} When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded. You can use the @samp{-l} option to tell @code{make} to limit the number of jobs to run at once, based on the load average. The @samp{-l} or @samp{--max-load} option is followed by a floating-point number. For example, @example -l 2.5 @end example @noindent will not let @code{make} start more than one job if the load average is above 2.5. The @samp{-l} option with no following number removes the load limit, if one was given with a previous @samp{-l} option.@refill More precisely, when @code{make} goes to start up a job, and it already has at least one job running, it checks the current load average; if it is not lower than the limit given with @samp{-l}, @code{make} waits until the load average goes below that limit, or until all the other jobs finish. By default, there is no load limit. @node Errors, Interrupts, Parallel, Commands @section Errors in Commands @cindex errors (in commands) @cindex commands, errors in @cindex exit status (errors) After each shell command returns, @code{make} looks at its exit status. If the command completed successfully, the next command line is executed in a new shell; after the last command line is finished, the rule is finished. If there is an error (the exit status is nonzero), @code{make} gives up on the current rule, and perhaps on all rules. Sometimes the failure of a certain command does not indicate a problem. For example, you may use the @code{mkdir} command to ensure that a directory exists. If the directory already exists, @code{mkdir} will report an error, but you probably want @code{make} to continue regardless. @cindex @code{-} (in commands) To ignore errors in a command line, write a @samp{-} at the beginning of the line's text (after the initial tab). The @samp{-} is discarded before the command is passed to the shell for execution. For example, @example @group clean: -rm -f *.o @end group @end example @cindex @code{rm} (shell command) @noindent This causes @code{rm} to continue even if it is unable to remove a file. @cindex @code{-i} @cindex @code{--ignore-errors} @findex .IGNORE When you run @code{make} with the @samp{-i} or @samp{--ignore-errors} flag, errors are ignored in all commands of all rules. A rule in the makefile for the special target @code{.IGNORE} has the same effect, if there are no dependencies. These ways of ignoring errors are obsolete because @samp{-} is more flexible. When errors are to be ignored, because of either a @samp{-} or the @samp{-i} flag, @code{make} treats an error return just like success, except that it prints out a message that tells you the status code the command exited with, and says that the error has been ignored. When an error happens that @code{make} has not been told to ignore, it implies that the current target cannot be correctly remade, and neither can any other that depends on it either directly or indirectly. No further commands will be executed for these targets, since their preconditions have not been achieved. @cindex @code{-k} @cindex @code{--keep-going} Normally @code{make} gives up immediately in this circumstance, returning a nonzero status. However, if the @samp{-k} or @samp{--keep-going} flag is specified, @code{make} continues to consider the other dependencies of the pending targets, remaking them if necessary, before it gives up and returns nonzero status. For example, after an error in compiling one object file, @samp{make -k} will continue compiling other object files even though it already knows that linking them will be impossible. @xref{Options Summary, ,Summary of Options}. The usual behavior assumes that your purpose is to get the specified targets up to date; once @code{make} learns that this is impossible, it might as well report the failure immediately. The @samp{-k} option says that the real purpose is to test as many of the changes made in the program as possible, perhaps to find several independent problems so that you can correct them all before the next attempt to compile. This is why Emacs' @code{compile} command passes the @samp{-k} flag by default. @cindex Emacs (@code{M-x compile}) @findex .DELETE_ON_ERROR @cindex deletion of target files @cindex removal of target files @cindex target, deleting on error Usually when a command fails, if it has changed the target file at all, the file is corrupted and cannot be used---or at least it is not completely updated. Yet the file's timestamp says that it is now up to date, so the next time @code{make} runs, it will not try to update that file. The situation is just the same as when the command is killed by a signal; @pxref{Interrupts}. So generally the right thing to do is to delete the target file if the command fails after beginning to change the file. @code{make} will do this if @code{.DELETE_ON_ERROR} appears as a target. This is almost always what you want @code{make} to do, but it is not historical practice; so for compatibility, you must explicitly request it. @node Interrupts, Recursion, Errors, Commands @section Interrupting or Killing @code{make} @cindex interrupt @cindex signal @cindex deletion of target files @cindex removal of target files @cindex target, deleting on interrupt @cindex killing (interruption) If @code{make} gets a fatal signal while a command is executing, it may delete the target file that the command was supposed to update. This is done if the target file's last-modification time has changed since @code{make} first checked it. The purpose of deleting the target is to make sure that it is remade from scratch when @code{make} is next run. Why is this? Suppose you type @kbd{Ctrl-c} while a compiler is running, and it has begun to write an object file @file{foo.o}. The @kbd{Ctrl-c} kills the compiler, resulting in an incomplete file whose last-modification time is newer than the source file @file{foo.c}. But @code{make} also receives the @kbd{Ctrl-c} signal and deletes this incomplete file. If @code{make} did not do this, the next invocation of @code{make} would think that @file{foo.o} did not require updating---resulting in a strange error message from the linker when it tries to link an object file half of which is missing. @findex .PRECIOUS You can prevent the deletion of a target file in this way by making the special target @code{.PRECIOUS} depend on it. Before remaking a target, @code{make} checks to see whether it appears on the dependencies of @code{.PRECIOUS}, and thereby decides whether the target should be deleted if a signal happens. Some reasons why you might do this are that the target is updated in some atomic fashion, or exists only to record a modification-time (its contents do not matter), or must exist at all times to prevent other sorts of trouble. @node Recursion, Sequences, Interrupts, Commands @section Recursive Use of @code{make} @cindex recursion @cindex subdirectories, recursion for Recursive use of @code{make} means using @code{make} as a command in a makefile. This technique is useful when you want separate makefiles for various subsystems that compose a larger system. For example, suppose you have a subdirectory @file{subdir} which has its own makefile, and you would like the containing directory's makefile to run @code{make} on the subdirectory. You can do it by writing this: @example subsystem: cd subdir &&$(MAKE) @end example @noindent or, equivalently, this (@pxref{Options Summary, ,Summary of Options}): @example subsystem: $(MAKE) -C subdir @end example @cindex @code{-C} @cindex @code{--directory} You can write recursive @code{make} commands just by copying this example, but there are many things to know about how they work and why, and about how the sub-@code{make} relates to the top-level @code{make}. @menu * MAKE Variable:: The special effects of using @samp{$(MAKE)}. * Variables/Recursion:: How to communicate variables to a sub-@code{make}. * Options/Recursion:: How to communicate options to a sub-@code{make}. * -w Option:: How the @samp{-w} or @samp{--print-directory} option helps debug use of recursive @code{make} commands. @end menu @node MAKE Variable, Variables/Recursion, , Recursion @subsection How the @code{MAKE} Variable Works @vindex MAKE @cindex recursion, and @code{MAKE} variable Recursive @code{make} commands should always use the variable @code{MAKE}, not the explicit command name @samp{make}, as shown here: @example @group subsystem: cd subdir && $(MAKE) @end group @end example The value of this variable is the file name with which @code{make} was invoked. If this file name was @file{/bin/make}, then the command executed is @samp{cd subdir && /bin/make}. If you use a special version of @code{make} to run the top-level makefile, the same special version will be executed for recursive invocations. @cindex @code{cd} (shell command) As a special feature, using the variable @code{MAKE} in the commands of a rule alters the effects of the @samp{-t} (@samp{--touch}), @samp{-n} (@samp{--just-print}), or @samp{-q} (@w{@samp{--question}}) option. Using the @code{MAKE} variable has the same effect as using a @samp{+} character at the beginning of the command line. @xref{Instead of Execution, ,Instead of Executing the Commands}.@refill Consider the command @samp{make -t} in the above example. (The @samp{-t} option marks targets as up to date without actually running any commands; see @ref{Instead of Execution}.) Following the usual definition of @samp{-t}, a @samp{make -t} command in the example would create a file named @file{subsystem} and do nothing else. What you really want it to do is run @samp{@w{cd subdir &&} @w{make -t}}; but that would require executing the command, and @samp{-t} says not to execute commands.@refill @cindex @code{-t}, and recursion @cindex recursion, and @code{-t} @cindex @code{--touch}, and recursion The special feature makes this do what you want: whenever a command line of a rule contains the variable @code{MAKE}, the flags @samp{-t}, @samp{-n} and @samp{-q} do not apply to that line. Command lines containing @code{MAKE} are executed normally despite the presence of a flag that causes most commands not to be run. The usual @code{MAKEFLAGS} mechanism passes the flags to the sub-@code{make} (@pxref{Options/Recursion, ,Communicating Options to a Sub-@code{make}}), so your request to touch the files, or print the commands, is propagated to the subsystem.@refill @node Variables/Recursion, Options/Recursion, MAKE Variable, Recursion @subsection Communicating Variables to a Sub-@code{make} @cindex sub-@code{make} @cindex environment, and recursion @cindex exporting variables @cindex variables, environment @cindex variables, exporting @cindex recursion, and environment @cindex recursion, and variables Variable values of the top-level @code{make} can be passed to the sub-@code{make} through the environment by explicit request. These variables are defined in the sub-@code{make} as defaults, but do not override what is specified in the makefile used by the sub-@code{make} makefile unless you use the @samp{-e} switch (@pxref{Options Summary, ,Summary of Options}).@refill To pass down, or @dfn{export}, a variable, @code{make} adds the variable and its value to the environment for running each command. The sub-@code{make}, in turn, uses the environment to initialize its table of variable values. @xref{Environment, ,Variables from the Environment}. Except by explicit request, @code{make} exports a variable only if it is either defined in the environment initially or set on the command line, and if its name consists only of letters, numbers, and underscores. Some shells cannot cope with environment variable names consisting of characters other than letters, numbers, and underscores. The special variables @code{SHELL} and @code{MAKEFLAGS} are always exported (unless you unexport them). @code{MAKEFILES} is exported if you set it to anything. @code{make} automatically passes down variable values that were defined on the command line, by putting them in the @code{MAKEFLAGS} variable. @iftex See the next section. @end iftex @ifinfo @xref{Options/Recursion}. @end ifinfo Variables are @emph{not} normally passed down if they were created by default by @code{make} (@pxref{Implicit Variables, ,Variables Used by Implicit Rules}). The sub-@code{make} will define these for itself.@refill @findex export If you want to export specific variables to a sub-@code{make}, use the @code{export} directive, like this: @example export @var{variable} @dots{} @end example @noindent @findex unexport If you want to @emph{prevent} a variable from being exported, use the @code{unexport} directive, like this: @example unexport @var{variable} @dots{} @end example @noindent As a convenience, you can define a variable and export it at the same time by doing: @example export @var{variable} = value @end example @noindent has the same result as: @example @var{variable} = value export @var{variable} @end example @noindent and @example export @var{variable} := value @end example @noindent has the same result as: @example @var{variable} := value export @var{variable} @end example Likewise, @example export @var{variable} += value @end example @noindent is just like: @example @var{variable} += value export @var{variable} @end example @noindent @xref{Appending, ,Appending More Text to Variables}. You may notice that the @code{export} and @code{unexport} directives work in @code{make} in the same way they work in the shell, @code{sh}. If you want all variables to be exported by default, you can use @code{export} by itself: @example export @end example @noindent This tells @code{make} that variables which are not explicitly mentioned in an @code{export} or @code{unexport} directive should be exported. Any variable given in an @code{unexport} directive will still @emph{not} be exported. If you use @code{export} by itself to export variables by default, variables whose names contain characters other than alphanumerics and underscores will not be exported unless specifically mentioned in an @code{export} directive.@refill @findex .EXPORT_ALL_VARIABLES The behavior elicited by an @code{export} directive by itself was the default in older versions of GNU @code{make}. If your makefiles depend on this behavior and you want to be compatible with old versions of @code{make}, you can write a rule for the special target @code{.EXPORT_ALL_VARIABLES} instead of using the @code{export} directive. This will be ignored by old @code{make}s, while the @code{export} directive will cause a syntax error.@refill @cindex compatibility in exporting Likewise, you can use @code{unexport} by itself to tell @code{make} @emph{not} to export variables by default. Since this is the default behavior, you would only need to do this if @code{export} had been used by itself earlier (in an included makefile, perhaps). You @strong{cannot} use @code{export} and @code{unexport} by themselves to have variables exported for some commands and not for others. The last @code{export} or @code{unexport} directive that appears by itself determines the behavior for the entire run of @code{make}.@refill @vindex MAKELEVEL @cindex recursion, level of As a special feature, the variable @code{MAKELEVEL} is changed when it is passed down from level to level. This variable's value is a string which is the depth of the level as a decimal number. The value is @samp{0} for the top-level @code{make}; @samp{1} for a sub-@code{make}, @samp{2} for a sub-sub-@code{make}, and so on. The incrementation happens when @code{make} sets up the environment for a command.@refill The main use of @code{MAKELEVEL} is to test it in a conditional directive (@pxref{Conditionals, ,Conditional Parts of Makefiles}); this way you can write a makefile that behaves one way if run recursively and another way if run directly by you.@refill @vindex MAKEFILES You can use the variable @code{MAKEFILES} to cause all sub-@code{make} commands to use additional makefiles. The value of @code{MAKEFILES} is a whitespace-separated list of file names. This variable, if defined in the outer-level makefile, is passed down through the environment; then it serves as a list of extra makefiles for the sub-@code{make} to read before the usual or specified ones. @xref{MAKEFILES Variable, ,The Variable @code{MAKEFILES}}.@refill @node Options/Recursion, -w Option, Variables/Recursion, Recursion @subsection Communicating Options to a Sub-@code{make} @cindex options, and recursion @cindex recursion, and options @vindex MAKEFLAGS Flags such as @samp{-s} and @samp{-k} are passed automatically to the sub-@code{make} through the variable @code{MAKEFLAGS}. This variable is set up automatically by @code{make} to contain the flag letters that @code{make} received. Thus, if you do @w{@samp{make -ks}} then @code{MAKEFLAGS} gets the value @samp{ks}.@refill As a consequence, every sub-@code{make} gets a value for @code{MAKEFLAGS} in its environment. In response, it takes the flags from that value and processes them as if they had been given as arguments. @xref{Options Summary, ,Summary of Options}. @cindex command line variable definitions, and recursion @cindex variables, command line, and recursion @cindex recursion, and command line variable definitions Likewise variables defined on the command line are passed to the sub-@code{make} through @code{MAKEFLAGS}. Words in the value of @code{MAKEFLAGS} that contain @samp{=}, @code{make} treats as variable definitions just as if they appeared on the command line. @xref{Overriding, ,Overriding Variables}. @cindex @code{-C}, and recursion @cindex @code{-f}, and recursion @cindex @code{-o}, and recursion @cindex @code{-W}, and recursion @cindex @code{--directory}, and recursion @cindex @code{--file}, and recursion @cindex @code{--old-file}, and recursion @cindex @code{--assume-old}, and recursion @cindex @code{--assume-new}, and recursion @cindex @code{--new-file}, and recursion @cindex recursion, and @code{-C} @cindex recursion, and @code{-f} @cindex recursion, and @code{-o} @cindex recursion, and @code{-W} The options @samp{-C}, @samp{-f}, @samp{-o}, and @samp{-W} are not put into @code{MAKEFLAGS}; these options are not passed down.@refill @cindex @code{-j}, and recursion @cindex @code{--jobs}, and recursion @cindex recursion, and @code{-j} @cindex job slots, and recursion The @samp{-j} option is a special case (@pxref{Parallel, ,Parallel Execution}). If you set it to some numeric value, @samp{-j 1} is always put into @code{MAKEFLAGS} instead of the value you specified. This is because if the @w{@samp{-j}} option were passed down to sub-@code{make}s, you would get many more jobs running in parallel than you asked for. If you give @samp{-j} with no numeric argument, meaning to run as many jobs as possible in parallel, this is passed down, since multiple infinities are no more than one.@refill If you do not want to pass the other flags down, you must change the value of @code{MAKEFLAGS}, like this: @example subsystem: cd subdir &&$(MAKE) MAKEFLAGS= @end example @vindex MAKEOVERRIDES The command line variable definitions really appear in the variable @code{MAKEOVERRIDES}, and @code{MAKEFLAGS} contains a reference to this variable. If you do want to pass flags down normally, but don't want to pass down the command line variable definitions, you can reset @code{MAKEOVERRIDES} to empty, like this: @example MAKEOVERRIDES = @end example @noindent @cindex Arg list too long @cindex E2BIG This is not usually useful to do. However, some systems have a small fixed limit on the size of the environment, and putting so much information in into the value of @code{MAKEFLAGS} can exceed it. If you see the error message @samp{Arg list too long}, this may be the problem. @findex .POSIX @cindex POSIX.2 (For strict compliance with POSIX.2, changing @code{MAKEOVERRIDES} does not affect @code{MAKEFLAGS} if the special target @samp{.POSIX} appears in the makefile. You probably do not care about this.) @vindex MFLAGS A similar variable @code{MFLAGS} exists also, for historical compatibility. It has the same value as @code{MAKEFLAGS} except that it does not contain the command line variable definitions, and it always begins with a hyphen unless it is empty (@code{MAKEFLAGS} begins with a hyphen only when it begins with an option that has no single-letter version, such as @samp{--warn-undefined-variables}). @code{MFLAGS} was traditionally used explicitly in the recursive @code{make} command, like this: @example subsystem: cd subdir && $(MAKE)$(MFLAGS) @end example @noindent but now @code{MAKEFLAGS} makes this usage redundant. If you want your makefiles to be compatible with old @code{make} programs, use this technique; it will work fine with more modern @code{make} versions too. @cindex setting options from environment @cindex options, setting from environment @cindex setting options in makefiles @cindex options, setting in makefiles The @code{MAKEFLAGS} variable can also be useful if you want to have certain options, such as @samp{-k} (@pxref{Options Summary, ,Summary of Options}), set each time you run @code{make}. You simply put a value for @code{MAKEFLAGS} in your environment. You can also set @code{MAKEFLAGS} in a makefile, to specify additional flags that should also be in effect for that makefile. (Note that you cannot use @code{MFLAGS} this way. That variable is set only for compatibility; @code{make} does not interpret a value you set for it in any way.) When @code{make} interprets the value of @code{MAKEFLAGS} (either from the environment or from a makefile), it first prepends a hyphen if the value does not already begin with one. Then it chops the value into words separated by blanks, and parses these words as if they were options given on the command line (except that @samp{-C}, @samp{-f}, @samp{-h}, @samp{-o}, @samp{-W}, and their long-named versions are ignored; and there is no error for an invalid option). If you do put @code{MAKEFLAGS} in your environment, you should be sure not to include any options that will drastically affect the actions of @code{make} and undermine the purpose of makefiles and of @code{make} itself. For instance, the @samp{-t}, @samp{-n}, and @samp{-q} options, if put in one of these variables, could have disastrous consequences and would certainly have at least surprising and probably annoying effects.@refill @node -w Option, , Options/Recursion, Recursion @subsection The @samp{--print-directory} Option @cindex directories, printing them @cindex printing directories @cindex recursion, and printing directories If you use several levels of recursive @code{make} invocations, the @samp{-w} or @w{@samp{--print-directory}} option can make the output a lot easier to understand by showing each directory as @code{make} starts processing it and as @code{make} finishes processing it. For example, if @samp{make -w} is run in the directory @file{/u/gnu/make}, @code{make} will print a line of the form:@refill @example make: Entering directory /u/gnu/make'. @end example @noindent before doing anything else, and a line of the form: @example make: Leaving directory /u/gnu/make'. @end example @noindent when processing is completed. @cindex @code{-C}, and @code{-w} @cindex @code{--directory}, and @code{--print-directory} @cindex recursion, and @code{-w} @cindex @code{-w}, and @code{-C} @cindex @code{-w}, and recursion @cindex @code{--print-directory}, and @code{--directory} @cindex @code{--print-directory}, and recursion @cindex @code{--no-print-directory} @cindex @code{--print-directory}, disabling @cindex @code{-w}, disabling Normally, you do not need to specify this option because @samp{make} does it for you: @samp{-w} is turned on automatically when you use the @samp{-C} option, and in sub-@code{make}s. @code{make} will not automatically turn on @samp{-w} if you also use @samp{-s}, which says to be silent, or if you use @samp{--no-print-directory} to explicitly disable it. @node Sequences, Empty Commands, Recursion, Commands @section Defining Canned Command Sequences @cindex sequences of commands @cindex commands, sequences of