Initial placement cost = 74.6951

Cost recomputed from scratch is 29.294008.
Final Placement cost: 29.2937


VPR FPGA Placement and Routing Program Version 4.00-spec
Source completed August 19, 1997.


General Options:
	The circuit will be placed but not routed.

Placer Options:
	User annealing schedule selected with:
	Initial Temperature: 5
	Exit (Final) Temperature: 0.005
	Temperature Reduction factor (alpha_t): 0.9412
	Number of moves in the inner loop is (num_blocks)^4/3 * 2
	Placement cost type is linear congestion.
	Placement will be performed once.
	Placement channel width factor = 100.
	Exponent used in placement cost: 1
	Initial random seed: 1

Reading the FPGA architectural description from arch.in.
Successfully read arch.in.
Pins per clb: 6.  Pads per row/column: 2.
Subblocks per clb: 1.  Subblock LUT size: 4.
Fc value is fraction of tracks in a channel.
Fc_output: 1.  Fc_input: 1.  Fc_pad: 1.
Switch block type: Subset.
Distinct types of segments: 3.
Distinct types of user-specified switches: 3.

Reading the circuit netlist from net.in.
Successfully read net.in.
404 blocks, 339 nets, 0 global nets.
274 clbs, 65 inputs, 65 outputs.
The circuit will be mapped into a 17 x 17 array of clbs.


Completed placement consistency check successfully.

Total moves attempted: 686665.0
exit 0