| commit | dc2ed0043295a397d680db091c2033a51d21e32e | [log] [tgz] |
|---|---|---|
| author | Luke Lau <luke@igalia.com> | Fri Sep 05 08:25:48 2025 +0800 |
| committer | GitHub <noreply@github.com> | Fri Sep 05 00:25:48 2025 +0000 |
| tree | 0403d11d1c9e2d3ff2b8c22175605b09b9978027 | |
| parent | 4e5e65e55dc5a5ffc6e3db321df7f118e1c42d38 [diff] |
[RISCV] Handle non uimm5 VL constants in isVLKnownLE (#156639) If a VL operand is > 31 then it will be materialized into an ADDI $x0, imm. We can reason about it by peeking at the virtual register definition which allows RISCVVectorPeephole and RISCVVLOptimizer to catch more cases. There's a separate issue with RISCVVLOptimizer where the materialized immediate may not always dominate the instruction we want to reduce the VL of, but this is left to another patch.
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