llvm/test/CodeGen/X86/peephole-copy.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=i686-- -run-pass=peephole-opt %s -o - | FileCheck %s
--- |
  define void @c() {
  entry:
    tail call void asm sideeffect "", "q,~{dirflag},~{fpsr},~{flags}"(i32 512)
    tail call void asm sideeffect "", "q,~{dirflag},~{fpsr},~{flags}"(i32 512)
    ret void
  }
...
---
# In peephole optimization the modified COPY instruction should not cause
# compiler failure.
name: c
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32_abcd }
  - { id: 1, class: gr32_abcd }
  - { id: 2, class: gr32 }

body: |
  bb.0:
    ; CHECK-LABEL: name: c
    ; CHECK: [[MOV32ri:%[0-9]+]]:gr32_abcd = MOV32ri 512
    ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3211273 /* reguse:GR32_ABCD */, [[MOV32ri]], 1 /* reguse */, implicit-def early-clobber $df
    ; CHECK-NEXT: [[MOV32ri1:%[0-9]+]]:gr32_abcd = MOV32ri 512
    ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3211273 /* reguse:GR32_ABCD */, [[MOV32ri1]], 1 /* reguse */, implicit-def early-clobber $df
    ; CHECK-NEXT: RET 0
    %2 = MOV32ri 512
    %0 = COPY %2
    INLINEASM &"", 1 /* sideeffect attdialect */, 3211273 /* reguse:GR32_ABCD */, %0:gr32_abcd, 1 /* clobber */, implicit-def early-clobber $df
    %1 = COPY %2
    INLINEASM &"", 1 /* sideeffect attdialect */, 3211273 /* reguse:GR32_ABCD */, %1:gr32_abcd, 1 /* clobber */, implicit-def early-clobber $df
    RET 0
...