llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s

---
name: spill_partial_live_csr_sgpr_test
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr50_sgpr51' }
  - { reg: '$sgpr52_sgpr53' }
  - { reg: '$sgpr54_sgpr55' }
body:             |
  bb.0:
    liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55

    ; CHECK-LABEL: name: spill_partial_live_csr_sgpr_test
    ; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
    ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63
    ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63
    ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63
    ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63
    ; CHECK-NEXT: S_NOP 0, implicit $sgpr50
    ; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
    ; CHECK-NEXT: S_NOP 0, implicit $sgpr52
    ; CHECK-NEXT: $sgpr52_sgpr53 = S_MOV_B64 0
    ; CHECK-NEXT: S_NOP 0, implicit $sgpr55
    ; CHECK-NEXT: $sgpr54_sgpr55 = S_MOV_B64 0
    ; CHECK-NEXT: $sgpr56 = S_MOV_B32 0
    S_NOP 0, implicit $sgpr50
    $sgpr50 = S_MOV_B32 0
    S_NOP 0, implicit $sgpr52
    $sgpr52_sgpr53 = S_MOV_B64 0
    S_NOP 0, implicit $sgpr55
    $sgpr54_sgpr55 = S_MOV_B64 0
    $sgpr56 = S_MOV_B32 0
...