llvm/test/CodeGen/RISCV/xqcibm-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32XQCIBM

define i32 @sexti1_i32(i1 %a) nounwind {
; RV32I-LABEL: sexti1_i32:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 31
; RV32I-NEXT:    srai a0, a0, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti1_i32:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 1, 0
; RV32XQCIBM-NEXT:    ret
  %sext = sext i1 %a to i32
  ret i32 %sext
}

define i32 @sexti1_i32_2(i32 %a) {
; RV32I-LABEL: sexti1_i32_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 31
; RV32I-NEXT:    srai a0, a0, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti1_i32_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 1, 0
; RV32XQCIBM-NEXT:    ret
  %shl = shl i32 %a, 31
  %shr = ashr exact i32 %shl, 31
  ret i32 %shr
}


define i32 @sexti8_i32(i8 %a) nounwind {
; RV32I-LABEL: sexti8_i32:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 24
; RV32I-NEXT:    srai a0, a0, 24
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti8_i32:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 8, 0
; RV32XQCIBM-NEXT:    ret
  %sext = sext i8 %a to i32
  ret i32 %sext
}

define i32 @sexti8_i32_2(i32 %a) {
; RV32I-LABEL: sexti8_i32_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 24
; RV32I-NEXT:    srai a0, a0, 24
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti8_i32_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 8, 0
; RV32XQCIBM-NEXT:    ret
  %shl = shl i32 %a, 24
  %shr = ashr exact i32 %shl, 24
  ret i32 %shr
}

define i32 @sexti16_i32(i16 %a) nounwind {
; RV32I-LABEL: sexti16_i32:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 16
; RV32I-NEXT:    srai a0, a0, 16
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti16_i32:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 16, 0
; RV32XQCIBM-NEXT:    ret
  %sext = sext i16 %a to i32
  ret i32 %sext
}

define i32 @sexti16_i32_2(i32 %a) {
; RV32I-LABEL: sexti16_i32_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 16
; RV32I-NEXT:    srai a0, a0, 16
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti16_i32_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 16, 0
; RV32XQCIBM-NEXT:    ret
  %shl = shl i32 %a, 16
  %shr = ashr exact i32 %shl, 16
  ret i32 %shr
}

define i64 @sexti1_i64(i64 %a) {
; RV32I-LABEL: sexti1_i64:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 31
; RV32I-NEXT:    srai a0, a0, 31
; RV32I-NEXT:    mv a1, a0
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti1_i64:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 1, 0
; RV32XQCIBM-NEXT:    mv a1, a0
; RV32XQCIBM-NEXT:    ret
  %shl = shl i64 %a, 63
  %shr = ashr exact i64 %shl, 63
  ret i64 %shr
}

define i64 @sexti1_i64_2(i1 %a) {
; RV32I-LABEL: sexti1_i64_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a0, a0, 31
; RV32I-NEXT:    srai a0, a0, 31
; RV32I-NEXT:    mv a1, a0
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti1_i64_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 1, 0
; RV32XQCIBM-NEXT:    mv a1, a0
; RV32XQCIBM-NEXT:    ret
  %1 = sext i1 %a to i64
  ret i64 %1
}

define i64 @sexti8_i64(i64 %a) {
; RV32I-LABEL: sexti8_i64:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a1, a0, 24
; RV32I-NEXT:    srai a0, a1, 24
; RV32I-NEXT:    srai a1, a1, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti8_i64:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 8, 0
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %shl = shl i64 %a, 56
  %shr = ashr exact i64 %shl, 56
  ret i64 %shr
}

define i64 @sexti8_i64_2(i8 %a) {
; RV32I-LABEL: sexti8_i64_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a1, a0, 24
; RV32I-NEXT:    srai a0, a1, 24
; RV32I-NEXT:    srai a1, a1, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti8_i64_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 8, 0
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %1 = sext i8 %a to i64
  ret i64 %1
}

define i64 @sexti16_i64(i64 %a) {
; RV32I-LABEL: sexti16_i64:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a1, a0, 16
; RV32I-NEXT:    srai a0, a1, 16
; RV32I-NEXT:    srai a1, a1, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti16_i64:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 16, 0
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %shl = shl i64 %a, 48
  %shr = ashr exact i64 %shl, 48
  ret i64 %shr
}

define i64 @sexti16_i64_2(i16 %a) {
; RV32I-LABEL: sexti16_i64_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a1, a0, 16
; RV32I-NEXT:    srai a0, a1, 16
; RV32I-NEXT:    srai a1, a1, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti16_i64_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    qc.ext a0, a0, 16, 0
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %1 = sext i16 %a to i64
  ret i64 %1
}

define i64 @sexti32_i64(i64 %a) {
; RV32I-LABEL: sexti32_i64:
; RV32I:       # %bb.0:
; RV32I-NEXT:    srai a1, a0, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti32_i64:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %shl = shl i64 %a, 32
  %shr = ashr exact i64 %shl, 32
  ret i64 %shr
}

define i64 @sexti32_i64_2(i32 %a) {
; RV32I-LABEL: sexti32_i64_2:
; RV32I:       # %bb.0:
; RV32I-NEXT:    srai a1, a0, 31
; RV32I-NEXT:    ret
;
; RV32XQCIBM-LABEL: sexti32_i64_2:
; RV32XQCIBM:       # %bb.0:
; RV32XQCIBM-NEXT:    srai a1, a0, 31
; RV32XQCIBM-NEXT:    ret
  %1 = sext i32 %a to i64
  ret i64 %1
}