Google Git
Sign in
fuchsia / third_party / llvm-project / 0d19efa9d5d872962a0a83c865b4636d58f46519 / . / llvm / test / CodeGen / AMDGPU / amdgcn.bitcast.256bit.ll
blob: 6e7b5dd33ea0bade595190f69701980eb74a8ace [file] [log] [blame]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
define <8 x float> @bitcast_v8i32_to_v8f32(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB0_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: .LBB0_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB0_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <8 x i32> @bitcast_v8f32_to_v8i32(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB1_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6
; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4
; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2
; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
; GCN-NEXT: .LBB1_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <4 x i64> @bitcast_v8i32_to_v4i64(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB2_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: .LBB2_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB2_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <8 x i32> @bitcast_v4i64_to_v8i32(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB3_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: .LBB3_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB3_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB3_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <4 x double> @bitcast_v8i32_to_v4f64(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB4_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: .LBB4_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <8 x i32> @bitcast_v4f64_to_v8i32(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB5_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: .LBB5_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB5_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB5_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB5_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB5_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB5_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB5_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <16 x i16> @bitcast_v8i32_to_v16i16(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v14, v7
; GCN-NEXT: v_mov_b32_e32 v12, v6
; GCN-NEXT: v_mov_b32_e32 v10, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v6, v3
; GCN-NEXT: v_mov_b32_e32 v4, v2
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB6_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB6_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB6_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB6_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v16
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB6_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v20, v6
; GCN-NEXT: v_mov_b32_e32 v19, v4
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB7_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB7_4
; GCN-NEXT: .LBB7_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB7_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v18
; GCN-NEXT: v_or_b32_e32 v0, v0, v22
; GCN-NEXT: v_or_b32_e32 v1, v1, v23
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v19
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v20
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v2, v2, v16
; GCN-NEXT: v_or_b32_e32 v3, v3, v21
; GCN-NEXT: v_or_b32_e32 v4, v4, v9
; GCN-NEXT: v_or_b32_e32 v5, v5, v11
; GCN-NEXT: v_or_b32_e32 v6, v6, v13
; GCN-NEXT: v_or_b32_e32 v7, v7, v15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB7_2
; GCN-NEXT: .LBB7_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v17
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v0, v22, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_or_b32_e32 v2, v16, v2
; GCN-NEXT: v_or_b32_e32 v3, v21, v3
; GCN-NEXT: v_or_b32_e32 v4, v9, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v13, v6
; GCN-NEXT: v_or_b32_e32 v7, v15, v7
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB7_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
; VI-NEXT: v_add_u16_e32 v8, 3, v7
; VI-NEXT: v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_u16_e32 v8, 3, v6
; VI-NEXT: v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 3, v5
; VI-NEXT: v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 3, v4
; VI-NEXT: v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 3, v3
; VI-NEXT: v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 3, v1
; VI-NEXT: v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v8, v1
; VI-NEXT: v_add_u16_e32 v8, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB7_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB7_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB7_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <16 x half> @bitcast_v8i32_to_v16f16(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v17, v7
; GCN-NEXT: v_mov_b32_e32 v18, v6
; GCN-NEXT: v_mov_b32_e32 v19, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v21, v3
; GCN-NEXT: v_mov_b32_e32 v22, v2
; GCN-NEXT: v_mov_b32_e32 v23, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB8_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB8_4
; GCN-NEXT: .LBB8_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB8_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v18
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB8_2
; GCN-NEXT: .LBB8_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v23
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v21
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v17
; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <8 x i32> @bitcast_v16f16_to_v8i32(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v26, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v25, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v24, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB9_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB9_4
; GCN-NEXT: .LBB9_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB9_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v24
; GCN-NEXT: v_or_b32_e32 v0, v25, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v19, v2
; GCN-NEXT: v_or_b32_e32 v3, v17, v3
; GCN-NEXT: v_or_b32_e32 v4, v16, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v9, v6
; GCN-NEXT: v_or_b32_e32 v7, v8, v7
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB9_2
; GCN-NEXT: .LBB9_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v3, v2
; GCN-NEXT: v_or_b32_e32 v3, v5, v4
; GCN-NEXT: v_or_b32_e32 v4, v7, v6
; GCN-NEXT: v_or_b32_e32 v5, v11, v12
; GCN-NEXT: v_or_b32_e32 v6, v9, v13
; GCN-NEXT: v_or_b32_e32 v7, v8, v10
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB9_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 0x200
; VI-NEXT: v_add_f16_sdwa v9, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_f16_sdwa v9, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v6, v6, v9
; VI-NEXT: v_add_f16_sdwa v9, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_or_b32_e32 v5, v5, v9
; VI-NEXT: v_add_f16_sdwa v9, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_or_b32_e32 v4, v4, v9
; VI-NEXT: v_add_f16_sdwa v9, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_add_f16_sdwa v9, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_add_f16_sdwa v9, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v8, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v0, v8
; VI-NEXT: .LBB9_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB9_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB9_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <16 x bfloat> @bitcast_v8i32_to_v16bf16(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v23, v7
; GCN-NEXT: v_mov_b32_e32 v22, v6
; GCN-NEXT: v_mov_b32_e32 v21, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v19, v3
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB10_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB10_4
; GCN-NEXT: .LBB10_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB10_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v23
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v23
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v21
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v20
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v20
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v18
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB10_2
; GCN-NEXT: .LBB10_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v21
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v23
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB10_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v15
; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB11_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB11_4
; GCN-NEXT: .LBB11_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB11_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v23
; GCN-NEXT: v_alignbit_b32 v0, v0, v26, 16
; GCN-NEXT: v_alignbit_b32 v1, v1, v24, 16
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v2, v20, 16
; GCN-NEXT: v_alignbit_b32 v3, v3, v18, 16
; GCN-NEXT: v_alignbit_b32 v4, v4, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v5, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v6, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v7, v8, 16
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB11_2
; GCN-NEXT: .LBB11_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v3, v5, v4, 16
; GCN-NEXT: v_alignbit_b32 v4, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v5, v12, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v13, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v9, v8, 16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB11_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_alignbit_b32 v6, v6, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_alignbit_b32 v5, v5, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_alignbit_b32 v4, v4, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v3, v3, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_alignbit_b32 v2, v2, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_alignbit_b32 v1, v1, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB11_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB11_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v7, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v6, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v6, v6, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v5, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v5, v5, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v4, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v4, v4, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v3, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v3, v3, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v2, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v2, v2, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v1, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v1, v1, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s7
; GFX9-NEXT: .LBB11_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB11_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v6
; GFX11-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v9
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v3
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GFX11-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v11
; GFX11-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
; GFX11-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
; GFX11-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-NEXT: .LBB11_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <32 x i8> @bitcast_v8i32_to_v32i8(<8 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v8i32_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v28, v7
; GCN-NEXT: v_mov_b32_e32 v24, v6
; GCN-NEXT: v_mov_b32_e32 v20, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v12, v3
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v4, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB12_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB12_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB12_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v32, vcc, 3, v32
; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB12_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v32
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8i32_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v5
; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: .LBB12_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_add_u32_e32 v35, vcc, 3, v35
; VI-NEXT: v_add_u32_e32 v34, vcc, 3, v34
; VI-NEXT: v_add_u32_e32 v33, vcc, 3, v33
; VI-NEXT: v_add_u32_e32 v32, vcc, 3, v32
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB12_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v34
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v16, v32
; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v37
; VI-NEXT: v_mov_b32_e32 v7, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8i32_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB12_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_add_u32_e32 v35, 3, v35
; GFX9-NEXT: v_add_u32_e32 v34, 3, v34
; GFX9-NEXT: v_add_u32_e32 v33, 3, v33
; GFX9-NEXT: v_add_u32_e32 v32, 3, v32
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB12_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8i32_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB12_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB12_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB12_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v39, 3, v39
; GFX11-NEXT: v_add_nc_u32_e32 v37, 3, v37
; GFX11-NEXT: v_add_nc_u32_e32 v35, 3, v35
; GFX11-NEXT: v_add_nc_u32_e32 v33, 3, v33
; GFX11-NEXT: v_add_nc_u32_e32 v32, 3, v32
; GFX11-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-NEXT: v_add_nc_u32_e32 v38, 3, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB12_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <8 x i32> %a, splat (i32 3)
%a2 = bitcast <8 x i32> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <8 x i32> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v8i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v34, v6
; GCN-NEXT: v_mov_b32_e32 v33, v4
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v31, v0
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v37, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v35, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v38, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v39, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v23, 8, v25
; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v25, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 24, v0
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB13_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB13_4
; GCN-NEXT: .LBB13_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB13_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v32
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v33
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v34
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v24
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v30
; GCN-NEXT: v_or_b32_e32 v0, v0, v37
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v2, v38
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v4, v39
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v6, v48
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v8, v49
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v12, v21
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v16, v23
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v20, v25
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_or_b32_e32 v1, v2, v3
; GCN-NEXT: v_or_b32_e32 v2, v4, v5
; GCN-NEXT: v_or_b32_e32 v3, v6, v7
; GCN-NEXT: v_or_b32_e32 v4, v8, v9
; GCN-NEXT: v_or_b32_e32 v5, v10, v11
; GCN-NEXT: v_or_b32_e32 v6, v12, v13
; GCN-NEXT: v_or_b32_e32 v7, v14, v15
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB13_2
; GCN-NEXT: .LBB13_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v30
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v22
; GCN-NEXT: v_or_b32_e32 v0, v37, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v38, v2
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v39, v4
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v48, v6
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v49, v8
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v21, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v23, v16
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v25, v20
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x300, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_or_b32_e32 v2, v5, v4
; GCN-NEXT: v_or_b32_e32 v3, v7, v6
; GCN-NEXT: v_or_b32_e32 v4, v9, v8
; GCN-NEXT: v_or_b32_e32 v5, v11, v10
; GCN-NEXT: v_or_b32_e32 v6, v13, v12
; GCN-NEXT: v_or_b32_e32 v7, v15, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v8i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v32, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v34, v6
; VI-NEXT: v_mov_b32_e32 v33, v4
; VI-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB13_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB13_4
; VI-NEXT: .LBB13_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB13_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB13_2
; VI-NEXT: .LBB13_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v31
; VI-NEXT: v_add_u16_e32 v1, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v7, 0x300
; VI-NEXT: v_add_u16_e32 v2, 3, v33
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v50, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 0x300, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v34
; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v8
; VI-NEXT: v_add_u16_e32 v3, 3, v10
; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v12
; VI-NEXT: v_add_u16_e32 v4, 3, v14
; VI-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v16
; VI-NEXT: v_add_u16_e32 v5, 3, v18
; VI-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v20
; VI-NEXT: v_add_u16_e32 v6, 3, v22
; VI-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
; VI-NEXT: v_add_u16_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v24
; VI-NEXT: v_add_u16_e32 v8, 3, v26
; VI-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v8, v13, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
; VI-NEXT: v_add_u16_sdwa v8, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v28
; VI-NEXT: v_add_u16_e32 v10, 3, v30
; VI-NEXT: v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_add_u16_sdwa v7, v9, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v8i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v31, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v33, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB13_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB13_4
; GFX9-NEXT: .LBB13_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB13_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB13_2
; GFX9-NEXT: .LBB13_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_add_u16_e32 v1, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u16_e32 v1, 3, v33
; GFX9-NEXT: v_add_u16_e32 v2, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v1, v50, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_add_u16_e32 v3, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_add_u16_e32 v4, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_add_u16_e32 v7, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_add_u16_e32 v8, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v8i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
; GFX11-NEXT: v_lshlrev_b16 v51, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v50, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB13_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB13_4
; GFX11-NEXT: .LBB13_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB13_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v51
; GFX11-NEXT: v_or_b32_e32 v1, v1, v49
; GFX11-NEXT: v_or_b32_e32 v2, v2, v50
; GFX11-NEXT: v_or_b32_e32 v3, v3, v48
; GFX11-NEXT: v_or_b32_e32 v4, v4, v38
; GFX11-NEXT: v_or_b32_e32 v5, v5, v39
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v24
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v35
; GFX11-NEXT: v_or_b32_e32 v4, v4, v36
; GFX11-NEXT: v_or_b32_e32 v5, v5, v37
; GFX11-NEXT: v_or_b32_e32 v6, v6, v19
; GFX11-NEXT: v_or_b32_e32 v7, v7, v21
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_or_b32_e32 v9, v10, v11
; GFX11-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-NEXT: v_or_b32_e32 v12, v16, v17
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr51
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr50
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB13_2
; GFX11-NEXT: .LBB13_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v31, 3
; GFX11-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-NEXT: v_add_nc_u16 v2, v33, 3
; GFX11-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-NEXT: v_add_nc_u16 v4, v8, 3
; GFX11-NEXT: v_add_nc_u16 v5, v10, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v0, v51, v0
; GFX11-NEXT: v_or_b32_e32 v1, v49, v1
; GFX11-NEXT: v_or_b32_e32 v2, v50, v2
; GFX11-NEXT: v_or_b32_e32 v3, v48, v3
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v5, v39, v5
; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_add_nc_u16 v6, v18, 3
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_add_nc_u16 v3, v12, 3
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_add_nc_u16 v5, v16, 3
; GFX11-NEXT: v_add_nc_u16 v7, v20, 3
; GFX11-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-NEXT: v_add_nc_u16 v10, v24, 3
; GFX11-NEXT: v_add_nc_u16 v12, v26, 3
; GFX11-NEXT: v_add_nc_u16 v14, v28, 3
; GFX11-NEXT: v_add_nc_u16 v16, v30, 3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v16
; GFX11-NEXT: v_or_b32_e32 v3, v35, v3
; GFX11-NEXT: v_or_b32_e32 v4, v36, v4
; GFX11-NEXT: v_or_b32_e32 v5, v37, v5
; GFX11-NEXT: v_or_b32_e32 v6, v19, v6
; GFX11-NEXT: v_or_b32_e32 v7, v21, v7
; GFX11-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-NEXT: v_or_b32_e32 v10, v13, v12
; GFX11-NEXT: v_or_b32_e32 v11, v15, v14
; GFX11-NEXT: v_or_b32_e32 v12, v17, v16
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v10
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <8 x i32>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <8 x i32>
br label %end
end:
%phi = phi <8 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x i32> %phi
}
define <4 x i64> @bitcast_v8f32_to_v4i64(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB14_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6
; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4
; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2
; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
; GCN-NEXT: .LBB14_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <8 x float> @bitcast_v4i64_to_v8f32(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB15_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: .LBB15_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB15_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB15_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <4 x double> @bitcast_v8f32_to_v4f64(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB16_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6
; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4
; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2
; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
; GCN-NEXT: .LBB16_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <8 x float> @bitcast_v4f64_to_v8f32(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB17_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: .LBB17_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB17_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB17_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB17_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB17_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB17_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB17_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <16 x i16> @bitcast_v8f32_to_v16i16(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v14, v7
; GCN-NEXT: v_mov_b32_e32 v12, v6
; GCN-NEXT: v_mov_b32_e32 v10, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v6, v3
; GCN-NEXT: v_mov_b32_e32 v4, v2
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB18_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB18_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB18_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4
; GCN-NEXT: v_add_f32_e32 v10, 1.0, v10
; GCN-NEXT: v_add_f32_e32 v16, 1.0, v16
; GCN-NEXT: v_add_f32_e32 v14, 1.0, v14
; GCN-NEXT: v_add_f32_e32 v12, 1.0, v12
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB18_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v16
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v20, v6
; GCN-NEXT: v_mov_b32_e32 v19, v4
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB19_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB19_4
; GCN-NEXT: .LBB19_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB19_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v18
; GCN-NEXT: v_or_b32_e32 v0, v0, v22
; GCN-NEXT: v_or_b32_e32 v1, v1, v23
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v19
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v20
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v2, v2, v16
; GCN-NEXT: v_or_b32_e32 v3, v3, v21
; GCN-NEXT: v_or_b32_e32 v4, v4, v9
; GCN-NEXT: v_or_b32_e32 v5, v5, v11
; GCN-NEXT: v_or_b32_e32 v6, v6, v13
; GCN-NEXT: v_or_b32_e32 v7, v7, v15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB19_2
; GCN-NEXT: .LBB19_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v17
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v0, v22, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_or_b32_e32 v2, v16, v2
; GCN-NEXT: v_or_b32_e32 v3, v21, v3
; GCN-NEXT: v_or_b32_e32 v4, v9, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v13, v6
; GCN-NEXT: v_or_b32_e32 v7, v15, v7
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB19_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
; VI-NEXT: v_add_u16_e32 v8, 3, v7
; VI-NEXT: v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_u16_e32 v8, 3, v6
; VI-NEXT: v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 3, v5
; VI-NEXT: v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 3, v4
; VI-NEXT: v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 3, v3
; VI-NEXT: v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 3, v1
; VI-NEXT: v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v8, v1
; VI-NEXT: v_add_u16_e32 v8, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB19_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB19_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB19_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <16 x half> @bitcast_v8f32_to_v16f16(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v17, v7
; GCN-NEXT: v_mov_b32_e32 v18, v6
; GCN-NEXT: v_mov_b32_e32 v19, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v21, v3
; GCN-NEXT: v_mov_b32_e32 v22, v2
; GCN-NEXT: v_mov_b32_e32 v23, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB20_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB20_4
; GCN-NEXT: .LBB20_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB20_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v18
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB20_2
; GCN-NEXT: .LBB20_4: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v16
; GCN-NEXT: v_add_f32_e32 v1, 1.0, v23
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v22
; GCN-NEXT: v_add_f32_e32 v3, 1.0, v21
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v20
; GCN-NEXT: v_add_f32_e32 v5, 1.0, v19
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v18
; GCN-NEXT: v_add_f32_e32 v7, 1.0, v17
; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <8 x float> @bitcast_v16f16_to_v8f32(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v26, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v25, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v24, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB21_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB21_4
; GCN-NEXT: .LBB21_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB21_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v24
; GCN-NEXT: v_or_b32_e32 v0, v25, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v19, v2
; GCN-NEXT: v_or_b32_e32 v3, v17, v3
; GCN-NEXT: v_or_b32_e32 v4, v16, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v9, v6
; GCN-NEXT: v_or_b32_e32 v7, v8, v7
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB21_2
; GCN-NEXT: .LBB21_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v3, v2
; GCN-NEXT: v_or_b32_e32 v3, v5, v4
; GCN-NEXT: v_or_b32_e32 v4, v7, v6
; GCN-NEXT: v_or_b32_e32 v5, v11, v12
; GCN-NEXT: v_or_b32_e32 v6, v9, v13
; GCN-NEXT: v_or_b32_e32 v7, v8, v10
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB21_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 0x200
; VI-NEXT: v_add_f16_sdwa v9, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_f16_sdwa v9, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v6, v6, v9
; VI-NEXT: v_add_f16_sdwa v9, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_or_b32_e32 v5, v5, v9
; VI-NEXT: v_add_f16_sdwa v9, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_or_b32_e32 v4, v4, v9
; VI-NEXT: v_add_f16_sdwa v9, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_add_f16_sdwa v9, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_add_f16_sdwa v9, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v8, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v0, v8
; VI-NEXT: .LBB21_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB21_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB21_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <16 x bfloat> @bitcast_v8f32_to_v16bf16(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v23, v7
; GCN-NEXT: v_mov_b32_e32 v22, v6
; GCN-NEXT: v_mov_b32_e32 v21, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v19, v3
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB22_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB22_4
; GCN-NEXT: .LBB22_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB22_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v23
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v23
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v21
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v20
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v20
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v18
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB22_2
; GCN-NEXT: .LBB22_4: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v16
; GCN-NEXT: v_add_f32_e32 v1, 1.0, v17
; GCN-NEXT: v_add_f32_e32 v2, 1.0, v18
; GCN-NEXT: v_add_f32_e32 v3, 1.0, v19
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v20
; GCN-NEXT: v_add_f32_e32 v5, 1.0, v21
; GCN-NEXT: v_add_f32_e32 v6, 1.0, v22
; GCN-NEXT: v_add_f32_e32 v7, 1.0, v23
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v15
; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB23_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB23_4
; GCN-NEXT: .LBB23_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB23_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v23
; GCN-NEXT: v_alignbit_b32 v0, v0, v26, 16
; GCN-NEXT: v_alignbit_b32 v1, v1, v24, 16
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v2, v20, 16
; GCN-NEXT: v_alignbit_b32 v3, v3, v18, 16
; GCN-NEXT: v_alignbit_b32 v4, v4, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v5, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v6, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v7, v8, 16
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB23_2
; GCN-NEXT: .LBB23_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v3, v5, v4, 16
; GCN-NEXT: v_alignbit_b32 v4, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v5, v12, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v13, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v9, v8, 16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB23_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_alignbit_b32 v6, v6, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_alignbit_b32 v5, v5, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_alignbit_b32 v4, v4, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v3, v3, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_alignbit_b32 v2, v2, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_alignbit_b32 v1, v1, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB23_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB23_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v7, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v6, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v6, v6, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v5, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v5, v5, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v4, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v4, v4, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v3, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v3, v3, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v2, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v2, v2, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v1, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v1, v1, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s7
; GFX9-NEXT: .LBB23_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB23_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v6
; GFX11-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v9
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v3
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GFX11-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v11
; GFX11-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
; GFX11-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
; GFX11-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-NEXT: .LBB23_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <32 x i8> @bitcast_v8f32_to_v32i8(<8 x float> %a, i32 %b) {
; GCN-LABEL: bitcast_v8f32_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v28, v7
; GCN-NEXT: v_mov_b32_e32 v24, v6
; GCN-NEXT: v_mov_b32_e32 v20, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v12, v3
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v4, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB24_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB24_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB24_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4
; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_add_f32_e32 v12, 1.0, v12
; GCN-NEXT: v_add_f32_e32 v32, 1.0, v32
; GCN-NEXT: v_add_f32_e32 v20, 1.0, v20
; GCN-NEXT: v_add_f32_e32 v16, 1.0, v16
; GCN-NEXT: v_add_f32_e32 v28, 1.0, v28
; GCN-NEXT: v_add_f32_e32 v24, 1.0, v24
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB24_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v32
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v8f32_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v5
; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB24_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: .LBB24_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB24_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: v_add_f32_e32 v35, 1.0, v35
; VI-NEXT: v_add_f32_e32 v34, 1.0, v34
; VI-NEXT: v_add_f32_e32 v33, 1.0, v33
; VI-NEXT: v_add_f32_e32 v32, 1.0, v32
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB24_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v34
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v16, v32
; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v37
; VI-NEXT: v_mov_b32_e32 v7, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v8f32_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB24_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB24_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB24_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: v_add_f32_e32 v35, 1.0, v35
; GFX9-NEXT: v_add_f32_e32 v34, 1.0, v34
; GFX9-NEXT: v_add_f32_e32 v33, 1.0, v33
; GFX9-NEXT: v_add_f32_e32 v32, 1.0, v32
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB24_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v8f32_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB24_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v39, 1.0, v39 :: v_dual_add_f32 v32, 1.0, v32
; GFX11-NEXT: v_dual_add_f32 v37, 1.0, v37 :: v_dual_add_f32 v34, 1.0, v34
; GFX11-NEXT: v_dual_add_f32 v35, 1.0, v35 :: v_dual_add_f32 v36, 1.0, v36
; GFX11-NEXT: v_dual_add_f32 v33, 1.0, v33 :: v_dual_add_f32 v38, 1.0, v38
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB24_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <8 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <8 x float> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <8 x float> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v8f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v34, v6
; GCN-NEXT: v_mov_b32_e32 v33, v4
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v31, v0
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v37, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v35, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v38, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v39, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v23, 8, v25
; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v25, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 24, v0
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB25_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB25_4
; GCN-NEXT: .LBB25_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB25_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v32
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v33
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v34
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v24
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v30
; GCN-NEXT: v_or_b32_e32 v0, v0, v37
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v2, v38
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v4, v39
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v6, v48
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v8, v49
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v12, v21
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v16, v23
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v20, v25
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_or_b32_e32 v1, v2, v3
; GCN-NEXT: v_or_b32_e32 v2, v4, v5
; GCN-NEXT: v_or_b32_e32 v3, v6, v7
; GCN-NEXT: v_or_b32_e32 v4, v8, v9
; GCN-NEXT: v_or_b32_e32 v5, v10, v11
; GCN-NEXT: v_or_b32_e32 v6, v12, v13
; GCN-NEXT: v_or_b32_e32 v7, v14, v15
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB25_2
; GCN-NEXT: .LBB25_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v30
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v22
; GCN-NEXT: v_or_b32_e32 v0, v37, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v38, v2
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v39, v4
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v48, v6
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v49, v8
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v21, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v23, v16
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v25, v20
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x300, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_or_b32_e32 v2, v5, v4
; GCN-NEXT: v_or_b32_e32 v3, v7, v6
; GCN-NEXT: v_or_b32_e32 v4, v9, v8
; GCN-NEXT: v_or_b32_e32 v5, v11, v10
; GCN-NEXT: v_or_b32_e32 v6, v13, v12
; GCN-NEXT: v_or_b32_e32 v7, v15, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v8f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v32, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v34, v6
; VI-NEXT: v_mov_b32_e32 v33, v4
; VI-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB25_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB25_4
; VI-NEXT: .LBB25_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB25_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB25_2
; VI-NEXT: .LBB25_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v31
; VI-NEXT: v_add_u16_e32 v1, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v7, 0x300
; VI-NEXT: v_add_u16_e32 v2, 3, v33
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v50, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 0x300, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v34
; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v8
; VI-NEXT: v_add_u16_e32 v3, 3, v10
; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v12
; VI-NEXT: v_add_u16_e32 v4, 3, v14
; VI-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v16
; VI-NEXT: v_add_u16_e32 v5, 3, v18
; VI-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v20
; VI-NEXT: v_add_u16_e32 v6, 3, v22
; VI-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
; VI-NEXT: v_add_u16_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v24
; VI-NEXT: v_add_u16_e32 v8, 3, v26
; VI-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v8, v13, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
; VI-NEXT: v_add_u16_sdwa v8, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v28
; VI-NEXT: v_add_u16_e32 v10, 3, v30
; VI-NEXT: v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_add_u16_sdwa v7, v9, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v8f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v31, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v33, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB25_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB25_4
; GFX9-NEXT: .LBB25_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB25_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB25_2
; GFX9-NEXT: .LBB25_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_add_u16_e32 v1, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u16_e32 v1, 3, v33
; GFX9-NEXT: v_add_u16_e32 v2, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v1, v50, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_add_u16_e32 v3, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_add_u16_e32 v4, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_add_u16_e32 v7, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_add_u16_e32 v8, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v8f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
; GFX11-NEXT: v_lshlrev_b16 v51, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v50, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB25_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB25_4
; GFX11-NEXT: .LBB25_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB25_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v51
; GFX11-NEXT: v_or_b32_e32 v1, v1, v49
; GFX11-NEXT: v_or_b32_e32 v2, v2, v50
; GFX11-NEXT: v_or_b32_e32 v3, v3, v48
; GFX11-NEXT: v_or_b32_e32 v4, v4, v38
; GFX11-NEXT: v_or_b32_e32 v5, v5, v39
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v24
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v35
; GFX11-NEXT: v_or_b32_e32 v4, v4, v36
; GFX11-NEXT: v_or_b32_e32 v5, v5, v37
; GFX11-NEXT: v_or_b32_e32 v6, v6, v19
; GFX11-NEXT: v_or_b32_e32 v7, v7, v21
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_or_b32_e32 v9, v10, v11
; GFX11-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-NEXT: v_or_b32_e32 v12, v16, v17
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr51
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr50
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB25_2
; GFX11-NEXT: .LBB25_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v31, 3
; GFX11-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-NEXT: v_add_nc_u16 v2, v33, 3
; GFX11-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-NEXT: v_add_nc_u16 v4, v8, 3
; GFX11-NEXT: v_add_nc_u16 v5, v10, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v0, v51, v0
; GFX11-NEXT: v_or_b32_e32 v1, v49, v1
; GFX11-NEXT: v_or_b32_e32 v2, v50, v2
; GFX11-NEXT: v_or_b32_e32 v3, v48, v3
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v5, v39, v5
; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_add_nc_u16 v6, v18, 3
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_add_nc_u16 v3, v12, 3
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_add_nc_u16 v5, v16, 3
; GFX11-NEXT: v_add_nc_u16 v7, v20, 3
; GFX11-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-NEXT: v_add_nc_u16 v10, v24, 3
; GFX11-NEXT: v_add_nc_u16 v12, v26, 3
; GFX11-NEXT: v_add_nc_u16 v14, v28, 3
; GFX11-NEXT: v_add_nc_u16 v16, v30, 3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v16
; GFX11-NEXT: v_or_b32_e32 v3, v35, v3
; GFX11-NEXT: v_or_b32_e32 v4, v36, v4
; GFX11-NEXT: v_or_b32_e32 v5, v37, v5
; GFX11-NEXT: v_or_b32_e32 v6, v19, v6
; GFX11-NEXT: v_or_b32_e32 v7, v21, v7
; GFX11-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-NEXT: v_or_b32_e32 v10, v13, v12
; GFX11-NEXT: v_or_b32_e32 v11, v15, v14
; GFX11-NEXT: v_or_b32_e32 v12, v17, v16
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v10
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <8 x float>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <8 x float>
br label %end
end:
%phi = phi <8 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <8 x float> %phi
}
define <4 x double> @bitcast_v4i64_to_v4f64(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB26_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-NEXT: .LBB26_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB26_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <4 x i64> @bitcast_v4f64_to_v4i64(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB27_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: .LBB27_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB27_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: .LBB27_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB27_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: .LBB27_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB27_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: .LBB27_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <16 x i16> @bitcast_v4i64_to_v16i16(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v14, v7
; GCN-NEXT: v_mov_b32_e32 v12, v6
; GCN-NEXT: v_mov_b32_e32 v10, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v6, v3
; GCN-NEXT: v_mov_b32_e32 v4, v2
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB28_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB28_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB28_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc
; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-NEXT: .LBB28_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v16
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB28_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB28_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v20, v6
; GCN-NEXT: v_mov_b32_e32 v19, v4
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB29_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB29_4
; GCN-NEXT: .LBB29_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB29_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v18
; GCN-NEXT: v_or_b32_e32 v0, v0, v22
; GCN-NEXT: v_or_b32_e32 v1, v1, v23
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v19
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v20
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v2, v2, v16
; GCN-NEXT: v_or_b32_e32 v3, v3, v21
; GCN-NEXT: v_or_b32_e32 v4, v4, v9
; GCN-NEXT: v_or_b32_e32 v5, v5, v11
; GCN-NEXT: v_or_b32_e32 v6, v6, v13
; GCN-NEXT: v_or_b32_e32 v7, v7, v15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB29_2
; GCN-NEXT: .LBB29_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v17
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v0, v22, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_or_b32_e32 v2, v16, v2
; GCN-NEXT: v_or_b32_e32 v3, v21, v3
; GCN-NEXT: v_or_b32_e32 v4, v9, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v13, v6
; GCN-NEXT: v_or_b32_e32 v7, v15, v7
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB29_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
; VI-NEXT: v_add_u16_e32 v8, 3, v7
; VI-NEXT: v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_u16_e32 v8, 3, v6
; VI-NEXT: v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 3, v5
; VI-NEXT: v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 3, v4
; VI-NEXT: v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 3, v3
; VI-NEXT: v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 3, v1
; VI-NEXT: v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v8, v1
; VI-NEXT: v_add_u16_e32 v8, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB29_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB29_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB29_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <16 x half> @bitcast_v4i64_to_v16f16(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v18, v7
; GCN-NEXT: v_mov_b32_e32 v17, v6
; GCN-NEXT: v_mov_b32_e32 v20, v5
; GCN-NEXT: v_mov_b32_e32 v19, v4
; GCN-NEXT: v_mov_b32_e32 v22, v3
; GCN-NEXT: v_mov_b32_e32 v21, v2
; GCN-NEXT: v_mov_b32_e32 v23, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB30_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB30_4
; GCN-NEXT: .LBB30_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB30_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v18
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB30_2
; GCN-NEXT: .LBB30_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v23, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v21
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v22, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v19
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v20, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v17
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v18, vcc
; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB30_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB30_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <4 x i64> @bitcast_v16f16_to_v4i64(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v26, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v25, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v24, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB31_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB31_4
; GCN-NEXT: .LBB31_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB31_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v24
; GCN-NEXT: v_or_b32_e32 v0, v25, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v19, v2
; GCN-NEXT: v_or_b32_e32 v3, v17, v3
; GCN-NEXT: v_or_b32_e32 v4, v16, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v9, v6
; GCN-NEXT: v_or_b32_e32 v7, v8, v7
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB31_2
; GCN-NEXT: .LBB31_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v3, v2
; GCN-NEXT: v_or_b32_e32 v3, v5, v4
; GCN-NEXT: v_or_b32_e32 v4, v7, v6
; GCN-NEXT: v_or_b32_e32 v5, v11, v12
; GCN-NEXT: v_or_b32_e32 v6, v9, v13
; GCN-NEXT: v_or_b32_e32 v7, v8, v10
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB31_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 0x200
; VI-NEXT: v_add_f16_sdwa v9, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_f16_sdwa v9, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v6, v6, v9
; VI-NEXT: v_add_f16_sdwa v9, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_or_b32_e32 v5, v5, v9
; VI-NEXT: v_add_f16_sdwa v9, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_or_b32_e32 v4, v4, v9
; VI-NEXT: v_add_f16_sdwa v9, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_add_f16_sdwa v9, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_add_f16_sdwa v9, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v8, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v0, v8
; VI-NEXT: .LBB31_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB31_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB31_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <16 x bfloat> @bitcast_v4i64_to_v16bf16(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v23, v7
; GCN-NEXT: v_mov_b32_e32 v22, v6
; GCN-NEXT: v_mov_b32_e32 v21, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v19, v3
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v1
; GCN-NEXT: v_mov_b32_e32 v16, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB32_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB32_4
; GCN-NEXT: .LBB32_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB32_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v23
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v23
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v21
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v20
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v20
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v18
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB32_2
; GCN-NEXT: .LBB32_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v17, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v18
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v19, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v20
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v21, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v22
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v23, vcc
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: ; %bb.2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB32_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB32_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v15
; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB33_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB33_4
; GCN-NEXT: .LBB33_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB33_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v23
; GCN-NEXT: v_alignbit_b32 v0, v0, v26, 16
; GCN-NEXT: v_alignbit_b32 v1, v1, v24, 16
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v2, v20, 16
; GCN-NEXT: v_alignbit_b32 v3, v3, v18, 16
; GCN-NEXT: v_alignbit_b32 v4, v4, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v5, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v6, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v7, v8, 16
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB33_2
; GCN-NEXT: .LBB33_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v3, v5, v4, 16
; GCN-NEXT: v_alignbit_b32 v4, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v5, v12, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v13, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v9, v8, 16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB33_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_alignbit_b32 v6, v6, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_alignbit_b32 v5, v5, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_alignbit_b32 v4, v4, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v3, v3, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_alignbit_b32 v2, v2, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_alignbit_b32 v1, v1, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB33_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB33_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v7, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v6, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v6, v6, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v5, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v5, v5, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v4, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v4, v4, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v3, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v3, v3, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v2, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v2, v2, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v1, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v1, v1, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s7
; GFX9-NEXT: .LBB33_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB33_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v6
; GFX11-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v9
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v3
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GFX11-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v11
; GFX11-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
; GFX11-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
; GFX11-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-NEXT: .LBB33_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <32 x i8> @bitcast_v4i64_to_v32i8(<4 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v4i64_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v28, v7
; GCN-NEXT: v_mov_b32_e32 v24, v6
; GCN-NEXT: v_mov_b32_e32 v20, v5
; GCN-NEXT: v_mov_b32_e32 v16, v4
; GCN-NEXT: v_mov_b32_e32 v12, v3
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v4, v1
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB34_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB34_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB34_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GCN-NEXT: v_add_i32_e32 v32, vcc, 3, v32
; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v12, vcc
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT: v_addc_u32_e32 v20, vcc, 0, v20, vcc
; GCN-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; GCN-NEXT: v_addc_u32_e32 v28, vcc, 0, v28, vcc
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v32, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v32, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v32, 8
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: .LBB34_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v8, v32
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4i64_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v5
; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB34_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: .LBB34_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB34_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v34, vcc, 3, v34
; VI-NEXT: v_addc_u32_e32 v35, vcc, 0, v35, vcc
; VI-NEXT: v_add_u32_e32 v32, vcc, 3, v32
; VI-NEXT: v_addc_u32_e32 v33, vcc, 0, v33, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v34
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v16, v32
; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v37
; VI-NEXT: v_mov_b32_e32 v7, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4i64_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB34_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB34_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB34_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v34, vcc, 3, v34
; GFX9-NEXT: v_addc_co_u32_e32 v35, vcc, 0, v35, vcc
; GFX9-NEXT: v_add_co_u32_e32 v32, vcc, 3, v32
; GFX9-NEXT: v_addc_co_u32_e32 v33, vcc, 0, v33, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4i64_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB34_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB34_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB34_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v36, vcc_lo, v36, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v37, null, 0, v37, vcc_lo
; GFX11-NEXT: v_add_co_u32 v34, vcc_lo, v34, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v35, null, 0, v35, vcc_lo
; GFX11-NEXT: v_add_co_u32 v32, vcc_lo, v32, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v33, null, 0, v33, vcc_lo
; GFX11-NEXT: v_add_co_u32 v38, vcc_lo, v38, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v39, null, 0, v39, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB34_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <4 x i64> %a, splat (i64 3)
%a2 = bitcast <4 x i64> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <4 x i64> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v4i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v34, v6
; GCN-NEXT: v_mov_b32_e32 v33, v4
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v31, v0
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v37, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v35, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v38, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v39, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v23, 8, v25
; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v25, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 24, v0
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB35_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB35_4
; GCN-NEXT: .LBB35_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB35_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v32
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v33
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v34
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v24
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v30
; GCN-NEXT: v_or_b32_e32 v0, v0, v37
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v2, v38
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v4, v39
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v6, v48
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v8, v49
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v12, v21
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v16, v23
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v20, v25
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_or_b32_e32 v1, v2, v3
; GCN-NEXT: v_or_b32_e32 v2, v4, v5
; GCN-NEXT: v_or_b32_e32 v3, v6, v7
; GCN-NEXT: v_or_b32_e32 v4, v8, v9
; GCN-NEXT: v_or_b32_e32 v5, v10, v11
; GCN-NEXT: v_or_b32_e32 v6, v12, v13
; GCN-NEXT: v_or_b32_e32 v7, v14, v15
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB35_2
; GCN-NEXT: .LBB35_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v30
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v22
; GCN-NEXT: v_or_b32_e32 v0, v37, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v38, v2
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v39, v4
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v48, v6
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v49, v8
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v21, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v23, v16
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v25, v20
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x300, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_or_b32_e32 v2, v5, v4
; GCN-NEXT: v_or_b32_e32 v3, v7, v6
; GCN-NEXT: v_or_b32_e32 v4, v9, v8
; GCN-NEXT: v_or_b32_e32 v5, v11, v10
; GCN-NEXT: v_or_b32_e32 v6, v13, v12
; GCN-NEXT: v_or_b32_e32 v7, v15, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v32, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v34, v6
; VI-NEXT: v_mov_b32_e32 v33, v4
; VI-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB35_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB35_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB35_2
; VI-NEXT: .LBB35_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v31
; VI-NEXT: v_add_u16_e32 v1, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v7, 0x300
; VI-NEXT: v_add_u16_e32 v2, 3, v33
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v50, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 0x300, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v34
; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v8
; VI-NEXT: v_add_u16_e32 v3, 3, v10
; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v12
; VI-NEXT: v_add_u16_e32 v4, 3, v14
; VI-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v16
; VI-NEXT: v_add_u16_e32 v5, 3, v18
; VI-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v20
; VI-NEXT: v_add_u16_e32 v6, 3, v22
; VI-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
; VI-NEXT: v_add_u16_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v24
; VI-NEXT: v_add_u16_e32 v8, 3, v26
; VI-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v8, v13, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
; VI-NEXT: v_add_u16_sdwa v8, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v28
; VI-NEXT: v_add_u16_e32 v10, 3, v30
; VI-NEXT: v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_add_u16_sdwa v7, v9, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v31, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v33, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB35_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB35_4
; GFX9-NEXT: .LBB35_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB35_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB35_2
; GFX9-NEXT: .LBB35_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_add_u16_e32 v1, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u16_e32 v1, 3, v33
; GFX9-NEXT: v_add_u16_e32 v2, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v1, v50, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_add_u16_e32 v3, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_add_u16_e32 v4, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_add_u16_e32 v7, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_add_u16_e32 v8, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
; GFX11-NEXT: v_lshlrev_b16 v51, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v50, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB35_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB35_4
; GFX11-NEXT: .LBB35_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v51
; GFX11-NEXT: v_or_b32_e32 v1, v1, v49
; GFX11-NEXT: v_or_b32_e32 v2, v2, v50
; GFX11-NEXT: v_or_b32_e32 v3, v3, v48
; GFX11-NEXT: v_or_b32_e32 v4, v4, v38
; GFX11-NEXT: v_or_b32_e32 v5, v5, v39
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v24
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v35
; GFX11-NEXT: v_or_b32_e32 v4, v4, v36
; GFX11-NEXT: v_or_b32_e32 v5, v5, v37
; GFX11-NEXT: v_or_b32_e32 v6, v6, v19
; GFX11-NEXT: v_or_b32_e32 v7, v7, v21
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_or_b32_e32 v9, v10, v11
; GFX11-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-NEXT: v_or_b32_e32 v12, v16, v17
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr51
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr50
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB35_2
; GFX11-NEXT: .LBB35_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v31, 3
; GFX11-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-NEXT: v_add_nc_u16 v2, v33, 3
; GFX11-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-NEXT: v_add_nc_u16 v4, v8, 3
; GFX11-NEXT: v_add_nc_u16 v5, v10, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v0, v51, v0
; GFX11-NEXT: v_or_b32_e32 v1, v49, v1
; GFX11-NEXT: v_or_b32_e32 v2, v50, v2
; GFX11-NEXT: v_or_b32_e32 v3, v48, v3
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v5, v39, v5
; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_add_nc_u16 v6, v18, 3
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_add_nc_u16 v3, v12, 3
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_add_nc_u16 v5, v16, 3
; GFX11-NEXT: v_add_nc_u16 v7, v20, 3
; GFX11-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-NEXT: v_add_nc_u16 v10, v24, 3
; GFX11-NEXT: v_add_nc_u16 v12, v26, 3
; GFX11-NEXT: v_add_nc_u16 v14, v28, 3
; GFX11-NEXT: v_add_nc_u16 v16, v30, 3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v16
; GFX11-NEXT: v_or_b32_e32 v3, v35, v3
; GFX11-NEXT: v_or_b32_e32 v4, v36, v4
; GFX11-NEXT: v_or_b32_e32 v5, v37, v5
; GFX11-NEXT: v_or_b32_e32 v6, v19, v6
; GFX11-NEXT: v_or_b32_e32 v7, v21, v7
; GFX11-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-NEXT: v_or_b32_e32 v10, v13, v12
; GFX11-NEXT: v_or_b32_e32 v11, v15, v14
; GFX11-NEXT: v_or_b32_e32 v12, v17, v16
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v10
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <4 x i64>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <4 x i64>
br label %end
end:
%phi = phi <4 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x i64> %phi
}
define <16 x i16> @bitcast_v4f64_to_v16i16(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v17, v7
; GCN-NEXT: v_mov_b32_e32 v16, v6
; GCN-NEXT: v_mov_b32_e32 v19, v5
; GCN-NEXT: v_mov_b32_e32 v18, v4
; GCN-NEXT: v_mov_b32_e32 v21, v3
; GCN-NEXT: v_mov_b32_e32 v20, v2
; GCN-NEXT: v_mov_b32_e32 v23, v1
; GCN-NEXT: v_mov_b32_e32 v22, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB36_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v13, v17, v16, 16
; GCN-NEXT: v_alignbit_b32 v9, v19, v18, 16
; GCN-NEXT: v_alignbit_b32 v5, v21, v20, 16
; GCN-NEXT: v_alignbit_b32 v1, v23, v22, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v23
; GCN-NEXT: .LBB36_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB36_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GCN-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GCN-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GCN-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GCN-NEXT: v_alignbit_b32 v13, v17, v16, 16
; GCN-NEXT: v_alignbit_b32 v9, v19, v18, 16
; GCN-NEXT: v_alignbit_b32 v5, v21, v20, 16
; GCN-NEXT: v_alignbit_b32 v1, v23, v22, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v23
; GCN-NEXT: .LBB36_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v22
; GCN-NEXT: v_mov_b32_e32 v2, v23
; GCN-NEXT: v_mov_b32_e32 v4, v20
; GCN-NEXT: v_mov_b32_e32 v6, v21
; GCN-NEXT: v_mov_b32_e32 v8, v18
; GCN-NEXT: v_mov_b32_e32 v10, v19
; GCN-NEXT: v_mov_b32_e32 v12, v16
; GCN-NEXT: v_mov_b32_e32 v14, v17
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB36_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB36_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB36_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v20, v6
; GCN-NEXT: v_mov_b32_e32 v19, v4
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB37_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB37_4
; GCN-NEXT: .LBB37_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB37_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v17
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v18
; GCN-NEXT: v_or_b32_e32 v0, v0, v22
; GCN-NEXT: v_or_b32_e32 v1, v1, v23
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v19
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v20
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v2, v2, v16
; GCN-NEXT: v_or_b32_e32 v3, v3, v21
; GCN-NEXT: v_or_b32_e32 v4, v4, v9
; GCN-NEXT: v_or_b32_e32 v5, v5, v11
; GCN-NEXT: v_or_b32_e32 v6, v6, v13
; GCN-NEXT: v_or_b32_e32 v7, v7, v15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB37_2
; GCN-NEXT: .LBB37_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v17
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v0, v22, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_or_b32_e32 v2, v16, v2
; GCN-NEXT: v_or_b32_e32 v3, v21, v3
; GCN-NEXT: v_or_b32_e32 v4, v9, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v13, v6
; GCN-NEXT: v_or_b32_e32 v7, v15, v7
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB37_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
; VI-NEXT: v_add_u16_e32 v8, 3, v7
; VI-NEXT: v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_u16_e32 v8, 3, v6
; VI-NEXT: v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 3, v5
; VI-NEXT: v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 3, v4
; VI-NEXT: v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 3, v3
; VI-NEXT: v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 3, v1
; VI-NEXT: v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v8, v1
; VI-NEXT: v_add_u16_e32 v8, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB37_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB37_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB37_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <16 x half> @bitcast_v4f64_to_v16f16(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB38_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v18, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v17, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v16, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v20, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v21, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v22, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v23, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v19, v0
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: .LBB38_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB38_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v0
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v18, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v17, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v16, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v19, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23
; GCN-NEXT: .LBB38_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v19
; GCN-NEXT: v_mov_b32_e32 v1, v23
; GCN-NEXT: v_mov_b32_e32 v2, v16
; GCN-NEXT: v_mov_b32_e32 v3, v22
; GCN-NEXT: v_mov_b32_e32 v4, v17
; GCN-NEXT: v_mov_b32_e32 v5, v21
; GCN-NEXT: v_mov_b32_e32 v6, v18
; GCN-NEXT: v_mov_b32_e32 v7, v20
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB38_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB38_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB38_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <4 x double> @bitcast_v16f16_to_v4f64(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v26, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v25, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v24, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB39_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB39_4
; GCN-NEXT: .LBB39_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB39_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v24
; GCN-NEXT: v_or_b32_e32 v0, v25, v0
; GCN-NEXT: v_or_b32_e32 v1, v23, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v19, v2
; GCN-NEXT: v_or_b32_e32 v3, v17, v3
; GCN-NEXT: v_or_b32_e32 v4, v16, v4
; GCN-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-NEXT: v_or_b32_e32 v6, v9, v6
; GCN-NEXT: v_or_b32_e32 v7, v8, v7
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB39_2
; GCN-NEXT: .LBB39_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v16
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v2, v3, v2
; GCN-NEXT: v_or_b32_e32 v3, v5, v4
; GCN-NEXT: v_or_b32_e32 v4, v7, v6
; GCN-NEXT: v_or_b32_e32 v5, v11, v12
; GCN-NEXT: v_or_b32_e32 v6, v9, v13
; GCN-NEXT: v_or_b32_e32 v7, v8, v10
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB39_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 0x200
; VI-NEXT: v_add_f16_sdwa v9, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_f16_sdwa v9, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v6, v6, v9
; VI-NEXT: v_add_f16_sdwa v9, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_or_b32_e32 v5, v5, v9
; VI-NEXT: v_add_f16_sdwa v9, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_or_b32_e32 v4, v4, v9
; VI-NEXT: v_add_f16_sdwa v9, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_add_f16_sdwa v9, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_add_f16_sdwa v9, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v8, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v0, v8
; VI-NEXT: .LBB39_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB39_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB39_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <16 x bfloat> @bitcast_v4f64_to_v16bf16(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB40_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GCN-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GCN-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GCN-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v1
; GCN-NEXT: v_and_b32_e32 v22, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: .LBB40_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB40_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GCN-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v3
; GCN-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GCN-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v1
; GCN-NEXT: v_and_b32_e32 v22, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GCN-NEXT: .LBB40_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v23
; GCN-NEXT: v_mov_b32_e32 v1, v22
; GCN-NEXT: v_mov_b32_e32 v2, v21
; GCN-NEXT: v_mov_b32_e32 v3, v20
; GCN-NEXT: v_mov_b32_e32 v4, v19
; GCN-NEXT: v_mov_b32_e32 v5, v18
; GCN-NEXT: v_mov_b32_e32 v6, v17
; GCN-NEXT: v_mov_b32_e32 v7, v16
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB40_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB40_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB40_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB40_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB40_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB40_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v15
; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v14
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB41_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB41_4
; GCN-NEXT: .LBB41_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB41_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v23
; GCN-NEXT: v_alignbit_b32 v0, v0, v26, 16
; GCN-NEXT: v_alignbit_b32 v1, v1, v24, 16
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v2, v20, 16
; GCN-NEXT: v_alignbit_b32 v3, v3, v18, 16
; GCN-NEXT: v_alignbit_b32 v4, v4, v16, 16
; GCN-NEXT: v_alignbit_b32 v5, v5, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v6, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v7, v8, 16
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB41_2
; GCN-NEXT: .LBB41_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v23
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_alignbit_b32 v2, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v3, v5, v4, 16
; GCN-NEXT: v_alignbit_b32 v4, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v5, v12, v11, 16
; GCN-NEXT: v_alignbit_b32 v6, v13, v10, 16
; GCN-NEXT: v_alignbit_b32 v7, v9, v8, 16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB41_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_alignbit_b32 v6, v6, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_alignbit_b32 v5, v5, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_alignbit_b32 v4, v4, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v3, v3, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_alignbit_b32 v2, v2, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_alignbit_b32 v1, v1, v8, 16
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB41_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB41_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v7, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v6
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v6, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v6, v6, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v5, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v5, v5, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v4, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v4, v4, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v3, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v3, v3, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v2, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v2, v2, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v1, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v1, v1, v8, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s7
; GFX9-NEXT: .LBB41_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB41_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v6
; GFX11-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v9
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v3
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GFX11-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v11
; GFX11-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
; GFX11-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
; GFX11-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-NEXT: .LBB41_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <32 x i8> @bitcast_v4f64_to_v32i8(<4 x double> %a, i32 %b) {
; GCN-LABEL: bitcast_v4f64_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v35, v5
; GCN-NEXT: v_mov_b32_e32 v34, v4
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB42_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_alignbit_b32 v27, v7, v6, 24
; GCN-NEXT: v_alignbit_b32 v26, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v25, v7, v6, 8
; GCN-NEXT: v_alignbit_b32 v19, v35, v34, 24
; GCN-NEXT: v_alignbit_b32 v18, v35, v34, 16
; GCN-NEXT: v_alignbit_b32 v17, v35, v34, 8
; GCN-NEXT: v_alignbit_b32 v11, v3, v2, 24
; GCN-NEXT: v_alignbit_b32 v10, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v9, v3, v2, 8
; GCN-NEXT: v_alignbit_b32 v38, v1, v0, 24
; GCN-NEXT: v_alignbit_b32 v32, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v33, v1, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v3
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v3
; GCN-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GCN-NEXT: .LBB42_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB42_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GCN-NEXT: v_add_f64 v[34:35], v[34:35], 1.0
; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GCN-NEXT: v_alignbit_b32 v27, v7, v6, 24
; GCN-NEXT: v_alignbit_b32 v26, v7, v6, 16
; GCN-NEXT: v_alignbit_b32 v25, v7, v6, 8
; GCN-NEXT: v_alignbit_b32 v19, v35, v34, 24
; GCN-NEXT: v_alignbit_b32 v18, v35, v34, 16
; GCN-NEXT: v_alignbit_b32 v17, v35, v34, 8
; GCN-NEXT: v_alignbit_b32 v11, v3, v2, 24
; GCN-NEXT: v_alignbit_b32 v10, v3, v2, 16
; GCN-NEXT: v_alignbit_b32 v9, v3, v2, 8
; GCN-NEXT: v_alignbit_b32 v38, v1, v0, 24
; GCN-NEXT: v_alignbit_b32 v32, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v33, v1, v0, 8
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v3
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v3
; GCN-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GCN-NEXT: .LBB42_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v4, v1
; GCN-NEXT: v_mov_b32_e32 v8, v2
; GCN-NEXT: v_mov_b32_e32 v12, v3
; GCN-NEXT: v_mov_b32_e32 v16, v34
; GCN-NEXT: v_mov_b32_e32 v20, v35
; GCN-NEXT: v_mov_b32_e32 v24, v6
; GCN-NEXT: v_mov_b32_e32 v28, v7
; GCN-NEXT: v_mov_b32_e32 v1, v33
; GCN-NEXT: v_mov_b32_e32 v2, v32
; GCN-NEXT: v_mov_b32_e32 v3, v38
; GCN-NEXT: v_mov_b32_e32 v6, v37
; GCN-NEXT: v_mov_b32_e32 v7, v36
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v4f64_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v5
; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB42_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: .LBB42_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB42_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[32:33], v[32:33], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: v_add_f64 v[34:35], v[34:35], 1.0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v34
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v16, v32
; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v37
; VI-NEXT: v_mov_b32_e32 v7, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v4f64_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB42_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB42_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB42_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[32:33], v[32:33], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: v_add_f64 v[34:35], v[34:35], 1.0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v4f64_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB42_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB42_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB42_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[32:33], v[32:33], 1.0
; GFX11-NEXT: v_add_f64 v[34:35], v[34:35], 1.0
; GFX11-NEXT: v_add_f64 v[36:37], v[36:37], 1.0
; GFX11-NEXT: v_add_f64 v[38:39], v[38:39], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB42_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <4 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <4 x double> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <4 x double> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v4f64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v34, v6
; GCN-NEXT: v_mov_b32_e32 v33, v4
; GCN-NEXT: v_mov_b32_e32 v32, v2
; GCN-NEXT: v_mov_b32_e32 v31, v0
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v37, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v35, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v38, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v39, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v23, 8, v25
; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v25, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_lshlrev_b32_e32 v19, 24, v0
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB43_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB43_4
; GCN-NEXT: .LBB43_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB43_3: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v32
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v33
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v34
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v24
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v30
; GCN-NEXT: v_or_b32_e32 v0, v0, v37
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v2, v38
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v4, v39
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v6, v48
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v8, v49
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v12, v21
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v16, v23
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v20, v25
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_or_b32_e32 v1, v2, v3
; GCN-NEXT: v_or_b32_e32 v2, v4, v5
; GCN-NEXT: v_or_b32_e32 v3, v6, v7
; GCN-NEXT: v_or_b32_e32 v4, v8, v9
; GCN-NEXT: v_or_b32_e32 v5, v10, v11
; GCN-NEXT: v_or_b32_e32 v6, v12, v13
; GCN-NEXT: v_or_b32_e32 v7, v14, v15
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB43_2
; GCN-NEXT: .LBB43_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v30
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v20, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v22, 0xff, v22
; GCN-NEXT: v_or_b32_e32 v0, v37, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v2, v38, v2
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v4, v39, v4
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v6, v48, v6
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v49, v8
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v21, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v16, v23, v16
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GCN-NEXT: v_or_b32_e32 v20, v25, v20
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
; GCN-NEXT: v_or_b32_e32 v1, v35, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; GCN-NEXT: v_or_b32_e32 v3, v36, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v9, v13, v10
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v11, v15, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v16
; GCN-NEXT: v_or_b32_e32 v13, v17, v18
; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x300, v20
; GCN-NEXT: v_or_b32_e32 v15, v19, v21
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_or_b32_e32 v1, v3, v2
; GCN-NEXT: v_or_b32_e32 v2, v5, v4
; GCN-NEXT: v_or_b32_e32 v3, v7, v6
; GCN-NEXT: v_or_b32_e32 v4, v9, v8
; GCN-NEXT: v_or_b32_e32 v5, v11, v10
; GCN-NEXT: v_or_b32_e32 v6, v13, v12
; GCN-NEXT: v_or_b32_e32 v7, v15, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v32, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v34, v6
; VI-NEXT: v_mov_b32_e32 v33, v4
; VI-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB43_4
; VI-NEXT: .LBB43_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB43_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB43_2
; VI-NEXT: .LBB43_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v31
; VI-NEXT: v_add_u16_e32 v1, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v7, 0x300
; VI-NEXT: v_add_u16_e32 v2, 3, v33
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v50, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 0x300, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v34
; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v8
; VI-NEXT: v_add_u16_e32 v3, 3, v10
; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v12
; VI-NEXT: v_add_u16_e32 v4, 3, v14
; VI-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v16
; VI-NEXT: v_add_u16_e32 v5, 3, v18
; VI-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v20
; VI-NEXT: v_add_u16_e32 v6, 3, v22
; VI-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
; VI-NEXT: v_add_u16_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v24
; VI-NEXT: v_add_u16_e32 v8, 3, v26
; VI-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v8, v13, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
; VI-NEXT: v_add_u16_sdwa v8, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v28
; VI-NEXT: v_add_u16_e32 v10, 3, v30
; VI-NEXT: v_or_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_add_u16_sdwa v7, v9, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v4f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v31, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v33, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v52, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v48, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB43_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB43_4
; GFX9-NEXT: .LBB43_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB43_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v31, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v51 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v33, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v49 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB43_2
; GFX9-NEXT: .LBB43_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_add_u16_e32 v1, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v51, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u16_e32 v1, 3, v33
; GFX9-NEXT: v_add_u16_e32 v2, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v1, v50, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_add_u16_e32 v3, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_add_u16_e32 v4, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v3, v38, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v4, v37, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v4, v36, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v5, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v5, v19, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_add_u16_e32 v7, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_add_u16_e32 v8, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v4f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
; GFX11-NEXT: v_lshlrev_b16 v51, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v50, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB43_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB43_4
; GFX11-NEXT: .LBB43_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v51
; GFX11-NEXT: v_or_b32_e32 v1, v1, v49
; GFX11-NEXT: v_or_b32_e32 v2, v2, v50
; GFX11-NEXT: v_or_b32_e32 v3, v3, v48
; GFX11-NEXT: v_or_b32_e32 v4, v4, v38
; GFX11-NEXT: v_or_b32_e32 v5, v5, v39
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v24
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v35
; GFX11-NEXT: v_or_b32_e32 v4, v4, v36
; GFX11-NEXT: v_or_b32_e32 v5, v5, v37
; GFX11-NEXT: v_or_b32_e32 v6, v6, v19
; GFX11-NEXT: v_or_b32_e32 v7, v7, v21
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_or_b32_e32 v9, v10, v11
; GFX11-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-NEXT: v_or_b32_e32 v12, v16, v17
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr51
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr50
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB43_2
; GFX11-NEXT: .LBB43_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v31, 3
; GFX11-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-NEXT: v_add_nc_u16 v2, v33, 3
; GFX11-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-NEXT: v_add_nc_u16 v4, v8, 3
; GFX11-NEXT: v_add_nc_u16 v5, v10, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v0, v51, v0
; GFX11-NEXT: v_or_b32_e32 v1, v49, v1
; GFX11-NEXT: v_or_b32_e32 v2, v50, v2
; GFX11-NEXT: v_or_b32_e32 v3, v48, v3
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v5, v39, v5
; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_add_nc_u16 v6, v18, 3
; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-NEXT: v_add_nc_u16 v3, v12, 3
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_add_nc_u16 v5, v16, 3
; GFX11-NEXT: v_add_nc_u16 v7, v20, 3
; GFX11-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-NEXT: v_add_nc_u16 v10, v24, 3
; GFX11-NEXT: v_add_nc_u16 v12, v26, 3
; GFX11-NEXT: v_add_nc_u16 v14, v28, 3
; GFX11-NEXT: v_add_nc_u16 v16, v30, 3
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v16, 0xff, v16
; GFX11-NEXT: v_or_b32_e32 v3, v35, v3
; GFX11-NEXT: v_or_b32_e32 v4, v36, v4
; GFX11-NEXT: v_or_b32_e32 v5, v37, v5
; GFX11-NEXT: v_or_b32_e32 v6, v19, v6
; GFX11-NEXT: v_or_b32_e32 v7, v21, v7
; GFX11-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-NEXT: v_or_b32_e32 v10, v13, v12
; GFX11-NEXT: v_or_b32_e32 v11, v15, v14
; GFX11-NEXT: v_or_b32_e32 v12, v17, v16
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v10
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_or_b32_e32 v7, v11, v12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <4 x double>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <4 x double>
br label %end
end:
%phi = phi <4 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <4 x double> %phi
}
define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v31, v15
; GCN-NEXT: v_mov_b32_e32 v30, v14
; GCN-NEXT: v_mov_b32_e32 v29, v13
; GCN-NEXT: v_mov_b32_e32 v28, v12
; GCN-NEXT: v_mov_b32_e32 v27, v11
; GCN-NEXT: v_mov_b32_e32 v26, v10
; GCN-NEXT: v_mov_b32_e32 v25, v9
; GCN-NEXT: v_mov_b32_e32 v24, v8
; GCN-NEXT: v_mov_b32_e32 v23, v7
; GCN-NEXT: v_mov_b32_e32 v22, v6
; GCN-NEXT: v_mov_b32_e32 v21, v5
; GCN-NEXT: v_mov_b32_e32 v20, v4
; GCN-NEXT: v_mov_b32_e32 v19, v3
; GCN-NEXT: v_mov_b32_e32 v18, v2
; GCN-NEXT: v_mov_b32_e32 v17, v1
; GCN-NEXT: v_mov_b32_e32 v32, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB44_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB44_4
; GCN-NEXT: .LBB44_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB44_3: ; %cmp.false
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v32
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v27
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v28
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v29
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v30
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v31
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB44_2
; GCN-NEXT: .LBB44_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v31
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v30
; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v29
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v27
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v25
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v23
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v21
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v32
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB44_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 3
; VI-NEXT: v_add_u16_sdwa v9, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v10, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v11, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v12, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v13, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v14, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v15, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v8, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v7, 3, v7
; VI-NEXT: v_add_u16_e32 v6, 3, v6
; VI-NEXT: v_add_u16_e32 v5, 3, v5
; VI-NEXT: v_add_u16_e32 v4, 3, v4
; VI-NEXT: v_add_u16_e32 v3, 3, v3
; VI-NEXT: v_add_u16_e32 v2, 3, v2
; VI-NEXT: v_add_u16_e32 v1, 3, v1
; VI-NEXT: v_add_u16_e32 v0, 3, v0
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_or_b32_e32 v6, v6, v15
; VI-NEXT: v_or_b32_e32 v5, v5, v14
; VI-NEXT: v_or_b32_e32 v4, v4, v13
; VI-NEXT: v_or_b32_e32 v3, v3, v12
; VI-NEXT: v_or_b32_e32 v2, v2, v11
; VI-NEXT: v_or_b32_e32 v1, v1, v10
; VI-NEXT: v_or_b32_e32 v0, v0, v9
; VI-NEXT: .LBB44_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB44_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB44_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <16 x i16> @bitcast_v16f16_to_v16i16(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14
; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB45_2
; GCN-NEXT: ; %bb.1: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v15
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_or_b32_e32 v4, v4, v5
; GCN-NEXT: v_or_b32_e32 v8, v8, v9
; GCN-NEXT: v_or_b32_e32 v12, v12, v13
; GCN-NEXT: v_or_b32_e32 v14, v14, v16
; GCN-NEXT: v_or_b32_e32 v10, v10, v17
; GCN-NEXT: v_or_b32_e32 v6, v6, v18
; GCN-NEXT: v_or_b32_e32 v2, v2, v19
; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v9, 16
; GCN-NEXT: v_alignbit_b32 v13, v14, v13, 16
; GCN-NEXT: .LBB45_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB45_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 0x200
; VI-NEXT: v_add_f16_e32 v8, 0x200, v0
; VI-NEXT: v_add_f16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v5
; VI-NEXT: v_add_f16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v16, v7
; VI-NEXT: v_or_b32_e32 v6, v15, v6
; VI-NEXT: v_or_b32_e32 v5, v14, v5
; VI-NEXT: v_or_b32_e32 v4, v13, v4
; VI-NEXT: v_or_b32_e32 v3, v12, v3
; VI-NEXT: v_or_b32_e32 v2, v11, v2
; VI-NEXT: v_or_b32_e32 v1, v10, v1
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB45_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB45_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB45_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v23, v14
; GCN-NEXT: v_mov_b32_e32 v22, v12
; GCN-NEXT: v_mov_b32_e32 v21, v10
; GCN-NEXT: v_mov_b32_e32 v20, v8
; GCN-NEXT: v_mov_b32_e32 v19, v6
; GCN-NEXT: v_mov_b32_e32 v18, v4
; GCN-NEXT: v_mov_b32_e32 v17, v2
; GCN-NEXT: v_mov_b32_e32 v24, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB46_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB46_4
; GCN-NEXT: .LBB46_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB46_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v24
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB46_2
; GCN-NEXT: .LBB46_4: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v23
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v21
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v19
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v17
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v24
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_or_b32_e32 v0, v15, v0
; GCN-NEXT: v_or_b32_e32 v2, v13, v2
; GCN-NEXT: v_or_b32_e32 v4, v11, v4
; GCN-NEXT: v_or_b32_e32 v6, v9, v6
; GCN-NEXT: v_or_b32_e32 v7, v7, v8
; GCN-NEXT: v_or_b32_e32 v5, v5, v10
; GCN-NEXT: v_or_b32_e32 v3, v3, v12
; GCN-NEXT: v_or_b32_e32 v1, v1, v14
; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v6
; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v7
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v5
; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v1
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v8
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB46_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v8, 3
; VI-NEXT: v_add_u16_sdwa v9, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v10, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v11, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v12, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v13, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v14, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v15, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v8, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v7, 3, v7
; VI-NEXT: v_add_u16_e32 v6, 3, v6
; VI-NEXT: v_add_u16_e32 v5, 3, v5
; VI-NEXT: v_add_u16_e32 v4, 3, v4
; VI-NEXT: v_add_u16_e32 v3, 3, v3
; VI-NEXT: v_add_u16_e32 v2, 3, v2
; VI-NEXT: v_add_u16_e32 v1, 3, v1
; VI-NEXT: v_add_u16_e32 v0, 3, v0
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_or_b32_e32 v6, v6, v15
; VI-NEXT: v_or_b32_e32 v5, v5, v14
; VI-NEXT: v_or_b32_e32 v4, v4, v13
; VI-NEXT: v_or_b32_e32 v3, v3, v12
; VI-NEXT: v_or_b32_e32 v2, v2, v11
; VI-NEXT: v_or_b32_e32 v1, v1, v10
; VI-NEXT: v_or_b32_e32 v0, v0, v9
; VI-NEXT: .LBB46_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB46_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: .LBB46_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v14
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v15
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB47_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB47_4
; GCN-NEXT: .LBB47_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB47_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v31
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v30
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v16
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v29
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v18
; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v27
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v26
; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v24
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v22
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB47_2
; GCN-NEXT: .LBB47_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v28
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v27
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v23
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v16, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v17, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v9
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v18, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v14
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GCN-NEXT: v_and_b32_e32 v22, 0xffff0000, v6
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v8
; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v4
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v10
; GCN-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v12
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GCN-NEXT: v_alignbit_b32 v0, v14, v0, 16
; GCN-NEXT: v_alignbit_b32 v4, v19, v2, 16
; GCN-NEXT: v_alignbit_b32 v8, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v12, v21, v5, 16
; GCN-NEXT: v_alignbit_b32 v14, v15, v17, 16
; GCN-NEXT: v_alignbit_b32 v10, v11, v9, 16
; GCN-NEXT: v_alignbit_b32 v6, v7, v18, 16
; GCN-NEXT: v_alignbit_b32 v2, v3, v13, 16
; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GCN-NEXT: v_alignbit_b32 v5, v6, v24, 16
; GCN-NEXT: v_alignbit_b32 v9, v10, v23, 16
; GCN-NEXT: v_alignbit_b32 v13, v14, v22, 16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB47_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; VI-NEXT: v_bfe_u32 v10, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v1
; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; VI-NEXT: v_bfe_u32 v11, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v2
; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; VI-NEXT: v_bfe_u32 v12, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v3
; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; VI-NEXT: v_bfe_u32 v13, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v4
; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v5
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; VI-NEXT: v_bfe_u32 v14, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v5
; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v6
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; VI-NEXT: v_bfe_u32 v15, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v6
; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, s6, v16
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
; VI-NEXT: v_bfe_u32 v16, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v7
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v16, v17, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v15, 16
; VI-NEXT: v_alignbit_b32 v6, v6, v14, 16
; VI-NEXT: v_alignbit_b32 v5, v5, v13, 16
; VI-NEXT: v_alignbit_b32 v4, v4, v12, 16
; VI-NEXT: v_alignbit_b32 v3, v3, v11, 16
; VI-NEXT: v_alignbit_b32 v2, v2, v10, 16
; VI-NEXT: v_alignbit_b32 v1, v1, v9, 16
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB47_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB47_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; GFX9-NEXT: v_bfe_u32 v10, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v1, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX9-NEXT: v_bfe_u32 v11, v10, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v11, v11, v10, s6
; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; GFX9-NEXT: v_bfe_u32 v11, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v11, v11, v2, s6
; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX9-NEXT: v_bfe_u32 v12, v11, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v12, v12, v11, s6
; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v11
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; GFX9-NEXT: v_bfe_u32 v12, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v12, v12, v3, s6
; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX9-NEXT: v_bfe_u32 v13, v12, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v13, v13, v12, s6
; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v12
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; GFX9-NEXT: v_bfe_u32 v13, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v13, v13, v4, s6
; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v5
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GFX9-NEXT: v_bfe_u32 v14, v13, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v14, v14, v13, s6
; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v13
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; GFX9-NEXT: v_bfe_u32 v14, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v14, v14, v5, s6
; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v6
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; GFX9-NEXT: v_bfe_u32 v15, v14, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v15, v15, v14, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX9-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v15, v15, v6, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX9-NEXT: v_bfe_u32 v16, v15, 16, 1
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v16, v16, v15, s6
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v15
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
; GFX9-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v16, v16, v7, s6
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v16, v17, vcc
; GFX9-NEXT: s_mov_b32 s6, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v15, s6
; GFX9-NEXT: v_perm_b32 v6, v6, v14, s6
; GFX9-NEXT: v_perm_b32 v5, v5, v13, s6
; GFX9-NEXT: v_perm_b32 v4, v4, v12, s6
; GFX9-NEXT: v_perm_b32 v3, v3, v11, s6
; GFX9-NEXT: v_perm_b32 v2, v2, v10, s6
; GFX9-NEXT: v_perm_b32 v1, v1, v9, s6
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s6
; GFX9-NEXT: .LBB47_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB47_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
; GFX11-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v12, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
; GFX11-NEXT: v_bfe_u32 v12, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-NEXT: v_cndmask_b32_e32 v9, v13, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v12, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v18, v4, 16, 1
; GFX11-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v10, 16, 1
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v11, v13, v10, 0x7fff
; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-NEXT: v_bfe_u32 v13, v14, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v14, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v14
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-NEXT: v_bfe_u32 v14, v15, 16, 1
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_add3_u32 v14, v14, v15, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_add3_u32 v15, v18, v4, 0x7fff
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v19, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11-NEXT: v_add3_u32 v18, v19, v12, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v6
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: v_add3_u32 v17, v21, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v12, v18, v20, vcc_lo
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-NEXT: v_bfe_u32 v22, v6, 16, 1
; GFX11-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
; GFX11-NEXT: v_add3_u32 v21, v22, v6, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v6
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
; GFX11-NEXT: v_add3_u32 v23, v23, v18, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v7
; GFX11-NEXT: v_cndmask_b32_e32 v6, v21, v22, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-NEXT: v_add3_u32 v19, v19, v7, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v18, v23, v24, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v18, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v20, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
; GFX11-NEXT: v_perm_b32 v5, v5, v12, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v3, v3, v11, 0x7060302
; GFX11-NEXT: .LBB47_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; GCN-LABEL: bitcast_v16i16_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v48, v15
; GCN-NEXT: v_mov_b32_e32 v32, v14
; GCN-NEXT: v_mov_b32_e32 v37, v12
; GCN-NEXT: v_mov_b32_e32 v49, v11
; GCN-NEXT: v_mov_b32_e32 v33, v10
; GCN-NEXT: v_mov_b32_e32 v36, v8
; GCN-NEXT: v_mov_b32_e32 v50, v7
; GCN-NEXT: v_mov_b32_e32 v34, v6
; GCN-NEXT: v_mov_b32_e32 v38, v4
; GCN-NEXT: v_mov_b32_e32 v51, v3
; GCN-NEXT: v_mov_b32_e32 v35, v2
; GCN-NEXT: v_mov_b32_e32 v39, v0
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v51
; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v50
; GCN-NEXT: s_waitcnt expcnt(3)
; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v9
; GCN-NEXT: s_waitcnt expcnt(2)
; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v49
; GCN-NEXT: s_waitcnt expcnt(1)
; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v13
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v43, 16, v48
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB48_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v39
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v35
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v38
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v34
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v36
; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v33
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v37
; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v32
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v51
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v50
; GCN-NEXT: v_and_b32_e32 v22, 0xffff, v49
; GCN-NEXT: v_and_b32_e32 v30, 0xffff, v48
; GCN-NEXT: v_bfe_u32 v7, v51, 8, 8
; GCN-NEXT: v_bfe_u32 v15, v50, 8, 8
; GCN-NEXT: v_bfe_u32 v23, v49, 8, 8
; GCN-NEXT: v_or_b32_e32 v0, v0, v52
; GCN-NEXT: v_or_b32_e32 v4, v1, v53
; GCN-NEXT: v_or_b32_e32 v8, v2, v54
; GCN-NEXT: v_or_b32_e32 v12, v3, v55
; GCN-NEXT: v_or_b32_e32 v16, v5, v40
; GCN-NEXT: v_or_b32_e32 v20, v9, v41
; GCN-NEXT: v_or_b32_e32 v24, v10, v42
; GCN-NEXT: v_or_b32_e32 v28, v11, v43
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_bfe_u32 v31, v48, 8, 8
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr52
; GCN-NEXT: ; implicit-def: $vgpr53
; GCN-NEXT: ; implicit-def: $vgpr54
; GCN-NEXT: ; implicit-def: $vgpr55
; GCN-NEXT: ; implicit-def: $vgpr40
; GCN-NEXT: ; implicit-def: $vgpr41
; GCN-NEXT: ; implicit-def: $vgpr42
; GCN-NEXT: ; implicit-def: $vgpr43
; GCN-NEXT: .LBB48_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB48_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v37
; GCN-NEXT: s_mov_b32 s6, 0x30000
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v36
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v33
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v38
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v34
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v39
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v35
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v0, v42, v0
; GCN-NEXT: v_or_b32_e32 v1, v43, v1
; GCN-NEXT: v_or_b32_e32 v2, v40, v2
; GCN-NEXT: v_or_b32_e32 v3, v41, v3
; GCN-NEXT: v_or_b32_e32 v4, v54, v4
; GCN-NEXT: v_or_b32_e32 v5, v55, v5
; GCN-NEXT: v_or_b32_e32 v6, v52, v6
; GCN-NEXT: v_or_b32_e32 v7, v53, v7
; GCN-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v0
; GCN-NEXT: v_add_i32_e32 v28, vcc, s6, v1
; GCN-NEXT: v_add_i32_e32 v16, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v20, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v5
; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v6
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v7
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v20
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v28
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: .LBB48_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16i16_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v5
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v5
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v4
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v3
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v3
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v39, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[0:1]
; VI-NEXT: v_mov_b32_e32 v50, v0
; VI-NEXT: v_mov_b32_e32 v48, v1
; VI-NEXT: v_mov_b32_e32 v8, v2
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v16, v4
; VI-NEXT: v_mov_b32_e32 v49, v5
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v51, v7
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: .LBB48_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
; VI-NEXT: v_add_u16_sdwa v36, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v32, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v14, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v22, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v18, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v30, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v26, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v48, 3, v1
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
; VI-NEXT: v_add_u16_e32 v50, 3, v0
; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v32
; VI-NEXT: v_add_u16_e32 v35, 3, v3
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
; VI-NEXT: v_add_u16_e32 v49, 3, v5
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v22
; VI-NEXT: v_add_u16_e32 v16, 3, v4
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; VI-NEXT: v_add_u16_e32 v51, 3, v7
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
; VI-NEXT: v_add_u16_e32 v24, 3, v6
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v26
; VI-NEXT: v_or_b32_e32 v1, v48, v1
; VI-NEXT: v_or_b32_e32 v0, v50, v0
; VI-NEXT: v_or_b32_e32 v3, v35, v3
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_or_b32_e32 v5, v49, v5
; VI-NEXT: v_or_b32_e32 v4, v16, v4
; VI-NEXT: v_or_b32_e32 v7, v51, v7
; VI-NEXT: v_or_b32_e32 v6, v24, v6
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v5
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v4
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v3
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_bfe_u32 v31, v30, 8, 8
; VI-NEXT: v_bfe_u32 v23, v22, 8, 8
; VI-NEXT: v_bfe_u32 v15, v14, 8, 8
; VI-NEXT: v_bfe_u32 v39, v36, 8, 8
; VI-NEXT: .LBB48_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, v50
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v2, v32
; VI-NEXT: v_mov_b32_e32 v3, v33
; VI-NEXT: v_mov_b32_e32 v4, v48
; VI-NEXT: v_mov_b32_e32 v5, v37
; VI-NEXT: v_mov_b32_e32 v6, v36
; VI-NEXT: v_mov_b32_e32 v7, v39
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v20, v49
; VI-NEXT: v_mov_b32_e32 v28, v51
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16i16_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB48_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB48_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB48_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v35, v35, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v34, v34, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB48_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16i16_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB48_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB48_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB48_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v39, v39, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v37, v37, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v35, v35, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v34, v34, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v36, v36, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v38, v38, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB48_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <16 x i16> %a, splat (i16 3)
%a2 = bitcast <16 x i16> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <16 x i16> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v16i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v32, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v33, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v34, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v35, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v50, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v37, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v53, 8, v29
; GCN-NEXT: v_lshlrev_b32_e32 v38, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v51, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v52, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v54, 8, v17
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v39
; GCN-NEXT: v_lshlrev_b32_e32 v39, 24, v31
; GCN-NEXT: v_lshlrev_b32_e32 v55, 8, v25
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB49_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v9, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v11, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v30
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v24
; GCN-NEXT: v_or_b32_e32 v1, v1, v48
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v4, v4, v49
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_or_b32_e32 v7, v7, v50
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v11, v11, v53
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GCN-NEXT: v_or_b32_e32 v0, v0, v51
; GCN-NEXT: v_or_b32_e32 v8, v8, v52
; GCN-NEXT: v_or_b32_e32 v14, v14, v54
; GCN-NEXT: v_or_b32_e32 v15, v15, v55
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_or_b32_e32 v3, v32, v3
; GCN-NEXT: v_or_b32_e32 v2, v33, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v5, v34, v5
; GCN-NEXT: v_or_b32_e32 v6, v35, v6
; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GCN-NEXT: v_or_b32_e32 v9, v36, v9
; GCN-NEXT: v_or_b32_e32 v10, v37, v10
; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GCN-NEXT: v_or_b32_e32 v12, v39, v12
; GCN-NEXT: v_or_b32_e32 v13, v38, v13
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GCN-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GCN-NEXT: v_or_b32_e32 v19, v1, v3
; GCN-NEXT: v_or_b32_e32 v23, v4, v5
; GCN-NEXT: v_or_b32_e32 v27, v7, v9
; GCN-NEXT: v_or_b32_e32 v31, v11, v12
; GCN-NEXT: v_or_b32_e32 v17, v0, v2
; GCN-NEXT: v_or_b32_e32 v21, v8, v6
; GCN-NEXT: v_or_b32_e32 v25, v14, v10
; GCN-NEXT: v_or_b32_e32 v29, v15, v13
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v9
; GCN-NEXT: v_alignbit_b32 v1, v19, v2, 16
; GCN-NEXT: v_alignbit_b32 v5, v23, v6, 16
; GCN-NEXT: v_alignbit_b32 v9, v27, v10, 16
; GCN-NEXT: v_alignbit_b32 v13, v31, v13, 16
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v12
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr50
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr53
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr51
; GCN-NEXT: ; implicit-def: $vgpr52
; GCN-NEXT: ; implicit-def: $vgpr54
; GCN-NEXT: ; implicit-def: $vgpr55
; GCN-NEXT: .LBB49_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB49_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v24
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v26
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v30
; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v9, 0xff, v9
; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v13
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_or_b32_e32 v1, v55, v1
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v5, v53, v5
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v9, v54, v9
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GCN-NEXT: v_or_b32_e32 v13, v50, v13
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: v_or_b32_e32 v8, v52, v8
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_or_b32_e32 v12, v49, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v0, v51, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v4, v48, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
; GCN-NEXT: v_or_b32_e32 v3, v38, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; GCN-NEXT: v_or_b32_e32 v7, v39, v7
; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; GCN-NEXT: v_or_b32_e32 v11, v37, v11
; GCN-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; GCN-NEXT: v_or_b32_e32 v15, v36, v15
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v10, v35, v10
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v14, v34, v14
; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; GCN-NEXT: v_or_b32_e32 v2, v33, v2
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v6, v32, v6
; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-NEXT: v_or_b32_e32 v3, v7, v5
; GCN-NEXT: v_or_b32_e32 v5, v11, v9
; GCN-NEXT: v_or_b32_e32 v7, v15, v13
; GCN-NEXT: v_or_b32_e32 v8, v10, v8
; GCN-NEXT: v_or_b32_e32 v9, v14, v12
; GCN-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-NEXT: v_or_b32_e32 v2, v6, v4
; GCN-NEXT: v_add_i32_e32 v29, vcc, s7, v1
; GCN-NEXT: v_add_i32_e32 v31, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v25, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v27, vcc, s7, v7
; GCN-NEXT: v_add_i32_e32 v21, vcc, s7, v8
; GCN-NEXT: v_add_i32_e32 v23, vcc, s7, v9
; GCN-NEXT: v_add_i32_e32 v17, vcc, s7, v0
; GCN-NEXT: v_add_i32_e32 v19, vcc, s7, v2
; GCN-NEXT: v_alignbit_b32 v1, v19, v17, 16
; GCN-NEXT: v_alignbit_b32 v5, v23, v21, 16
; GCN-NEXT: v_alignbit_b32 v9, v27, v25, 16
; GCN-NEXT: v_alignbit_b32 v13, v31, v29, 16
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v27
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v31
; GCN-NEXT: .LBB49_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v17
; GCN-NEXT: v_mov_b32_e32 v2, v19
; GCN-NEXT: v_mov_b32_e32 v4, v21
; GCN-NEXT: v_mov_b32_e32 v6, v23
; GCN-NEXT: v_mov_b32_e32 v8, v25
; GCN-NEXT: v_mov_b32_e32 v10, v27
; GCN-NEXT: v_mov_b32_e32 v12, v29
; GCN-NEXT: v_mov_b32_e32 v14, v31
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v32, v6
; VI-NEXT: v_mov_b32_e32 v34, v4
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB49_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB49_4
; VI-NEXT: .LBB49_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB49_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v32, v38 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB49_2
; VI-NEXT: .LBB49_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v30
; VI-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v1, 0x300
; VI-NEXT: v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v28
; VI-NEXT: v_or_b32_sdwa v28, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v26
; VI-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v24
; VI-NEXT: v_or_b32_sdwa v24, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v22
; VI-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v20
; VI-NEXT: v_or_b32_sdwa v20, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v18
; VI-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v16
; VI-NEXT: v_or_b32_sdwa v16, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v14
; VI-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v12
; VI-NEXT: v_or_b32_sdwa v12, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v10
; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v8
; VI-NEXT: v_or_b32_sdwa v8, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v34
; VI-NEXT: v_or_b32_sdwa v10, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v33
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 0x300, v12
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v1, 3, v31
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 0x300, v16
; VI-NEXT: v_or_b32_sdwa v1, v35, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 0x300, v20
; VI-NEXT: v_add_u16_e32 v1, 0x300, v1
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 0x300, v24
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_u16_e32 v1, 0x300, v10
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 0x300, v28
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v33, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v31, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB49_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB49_4
; GFX9-NEXT: .LBB49_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB49_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: v_or_b32_sdwa v1, v31, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB49_2
; GFX9-NEXT: .LBB49_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v0, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_or_b32_sdwa v0, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v10, v35, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v10, v0, s6
; GFX9-NEXT: v_perm_b32 v1, v9, v1, s6
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v11, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v15, v4, s6
; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v16i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v23, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v25, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB49_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB49_4
; GFX11-NEXT: .LBB49_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB49_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v37
; GFX11-NEXT: v_or_b32_e32 v1, v1, v35
; GFX11-NEXT: v_or_b32_e32 v2, v2, v38
; GFX11-NEXT: v_or_b32_e32 v3, v3, v36
; GFX11-NEXT: v_or_b32_e32 v4, v4, v48
; GFX11-NEXT: v_or_b32_e32 v5, v5, v9
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX11-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v39
; GFX11-NEXT: v_or_b32_e32 v5, v5, v15
; GFX11-NEXT: v_or_b32_e32 v6, v6, v13
; GFX11-NEXT: v_or_b32_e32 v7, v7, v49
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
; GFX11-NEXT: v_or_b32_e32 v9, v9, v21
; GFX11-NEXT: v_or_b32_e32 v10, v10, v19
; GFX11-NEXT: v_or_b32_e32 v11, v11, v23
; GFX11-NEXT: v_or_b32_e32 v12, v12, v25
; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB49_2
; GFX11-NEXT: .LBB49_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-NEXT: v_add_nc_u16 v2, v24, 3
; GFX11-NEXT: v_add_nc_u16 v3, v26, 3
; GFX11-NEXT: v_add_nc_u16 v4, v20, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v1, v25, v1
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v2, v21, v2
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v19, v3
; GFX11-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v49, v4
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v2
; GFX11-NEXT: v_or_b32_e32 v2, v17, v5
; GFX11-NEXT: v_add_nc_u16 v17, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v0, v16, 3
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v1, v12, 3
; GFX11-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v2
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v0, v15, v0
; GFX11-NEXT: v_add_nc_u16 v2, v8, 3
; GFX11-NEXT: v_or_b32_e32 v1, v39, v1
; GFX11-NEXT: v_add_nc_u16 v14, v31, 3
; GFX11-NEXT: v_add_nc_u16 v10, v10, 3
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v13, v3
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v11, v4
; GFX11-NEXT: v_add_nc_u16 v4, v32, 3
; GFX11-NEXT: v_add_nc_u16 v11, v33, 3
; GFX11-NEXT: v_add_nc_u16 v13, v34, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v2, v48, v2
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v11, v37, v11
; GFX11-NEXT: v_or_b32_e32 v13, v35, v13
; GFX11-NEXT: v_or_b32_e32 v14, v36, v14
; GFX11-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v13
; GFX11-NEXT: v_add_nc_u16 v13, 0x300, v14
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v14, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-NEXT: v_perm_b32 v0, v11, v10, 0x5040100
; GFX11-NEXT: v_perm_b32 v1, v13, v4, 0x5040100
; GFX11-NEXT: v_perm_b32 v2, v9, v2, 0x5040100
; GFX11-NEXT: v_perm_b32 v3, v14, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v15, v8, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v19, v7, 0x5040100
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <16 x i16>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <16 x i16>
br label %end
end:
%phi = phi <16 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x i16> %phi
}
define <16 x bfloat> @bitcast_v16f16_to_v16bf16(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v24, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v25, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v26, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v27, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v28, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v29, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v30, v14
; GCN-NEXT: v_cvt_f16_f32_e32 v31, v15
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB50_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB50_4
; GCN-NEXT: .LBB50_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB50_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v17
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v19
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v23
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v24
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v25
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v26
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v27
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v28
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v29
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v31
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB50_2
; GCN-NEXT: .LBB50_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v31
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v30
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v29
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v28
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v27
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v26
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v25
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v16
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v16, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v17, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v18, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v19, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v20, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v21, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v23, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v15
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v14
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v13
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v12
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v11
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v10
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v16
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v17
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v18
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v19
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v20
; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v21
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v23
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 0x200
; VI-NEXT: v_add_f16_e32 v8, 0x200, v0
; VI-NEXT: v_add_f16_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v5
; VI-NEXT: v_add_f16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v16, v7
; VI-NEXT: v_or_b32_e32 v6, v15, v6
; VI-NEXT: v_or_b32_e32 v5, v14, v5
; VI-NEXT: v_or_b32_e32 v4, v13, v4
; VI-NEXT: v_or_b32_e32 v3, v12, v3
; VI-NEXT: v_or_b32_e32 v2, v11, v2
; VI-NEXT: v_or_b32_e32 v1, v10, v1
; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: .LBB50_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB50_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-NEXT: .LBB50_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}
define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v14
; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v15
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB51_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB51_4
; GCN-NEXT: .LBB51_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB51_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v16
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v17
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v18
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v19
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v20
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v21
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v22
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v23
; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v24
; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v25
; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v26
; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v27
; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v28
; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v29
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v30
; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v31
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB51_2
; GCN-NEXT: .LBB51_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v31
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v28
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v27
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v26
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v25
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v24
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v23
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v22
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v21
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v20
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v19
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v18
; GCN-NEXT: v_and_b32_e32 v14, 0xffff0000, v17
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v16
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; GCN-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v8
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v9
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v11
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v13
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v14
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v15
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v23
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v21
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v19
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v17
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v16
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB51_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; VI-NEXT: v_bfe_u32 v10, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v1
; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; VI-NEXT: v_bfe_u32 v11, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v2
; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; VI-NEXT: v_bfe_u32 v12, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v3
; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; VI-NEXT: v_bfe_u32 v13, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v4
; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v5
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; VI-NEXT: v_bfe_u32 v14, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v5
; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v6
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; VI-NEXT: v_bfe_u32 v15, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v6
; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, s6, v16
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
; VI-NEXT: v_bfe_u32 v16, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v7
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v16, v17, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; VI-NEXT: v_alignbit_b32 v7, v7, v15, 16
; VI-NEXT: v_alignbit_b32 v6, v6, v14, 16
; VI-NEXT: v_alignbit_b32 v5, v5, v13, 16
; VI-NEXT: v_alignbit_b32 v4, v4, v12, 16
; VI-NEXT: v_alignbit_b32 v3, v3, v11, 16
; VI-NEXT: v_alignbit_b32 v2, v2, v10, 16
; VI-NEXT: v_alignbit_b32 v1, v1, v9, 16
; VI-NEXT: v_alignbit_b32 v0, v0, v8, 16
; VI-NEXT: .LBB51_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB51_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX9-NEXT: v_bfe_u32 v9, v8, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_add3_u32 v9, v9, v8, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX9-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v0, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; GFX9-NEXT: v_bfe_u32 v10, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v1, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX9-NEXT: v_bfe_u32 v11, v10, 16, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_add3_u32 v11, v11, v10, s6
; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; GFX9-NEXT: v_bfe_u32 v11, v2, 16, 1
; GFX9-NEXT: v_add3_u32 v11, v11, v2, s6
; GFX9-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v3
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX9-NEXT: v_bfe_u32 v12, v11, 16, 1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_add3_u32 v12, v12, v11, s6
; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v11
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX9-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; GFX9-NEXT: v_bfe_u32 v12, v3, 16, 1
; GFX9-NEXT: v_add3_u32 v12, v12, v3, s6
; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX9-NEXT: v_bfe_u32 v13, v12, 16, 1
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_add3_u32 v13, v13, v12, s6
; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v12
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX9-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; GFX9-NEXT: v_bfe_u32 v13, v4, 16, 1
; GFX9-NEXT: v_add3_u32 v13, v13, v4, s6
; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v4
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v5
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GFX9-NEXT: v_bfe_u32 v14, v13, 16, 1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_add3_u32 v14, v14, v13, s6
; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v13
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX9-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; GFX9-NEXT: v_bfe_u32 v14, v5, 16, 1
; GFX9-NEXT: v_add3_u32 v14, v14, v5, s6
; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v6
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; GFX9-NEXT: v_bfe_u32 v15, v14, 16, 1
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_add3_u32 v15, v15, v14, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX9-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX9-NEXT: v_add3_u32 v15, v15, v6, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX9-NEXT: v_bfe_u32 v16, v15, 16, 1
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_add3_u32 v16, v16, v15, s6
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v15
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
; GFX9-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX9-NEXT: v_add3_u32 v16, v16, v7, s6
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v16, v17, vcc
; GFX9-NEXT: s_mov_b32 s6, 0x7060302
; GFX9-NEXT: v_perm_b32 v7, v7, v15, s6
; GFX9-NEXT: v_perm_b32 v6, v6, v14, s6
; GFX9-NEXT: v_perm_b32 v5, v5, v13, s6
; GFX9-NEXT: v_perm_b32 v4, v4, v12, s6
; GFX9-NEXT: v_perm_b32 v3, v3, v11, s6
; GFX9-NEXT: v_perm_b32 v2, v2, v10, s6
; GFX9-NEXT: v_perm_b32 v1, v1, v9, s6
; GFX9-NEXT: v_perm_b32 v0, v0, v8, s6
; GFX9-NEXT: .LBB51_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB51_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
; GFX11-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v12, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
; GFX11-NEXT: v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
; GFX11-NEXT: v_bfe_u32 v12, v1, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-NEXT: v_cndmask_b32_e32 v9, v13, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v12, v1, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v18, v4, 16, 1
; GFX11-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v13, v10, 16, 1
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v10
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_add3_u32 v11, v13, v10, 0x7fff
; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-NEXT: v_bfe_u32 v13, v14, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
; GFX11-NEXT: v_add3_u32 v11, v13, v14, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v14
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-NEXT: v_bfe_u32 v14, v15, 16, 1
; GFX11-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
; GFX11-NEXT: v_add3_u32 v14, v14, v15, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_add3_u32 v15, v18, v4, 0x7fff
; GFX11-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
; GFX11-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-NEXT: v_bfe_u32 v19, v12, 16, 1
; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11-NEXT: v_add3_u32 v18, v19, v12, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v6
; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v4
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-NEXT: v_add3_u32 v17, v21, v5, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v12, v18, v20, vcc_lo
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-NEXT: v_bfe_u32 v22, v6, 16, 1
; GFX11-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
; GFX11-NEXT: v_add3_u32 v21, v22, v6, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v6
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
; GFX11-NEXT: v_add3_u32 v23, v23, v18, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v7
; GFX11-NEXT: v_cndmask_b32_e32 v6, v21, v22, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-NEXT: v_add3_u32 v19, v19, v7, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v18, v23, v24, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v7, v18, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v20, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
; GFX11-NEXT: v_perm_b32 v5, v5, v12, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v3, v3, v11, 0x7060302
; GFX11-NEXT: .LBB51_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
; GCN-LABEL: bitcast_v16f16_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v17, v14
; GCN-NEXT: v_mov_b32_e32 v18, v6
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v37, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v33, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v32, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v39, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v35, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v14, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v34, v18
; GCN-NEXT: v_cvt_f16_f32_e32 v50, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v38, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v36, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v51, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v49, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v30, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v48, v17
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB52_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB52_4
; GCN-NEXT: .LBB52_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB52_3: ; %cmp.false
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v37
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v6
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v39
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v14
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v50
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v51
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v30
; GCN-NEXT: v_bfe_u32 v7, v6, 8, 8
; GCN-NEXT: v_bfe_u32 v15, v14, 8, 8
; GCN-NEXT: v_bfe_u32 v23, v22, 8, 8
; GCN-NEXT: v_or_b32_e32 v0, v33, v0
; GCN-NEXT: v_or_b32_e32 v4, v32, v1
; GCN-NEXT: v_or_b32_e32 v8, v35, v2
; GCN-NEXT: v_or_b32_e32 v12, v34, v3
; GCN-NEXT: v_or_b32_e32 v16, v38, v5
; GCN-NEXT: v_or_b32_e32 v20, v36, v9
; GCN-NEXT: v_or_b32_e32 v24, v49, v10
; GCN-NEXT: v_or_b32_e32 v28, v48, v11
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_bfe_u32 v31, v30, 8, 8
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr50
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr51
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB52_2
; GCN-NEXT: .LBB52_4: ; %cmp.true
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v51
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v49
; GCN-NEXT: v_cvt_f32_f16_e32 v2, v30
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v48
; GCN-NEXT: v_cvt_f32_f16_e32 v4, v50
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v38
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v8, v36
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v39
; GCN-NEXT: v_cvt_f32_f16_e32 v10, v35
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v14
; GCN-NEXT: v_cvt_f32_f16_e32 v12, v34
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v37
; GCN-NEXT: v_cvt_f32_f16_e32 v14, v33
; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v32
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v14
; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_cvt_f16_f32_e32 v30, v2
; GCN-NEXT: v_cvt_f16_f32_e32 v2, v3
; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4
; GCN-NEXT: v_cvt_f16_f32_e32 v4, v5
; GCN-NEXT: v_cvt_f16_f32_e32 v22, v7
; GCN-NEXT: v_cvt_f16_f32_e32 v5, v8
; GCN-NEXT: v_cvt_f16_f32_e32 v7, v9
; GCN-NEXT: v_cvt_f16_f32_e32 v8, v10
; GCN-NEXT: v_cvt_f16_f32_e32 v14, v11
; GCN-NEXT: v_cvt_f16_f32_e32 v9, v12
; GCN-NEXT: v_cvt_f16_f32_e32 v10, v13
; GCN-NEXT: v_cvt_f16_f32_e32 v11, v16
; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6
; GCN-NEXT: v_cvt_f16_f32_e32 v13, v15
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v30
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v22
; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v6
; GCN-NEXT: v_bfe_u32 v7, v6, 8, 8
; GCN-NEXT: v_bfe_u32 v15, v14, 8, 8
; GCN-NEXT: v_bfe_u32 v23, v22, 8, 8
; GCN-NEXT: v_or_b32_e32 v24, v1, v0
; GCN-NEXT: v_or_b32_e32 v28, v2, v12
; GCN-NEXT: v_or_b32_e32 v16, v4, v3
; GCN-NEXT: v_or_b32_e32 v20, v5, v17
; GCN-NEXT: v_or_b32_e32 v8, v8, v18
; GCN-NEXT: v_or_b32_e32 v12, v9, v19
; GCN-NEXT: v_or_b32_e32 v0, v11, v10
; GCN-NEXT: v_or_b32_e32 v4, v13, v21
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_bfe_u32 v31, v30, 8, 8
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16f16_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v35, v5
; VI-NEXT: v_mov_b32_e32 v34, v4
; VI-NEXT: v_mov_b32_e32 v33, v3
; VI-NEXT: v_mov_b32_e32 v32, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB52_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v37, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB52_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB52_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v5, 0x200
; VI-NEXT: v_add_f16_sdwa v14, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v36, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
; VI-NEXT: v_add_f16_sdwa v10, v32, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v36
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_or_b32_e32 v12, v33, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
; VI-NEXT: v_add_f16_sdwa v22, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v1, v2
; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v11, v32, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
; VI-NEXT: v_add_f16_sdwa v18, v34, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v30, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v26, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v9, v35, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v30
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v3, v0, v3
; VI-NEXT: v_or_b32_e32 v8, v34, v8
; VI-NEXT: v_or_b32_e32 v16, v7, v13
; VI-NEXT: v_or_b32_e32 v15, v6, v5
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[8:9]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v11
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v3
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v15
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v8
; VI-NEXT: v_bfe_u32 v31, v30, 8, 8
; VI-NEXT: v_bfe_u32 v23, v22, 8, 8
; VI-NEXT: v_bfe_u32 v15, v14, 8, 8
; VI-NEXT: v_bfe_u32 v37, v36, 8, 8
; VI-NEXT: .LBB52_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v32
; VI-NEXT: v_mov_b32_e32 v12, v33
; VI-NEXT: v_mov_b32_e32 v16, v34
; VI-NEXT: v_mov_b32_e32 v20, v35
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v36
; VI-NEXT: v_mov_b32_e32 v7, v37
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB52_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB52_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB52_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: s_movk_i32 s6, 0x200
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v35, v35, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v34, v34, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v33, v33, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v32, v32, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: .LBB52_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16f16_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB52_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB52_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB52_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v39, 0x200, v39 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v37, 0x200, v37 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v35, 0x200, v35 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v33, 0x200, v33 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v34, 0x200, v34 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v36, 0x200, v36 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v38, 0x200, v38 op_sel_hi:[0,1]
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB52_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x half> %a, splat (half 0xH0200)
%a2 = bitcast <16 x half> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <16 x half> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v16f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v32, 8, v1
; GCN-NEXT: v_lshlrev_b32_e32 v33, 8, v3
; GCN-NEXT: v_lshlrev_b32_e32 v34, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v35, 8, v7
; GCN-NEXT: v_lshlrev_b32_e32 v36, 8, v9
; GCN-NEXT: v_lshlrev_b32_e32 v37, 8, v11
; GCN-NEXT: v_lshlrev_b32_e32 v38, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v39, 8, v15
; GCN-NEXT: v_lshlrev_b32_e32 v48, 8, v17
; GCN-NEXT: v_lshlrev_b32_e32 v49, 8, v19
; GCN-NEXT: v_lshlrev_b32_e32 v50, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v51, 8, v23
; GCN-NEXT: v_lshlrev_b32_e32 v52, 8, v25
; GCN-NEXT: v_lshlrev_b32_e32 v53, 8, v27
; GCN-NEXT: v_lshlrev_b32_e32 v54, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v55
; GCN-NEXT: v_lshlrev_b32_e32 v55, 8, v31
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB53_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v9, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v11, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v24
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v30
; GCN-NEXT: v_or_b32_e32 v0, v0, v32
; GCN-NEXT: v_or_b32_e32 v1, v1, v33
; GCN-NEXT: v_or_b32_e32 v2, v2, v34
; GCN-NEXT: v_or_b32_e32 v3, v3, v35
; GCN-NEXT: v_or_b32_e32 v4, v4, v36
; GCN-NEXT: v_or_b32_e32 v5, v5, v37
; GCN-NEXT: v_or_b32_e32 v6, v6, v38
; GCN-NEXT: v_or_b32_e32 v7, v7, v39
; GCN-NEXT: v_or_b32_e32 v8, v8, v48
; GCN-NEXT: v_or_b32_e32 v9, v9, v49
; GCN-NEXT: v_or_b32_e32 v10, v10, v50
; GCN-NEXT: v_or_b32_e32 v11, v11, v51
; GCN-NEXT: v_or_b32_e32 v12, v12, v52
; GCN-NEXT: v_or_b32_e32 v13, v13, v53
; GCN-NEXT: v_or_b32_e32 v14, v14, v54
; GCN-NEXT: v_or_b32_e32 v15, v15, v55
; GCN-NEXT: v_cvt_f32_f16_e32 v31, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v23, v2
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v19, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v27, v6
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v17, v8
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v21, v10
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v25, v12
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v29, v14
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr50
; GCN-NEXT: ; implicit-def: $vgpr51
; GCN-NEXT: ; implicit-def: $vgpr52
; GCN-NEXT: ; implicit-def: $vgpr53
; GCN-NEXT: ; implicit-def: $vgpr54
; GCN-NEXT: ; implicit-def: $vgpr55
; GCN-NEXT: .LBB53_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB53_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v30
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v16
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v9, 0xff, v9
; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v13
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_or_b32_e32 v1, v55, v1
; GCN-NEXT: v_or_b32_e32 v3, v54, v3
; GCN-NEXT: v_or_b32_e32 v5, v53, v5
; GCN-NEXT: v_or_b32_e32 v7, v52, v7
; GCN-NEXT: v_or_b32_e32 v9, v51, v9
; GCN-NEXT: v_or_b32_e32 v11, v50, v11
; GCN-NEXT: v_or_b32_e32 v13, v49, v13
; GCN-NEXT: v_or_b32_e32 v15, v48, v15
; GCN-NEXT: v_or_b32_e32 v14, v39, v14
; GCN-NEXT: v_or_b32_e32 v12, v38, v12
; GCN-NEXT: v_or_b32_e32 v10, v37, v10
; GCN-NEXT: v_or_b32_e32 v8, v36, v8
; GCN-NEXT: v_or_b32_e32 v6, v35, v6
; GCN-NEXT: v_or_b32_e32 v4, v34, v4
; GCN-NEXT: v_or_b32_e32 v2, v33, v2
; GCN-NEXT: v_or_b32_e32 v0, v32, v0
; GCN-NEXT: v_add_i32_e32 v16, vcc, 0x300, v1
; GCN-NEXT: v_add_i32_e32 v18, vcc, s6, v3
; GCN-NEXT: v_add_i32_e32 v20, vcc, s6, v5
; GCN-NEXT: v_add_i32_e32 v22, vcc, s6, v7
; GCN-NEXT: v_add_i32_e32 v24, vcc, s6, v9
; GCN-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v13
; GCN-NEXT: v_add_i32_e32 v13, vcc, s6, v15
; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v14
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v10
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v6
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v31, v0
; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1
; GCN-NEXT: v_cvt_f32_f16_e32 v23, v4
; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3
; GCN-NEXT: v_cvt_f32_f16_e32 v19, v8
; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5
; GCN-NEXT: v_cvt_f32_f16_e32 v27, v12
; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7
; GCN-NEXT: v_cvt_f32_f16_e32 v17, v13
; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9
; GCN-NEXT: v_cvt_f32_f16_e32 v21, v11
; GCN-NEXT: v_cvt_f32_f16_e32 v11, v24
; GCN-NEXT: v_cvt_f32_f16_e32 v25, v22
; GCN-NEXT: v_cvt_f32_f16_e32 v13, v20
; GCN-NEXT: v_cvt_f32_f16_e32 v29, v18
; GCN-NEXT: v_cvt_f32_f16_e32 v15, v16
; GCN-NEXT: .LBB53_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v31
; GCN-NEXT: v_mov_b32_e32 v2, v23
; GCN-NEXT: v_mov_b32_e32 v4, v19
; GCN-NEXT: v_mov_b32_e32 v6, v27
; GCN-NEXT: v_mov_b32_e32 v8, v17
; GCN-NEXT: v_mov_b32_e32 v10, v21
; GCN-NEXT: v_mov_b32_e32 v12, v25
; GCN-NEXT: v_mov_b32_e32 v14, v29
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v32, v6
; VI-NEXT: v_mov_b32_e32 v34, v4
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB53_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB53_4
; VI-NEXT: .LBB53_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB53_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v32, v38 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB53_2
; VI-NEXT: .LBB53_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v30
; VI-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v1, 0x300
; VI-NEXT: v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v28
; VI-NEXT: v_or_b32_sdwa v28, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v26
; VI-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v24
; VI-NEXT: v_or_b32_sdwa v24, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v22
; VI-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v20
; VI-NEXT: v_or_b32_sdwa v20, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v18
; VI-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v16
; VI-NEXT: v_or_b32_sdwa v16, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v14
; VI-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v12
; VI-NEXT: v_or_b32_sdwa v12, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v10
; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v8
; VI-NEXT: v_or_b32_sdwa v8, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v34
; VI-NEXT: v_or_b32_sdwa v10, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v33
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 0x300, v12
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v1, 3, v31
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 0x300, v16
; VI-NEXT: v_or_b32_sdwa v1, v35, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 0x300, v20
; VI-NEXT: v_add_u16_e32 v1, 0x300, v1
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 0x300, v24
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_u16_e32 v1, 0x300, v10
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 0x300, v28
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v33, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v31, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB53_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB53_4
; GFX9-NEXT: .LBB53_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB53_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: v_or_b32_sdwa v1, v31, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB53_2
; GFX9-NEXT: .LBB53_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v0, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_or_b32_sdwa v0, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v10, v35, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v10, v0, s6
; GFX9-NEXT: v_perm_b32 v1, v9, v1, s6
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v11, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v15, v4, s6
; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v16f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v23, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v25, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB53_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB53_4
; GFX11-NEXT: .LBB53_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB53_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v37
; GFX11-NEXT: v_or_b32_e32 v1, v1, v35
; GFX11-NEXT: v_or_b32_e32 v2, v2, v38
; GFX11-NEXT: v_or_b32_e32 v3, v3, v36
; GFX11-NEXT: v_or_b32_e32 v4, v4, v48
; GFX11-NEXT: v_or_b32_e32 v5, v5, v9
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX11-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v39
; GFX11-NEXT: v_or_b32_e32 v5, v5, v15
; GFX11-NEXT: v_or_b32_e32 v6, v6, v13
; GFX11-NEXT: v_or_b32_e32 v7, v7, v49
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
; GFX11-NEXT: v_or_b32_e32 v9, v9, v21
; GFX11-NEXT: v_or_b32_e32 v10, v10, v19
; GFX11-NEXT: v_or_b32_e32 v11, v11, v23
; GFX11-NEXT: v_or_b32_e32 v12, v12, v25
; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB53_2
; GFX11-NEXT: .LBB53_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-NEXT: v_add_nc_u16 v2, v24, 3
; GFX11-NEXT: v_add_nc_u16 v3, v26, 3
; GFX11-NEXT: v_add_nc_u16 v4, v20, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v1, v25, v1
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v2, v21, v2
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v19, v3
; GFX11-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v49, v4
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v2
; GFX11-NEXT: v_or_b32_e32 v2, v17, v5
; GFX11-NEXT: v_add_nc_u16 v17, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v0, v16, 3
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v1, v12, 3
; GFX11-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v2
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v0, v15, v0
; GFX11-NEXT: v_add_nc_u16 v2, v8, 3
; GFX11-NEXT: v_or_b32_e32 v1, v39, v1
; GFX11-NEXT: v_add_nc_u16 v14, v31, 3
; GFX11-NEXT: v_add_nc_u16 v10, v10, 3
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v13, v3
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v11, v4
; GFX11-NEXT: v_add_nc_u16 v4, v32, 3
; GFX11-NEXT: v_add_nc_u16 v11, v33, 3
; GFX11-NEXT: v_add_nc_u16 v13, v34, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v2, v48, v2
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v11, v37, v11
; GFX11-NEXT: v_or_b32_e32 v13, v35, v13
; GFX11-NEXT: v_or_b32_e32 v14, v36, v14
; GFX11-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v13
; GFX11-NEXT: v_add_nc_u16 v13, 0x300, v14
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v14, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-NEXT: v_perm_b32 v0, v11, v10, 0x5040100
; GFX11-NEXT: v_perm_b32 v1, v13, v4, 0x5040100
; GFX11-NEXT: v_perm_b32 v2, v9, v2, 0x5040100
; GFX11-NEXT: v_perm_b32 v3, v14, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v15, v8, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v19, v7, 0x5040100
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <16 x half>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <16 x half>
br label %end
end:
%phi = phi <16 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x half> %phi
}
define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) {
; GCN-LABEL: bitcast_v16bf16_to_v32i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GCN-NEXT: v_mul_f32_e32 v38, 1.0, v1
; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v0
; GCN-NEXT: v_mul_f32_e32 v34, 1.0, v3
; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v2
; GCN-NEXT: v_mul_f32_e32 v50, 1.0, v5
; GCN-NEXT: v_mul_f32_e32 v36, 1.0, v4
; GCN-NEXT: v_mul_f32_e32 v37, 1.0, v7
; GCN-NEXT: v_mul_f32_e32 v35, 1.0, v6
; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v9
; GCN-NEXT: v_mul_f32_e32 v48, 1.0, v8
; GCN-NEXT: v_mul_f32_e32 v49, 1.0, v11
; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v10
; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v13
; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v12
; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v15
; GCN-NEXT: v_mul_f32_e32 v51, 1.0, v14
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB54_3
; GCN-NEXT: ; %bb.1: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execnz .LBB54_4
; GCN-NEXT: .LBB54_2: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: .LBB54_3: ; %cmp.false
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v34
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v50
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v54
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v49
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v55
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v53
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v34
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v49
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v53
; GCN-NEXT: v_alignbit_b32 v0, v0, v33, 16
; GCN-NEXT: v_alignbit_b32 v4, v6, v32, 16
; GCN-NEXT: v_alignbit_b32 v8, v1, v36, 16
; GCN-NEXT: v_alignbit_b32 v12, v14, v35, 16
; GCN-NEXT: v_alignbit_b32 v16, v2, v48, 16
; GCN-NEXT: v_alignbit_b32 v20, v22, v39, 16
; GCN-NEXT: v_alignbit_b32 v24, v3, v52, 16
; GCN-NEXT: v_alignbit_b32 v28, v30, v51, 16
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr50
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr54
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr55
; GCN-NEXT: ; implicit-def: $vgpr52
; GCN-NEXT: ; implicit-def: $vgpr53
; GCN-NEXT: ; implicit-def: $vgpr51
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB54_2
; GCN-NEXT: .LBB54_4: ; %cmp.true
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v53
; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v54
; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v39
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v49
; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v36
; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v50
; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v35
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v37
; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v33
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v38
; GCN-NEXT: v_and_b32_e32 v14, 0xffff0000, v32
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v34
; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GCN-NEXT: v_add_f32_e32 v31, 0x40c00000, v3
; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v4
; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v5
; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
; GCN-NEXT: v_add_f32_e32 v16, 0x40c00000, v7
; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v9
; GCN-NEXT: v_add_f32_e32 v9, 0x40c00000, v10
; GCN-NEXT: v_add_f32_e32 v10, 0x40c00000, v11
; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v12
; GCN-NEXT: v_add_f32_e32 v7, 0x40c00000, v13
; GCN-NEXT: v_add_f32_e32 v13, 0x40c00000, v14
; GCN-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v31
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v16
; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v6
; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v10
; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v7
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v12
; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v12
; GCN-NEXT: v_lshrrev_b32_e32 v15, 24, v10
; GCN-NEXT: v_lshrrev_b32_e32 v23, 24, v16
; GCN-NEXT: v_alignbit_b32 v24, v1, v0, 16
; GCN-NEXT: v_alignbit_b32 v28, v30, v2, 16
; GCN-NEXT: v_alignbit_b32 v16, v4, v3, 16
; GCN-NEXT: v_alignbit_b32 v20, v22, v5, 16
; GCN-NEXT: v_alignbit_b32 v8, v17, v8, 16
; GCN-NEXT: v_alignbit_b32 v12, v14, v9, 16
; GCN-NEXT: v_alignbit_b32 v0, v18, v11, 16
; GCN-NEXT: v_alignbit_b32 v4, v6, v13, 16
; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24
; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16
; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8
; GCN-NEXT: v_alignbit_b32 v11, v12, v8, 24
; GCN-NEXT: v_alignbit_b32 v10, v12, v8, 16
; GCN-NEXT: v_alignbit_b32 v9, v12, v8, 8
; GCN-NEXT: v_alignbit_b32 v19, v20, v16, 24
; GCN-NEXT: v_alignbit_b32 v18, v20, v16, 16
; GCN-NEXT: v_alignbit_b32 v17, v20, v16, 8
; GCN-NEXT: v_alignbit_b32 v27, v28, v24, 24
; GCN-NEXT: v_alignbit_b32 v26, v28, v24, 16
; GCN-NEXT: v_alignbit_b32 v25, v28, v24, 8
; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GCN-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; GCN-NEXT: v_lshrrev_b32_e32 v29, 8, v28
; GCN-NEXT: v_lshrrev_b32_e32 v31, 24, v31
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v16bf16_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v5
; VI-NEXT: v_mov_b32_e32 v32, v4
; VI-NEXT: v_mov_b32_e32 v35, v3
; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB54_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: .LBB54_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB54_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v35
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v35, v3, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v34
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v34, v3, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v33
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v33, v3, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v32
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v32
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v32, v3, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v7
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v7, v3, v2, 16
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; VI-NEXT: v_alignbit_b32 v6, v3, v2, 16
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
; VI-NEXT: v_mov_b32_e32 v8, v34
; VI-NEXT: v_mov_b32_e32 v12, v35
; VI-NEXT: v_mov_b32_e32 v16, v32
; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
; VI-NEXT: v_mov_b32_e32 v1, v38
; VI-NEXT: v_mov_b32_e32 v6, v37
; VI-NEXT: v_mov_b32_e32 v7, v36
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16bf16_to_v32i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v33, v5
; GFX9-NEXT: v_mov_b32_e32 v32, v4
; GFX9-NEXT: v_mov_b32_e32 v35, v3
; GFX9-NEXT: v_mov_b32_e32 v34, v2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB54_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX9-NEXT: .LBB54_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB54_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_add3_u32 v3, v3, v2, s6
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v3, v3, v1, s6
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v4, vcc
; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_add3_u32 v3, v3, v1, s6
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
; GFX9-NEXT: v_add3_u32 v1, v1, v0, s6
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX9-NEXT: v_perm_b32 v3, v0, v5, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX9-NEXT: v_add3_u32 v1, v1, v0, s6
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v0
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v35
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX9-NEXT: v_add3_u32 v9, v9, v1, s6
; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v34
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v34
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_cndmask_b32_e32 v13, v10, v11, vcc
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; GFX9-NEXT: v_perm_b32 v11, v9, v13, s7
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v33
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v33
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_cndmask_b32_e32 v14, v10, v14, vcc
; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v10, v10, v9, s6
; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v32
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_cndmask_b32_e32 v17, v10, v15, vcc
; GFX9-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v15, v15, v9, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v32
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX9-NEXT: v_cndmask_b32_e32 v18, v15, v16, vcc
; GFX9-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX9-NEXT: v_add3_u32 v15, v15, v9, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v9
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: v_cndmask_b32_e32 v9, v15, v16, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX9-NEXT: v_bfe_u32 v16, v15, 16, 1
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX9-NEXT: v_add3_u32 v16, v16, v15, s6
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; GFX9-NEXT: v_bfe_u32 v15, v7, 16, 1
; GFX9-NEXT: v_cndmask_b32_e32 v19, v16, v19, vcc
; GFX9-NEXT: v_add3_u32 v15, v15, v7, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v16, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX9-NEXT: v_bfe_u32 v16, v15, 16, 1
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX9-NEXT: v_add3_u32 v16, v16, v15, s6
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v15
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; GFX9-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX9-NEXT: v_cndmask_b32_e32 v20, v16, v20, vcc
; GFX9-NEXT: v_add3_u32 v15, v15, v6, s6
; GFX9-NEXT: v_or_b32_e32 v16, 0x400000, v6
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
; GFX9-NEXT: v_perm_b32 v4, v8, v2, s7
; GFX9-NEXT: v_perm_b32 v12, v1, v0, s7
; GFX9-NEXT: v_perm_b32 v10, v17, v14, s7
; GFX9-NEXT: v_perm_b32 v9, v9, v18, s7
; GFX9-NEXT: v_perm_b32 v16, v7, v19, s7
; GFX9-NEXT: v_perm_b32 v15, v6, v20, s7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v15
; GFX9-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v9
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[9:10]
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v11
; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v3
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v8
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v34
; GFX9-NEXT: v_mov_b32_e32 v12, v35
; GFX9-NEXT: v_mov_b32_e32 v16, v32
; GFX9-NEXT: v_mov_b32_e32 v20, v33
; GFX9-NEXT: v_mov_b32_e32 v24, v6
; GFX9-NEXT: v_mov_b32_e32 v28, v7
; GFX9-NEXT: v_mov_b32_e32 v1, v38
; GFX9-NEXT: v_mov_b32_e32 v6, v37
; GFX9-NEXT: v_mov_b32_e32 v7, v36
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v16bf16_to_v32i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
; GFX11-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
; GFX11-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
; GFX11-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: ; implicit-def: $vgpr2
; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr27
; GFX11-NEXT: ; implicit-def: $vgpr29
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB54_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v32
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v36
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[32:33]
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[36:37]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[38:39]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v38
; GFX11-NEXT: .LBB54_2: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB54_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v39
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v38
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v38
; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v34
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v36
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v34
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX11-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-NEXT: v_add3_u32 v1, v9, v3, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v4
; GFX11-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc_lo
; GFX11-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-NEXT: v_or_b32_e32 v0, 0x400000, v2
; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v37
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v37
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v0, vcc_lo
; GFX11-NEXT: v_dual_add_f32 v7, 0x40c00000, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v36
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v2
; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc_lo
; GFX11-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
; GFX11-NEXT: v_bfe_u32 v12, v3, 16, 1
; GFX11-NEXT: v_perm_b32 v1, v5, v4, 0x7060302
; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: v_add_f32_e32 v7, 0x40c00000, v13
; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v6
; GFX11-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc_lo
; GFX11-NEXT: v_add3_u32 v9, v12, v3, 0x7fff
; GFX11-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v35
; GFX11-NEXT: v_perm_b32 v8, v11, v6, 0x7060302
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v9, 0x40c00000, v12
; GFX11-NEXT: v_add3_u32 v12, v13, v7, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v35
; GFX11-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v3
; GFX11-NEXT: v_dual_cndmask_b32 v7, v12, v13 :: v_dual_add_f32 v12, 0x40c00000, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-NEXT: v_add3_u32 v13, v15, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v17, v12, 16, 1
; GFX11-NEXT: v_perm_b32 v7, v7, v3, 0x7060302
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v14 :: v_dual_add_f32 v14, 0x40c00000, v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add3_u32 v16, v17, v12, 0x7fff
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v33
; GFX11-NEXT: v_bfe_u32 v15, v10, 16, 1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_bfe_u32 v19, v14, 16, 1
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add3_u32 v9, v15, v10, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-NEXT: v_add3_u32 v10, v19, v14, 0x7fff
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v20, v9, v15 :: v_dual_add_f32 v9, 0x40c00000, v17
; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v33
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v12
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v14
; GFX11-NEXT: v_cndmask_b32_e32 v12, v16, v18, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-NEXT: v_bfe_u32 v16, v9, 16, 1
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v32
; GFX11-NEXT: v_dual_cndmask_b32 v14, v10, v15 :: v_dual_add_f32 v15, 0x40c00000, v17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_f32_e32 v17, 0x40c00000, v18
; GFX11-NEXT: v_add3_u32 v16, v16, v9, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v9
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
; GFX11-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v17
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v12
; GFX11-NEXT: v_cndmask_b32_e32 v18, v16, v18, vcc_lo
; GFX11-NEXT: v_add3_u32 v16, v19, v15, 0x7fff
; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v19, v16, v19, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v32
; GFX11-NEXT: v_perm_b32 v16, v19, v18, 0x7060302
; GFX11-NEXT: v_cndmask_b32_e32 v17, v21, v22, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v20
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v16
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-NEXT: v_bfe_u32 v9, v10, 16, 1
; GFX11-NEXT: v_or_b32_e32 v23, 0x400000, v10
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add3_u32 v9, v9, v10, 0x7fff
; GFX11-NEXT: v_perm_b32 v10, v20, v13, 0x7060302
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v8
; GFX11-NEXT: v_cndmask_b32_e32 v15, v9, v23, vcc_lo
; GFX11-NEXT: v_perm_b32 v9, v14, v12, 0x7060302
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v11
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8]
; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v10
; GFX11-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[9:10]
; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v9
; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v9
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v15
; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v15
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-NEXT: .LBB54_4: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: v_mov_b32_e32 v0, v38
; GFX11-NEXT: v_mov_b32_e32 v4, v39
; GFX11-NEXT: v_mov_b32_e32 v8, v36
; GFX11-NEXT: v_mov_b32_e32 v12, v37
; GFX11-NEXT: v_mov_b32_e32 v16, v34
; GFX11-NEXT: v_mov_b32_e32 v20, v35
; GFX11-NEXT: v_mov_b32_e32 v24, v32
; GFX11-NEXT: v_mov_b32_e32 v28, v33
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <16 x bfloat> %a, splat (bfloat 0xR40C0)
%a2 = bitcast <16 x bfloat> %a1 to <32 x i8>
br label %end
cmp.false:
%a3 = bitcast <16 x bfloat> %a to <32 x i8>
br label %end
end:
%phi = phi <32 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <32 x i8> %phi
}
define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GCN-LABEL: bitcast_v32i8_to_v16bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
; GCN-NEXT: v_lshlrev_b32_e32 v36, 24, v3
; GCN-NEXT: v_lshlrev_b32_e32 v52, 8, v5
; GCN-NEXT: v_lshlrev_b32_e32 v37, 24, v7
; GCN-NEXT: v_lshlrev_b32_e32 v38, 24, v11
; GCN-NEXT: v_lshlrev_b32_e32 v53, 8, v13
; GCN-NEXT: v_lshlrev_b32_e32 v39, 24, v15
; GCN-NEXT: v_lshlrev_b32_e32 v48, 24, v19
; GCN-NEXT: v_lshlrev_b32_e32 v54, 8, v21
; GCN-NEXT: v_lshlrev_b32_e32 v49, 24, v23
; GCN-NEXT: v_lshlrev_b32_e32 v50, 24, v27
; GCN-NEXT: v_lshlrev_b32_e32 v55, 8, v29
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
; GCN-NEXT: v_lshlrev_b32_e32 v51, 24, v31
; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: ; implicit-def: $vgpr35
; GCN-NEXT: ; implicit-def: $vgpr21
; GCN-NEXT: ; implicit-def: $vgpr3
; GCN-NEXT: ; implicit-def: $vgpr33
; GCN-NEXT: ; implicit-def: $vgpr5
; GCN-NEXT: ; implicit-def: $vgpr19
; GCN-NEXT: ; implicit-def: $vgpr7
; GCN-NEXT: ; implicit-def: $vgpr23
; GCN-NEXT: ; implicit-def: $vgpr27
; GCN-NEXT: ; implicit-def: $vgpr29
; GCN-NEXT: ; implicit-def: $vgpr11
; GCN-NEXT: ; implicit-def: $vgpr32
; GCN-NEXT: ; implicit-def: $vgpr13
; GCN-NEXT: ; implicit-def: $vgpr34
; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB55_2
; GCN-NEXT: ; %bb.1: ; %cmp.false
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v8
; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v9
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v9, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v16
; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v17
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v20
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v22
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v24
; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v25
; GCN-NEXT: v_and_b32_e32 v17, 0xff, v26
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v28
; GCN-NEXT: v_and_b32_e32 v19, 0xff, v30
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_or_b32_e32 v3, v3, v52
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GCN-NEXT: v_or_b32_e32 v8, v8, v53
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GCN-NEXT: v_or_b32_e32 v13, v13, v54
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GCN-NEXT: v_or_b32_e32 v18, v18, v55
; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v19
; GCN-NEXT: v_or_b32_e32 v31, v1, v0
; GCN-NEXT: v_or_b32_e32 v35, v36, v2
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v3
; GCN-NEXT: v_or_b32_e32 v3, v37, v4
; GCN-NEXT: v_or_b32_e32 v33, v6, v5
; GCN-NEXT: v_or_b32_e32 v5, v38, v7
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v8
; GCN-NEXT: v_or_b32_e32 v7, v39, v9
; GCN-NEXT: v_or_b32_e32 v23, v11, v10
; GCN-NEXT: v_or_b32_e32 v27, v48, v12
; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v13
; GCN-NEXT: v_or_b32_e32 v11, v49, v14
; GCN-NEXT: v_or_b32_e32 v32, v16, v15
; GCN-NEXT: v_or_b32_e32 v13, v50, v17
; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v18
; GCN-NEXT: v_or_b32_e32 v15, v51, v20
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: ; implicit-def: $vgpr2
; GCN-NEXT: ; implicit-def: $vgpr4
; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: ; implicit-def: $vgpr8
; GCN-NEXT: ; implicit-def: $vgpr9
; GCN-NEXT: ; implicit-def: $vgpr10
; GCN-NEXT: ; implicit-def: $vgpr12
; GCN-NEXT: ; implicit-def: $vgpr14
; GCN-NEXT: ; implicit-def: $vgpr16
; GCN-NEXT: ; implicit-def: $vgpr17
; GCN-NEXT: ; implicit-def: $vgpr18
; GCN-NEXT: ; implicit-def: $vgpr20
; GCN-NEXT: ; implicit-def: $vgpr22
; GCN-NEXT: ; implicit-def: $vgpr24
; GCN-NEXT: ; implicit-def: $vgpr25
; GCN-NEXT: ; implicit-def: $vgpr26
; GCN-NEXT: ; implicit-def: $vgpr28
; GCN-NEXT: ; implicit-def: $vgpr30
; GCN-NEXT: ; implicit-def: $vgpr36
; GCN-NEXT: ; implicit-def: $vgpr52
; GCN-NEXT: ; implicit-def: $vgpr37
; GCN-NEXT: ; implicit-def: $vgpr38
; GCN-NEXT: ; implicit-def: $vgpr53
; GCN-NEXT: ; implicit-def: $vgpr39
; GCN-NEXT: ; implicit-def: $vgpr48
; GCN-NEXT: ; implicit-def: $vgpr54
; GCN-NEXT: ; implicit-def: $vgpr49
; GCN-NEXT: ; implicit-def: $vgpr50
; GCN-NEXT: ; implicit-def: $vgpr55
; GCN-NEXT: ; implicit-def: $vgpr51
; GCN-NEXT: .LBB55_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB55_4
; GCN-NEXT: ; %bb.3: ; %cmp.true
; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; GCN-NEXT: s_movk_i32 s6, 0x300
; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v30
; GCN-NEXT: s_mov_b32 s7, 0x3000000
; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; GCN-NEXT: v_lshlrev_b32_e32 v11, 8, v25
; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v26
; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v20
; GCN-NEXT: v_add_i32_e32 v19, vcc, 3, v22
; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; GCN-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3
; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5
; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7
; GCN-NEXT: v_and_b32_e32 v13, 0xff, v13
; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15
; GCN-NEXT: v_and_b32_e32 v19, 0xff, v19
; GCN-NEXT: v_and_b32_e32 v16, 0xff, v16
; GCN-NEXT: v_and_b32_e32 v18, 0xff, v18
; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12
; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14
; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8
; GCN-NEXT: v_and_b32_e32 v10, 0xff, v10
; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4
; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6
; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2
; GCN-NEXT: v_or_b32_e32 v3, v55, v3
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_or_b32_e32 v7, v11, v7
; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v13
; GCN-NEXT: v_or_b32_e32 v13, v54, v15
; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v19
; GCN-NEXT: v_or_b32_e32 v16, v17, v16
; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; GCN-NEXT: v_or_b32_e32 v12, v53, v12
; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GCN-NEXT: v_or_b32_e32 v8, v9, v8
; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; GCN-NEXT: v_or_b32_e32 v4, v52, v4
; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x300, v3
; GCN-NEXT: v_or_b32_e32 v3, v51, v5
; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v7
; GCN-NEXT: v_or_b32_e32 v7, v50, v11
; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v13
; GCN-NEXT: v_or_b32_e32 v11, v49, v15
; GCN-NEXT: v_add_i32_e32 v13, vcc, s6, v16
; GCN-NEXT: v_or_b32_e32 v15, v48, v17
; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; GCN-NEXT: v_or_b32_e32 v14, v39, v14
; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; GCN-NEXT: v_or_b32_e32 v9, v38, v9
; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; GCN-NEXT: v_or_b32_e32 v6, v37, v6
; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; GCN-NEXT: v_or_b32_e32 v1, v36, v1
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_or_b32_e32 v2, v3, v2
; GCN-NEXT: v_or_b32_e32 v3, v7, v5
; GCN-NEXT: v_or_b32_e32 v5, v11, v10
; GCN-NEXT: v_or_b32_e32 v7, v15, v13
; GCN-NEXT: v_or_b32_e32 v10, v14, v12
; GCN-NEXT: v_or_b32_e32 v8, v9, v8
; GCN-NEXT: v_or_b32_e32 v4, v6, v4
; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, s7, v5
; GCN-NEXT: v_add_i32_e32 v9, vcc, s7, v7
; GCN-NEXT: v_add_i32_e32 v10, vcc, s7, v10
; GCN-NEXT: v_add_i32_e32 v7, vcc, s7, v8
; GCN-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v0
; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v0
; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v4
; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v7
; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v10
; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v9
; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v9
; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v6
; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v2
; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v2
; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v1
; GCN-NEXT: .LBB55_4: ; %end
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v31
; GCN-NEXT: v_mov_b32_e32 v1, v35
; GCN-NEXT: v_mov_b32_e32 v2, v21
; GCN-NEXT: v_mov_b32_e32 v4, v33
; GCN-NEXT: v_mov_b32_e32 v6, v19
; GCN-NEXT: v_mov_b32_e32 v8, v23
; GCN-NEXT: v_mov_b32_e32 v9, v27
; GCN-NEXT: v_mov_b32_e32 v10, v29
; GCN-NEXT: v_mov_b32_e32 v12, v32
; GCN-NEXT: v_mov_b32_e32 v14, v34
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v33, v2
; VI-NEXT: v_mov_b32_e32 v31, v0
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v32, v6
; VI-NEXT: v_mov_b32_e32 v34, v4
; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v3
; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v5
; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v7
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v9
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v11
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v15
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; VI-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; VI-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; VI-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; VI-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; VI-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v39, 8, v2
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB55_3
; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB55_3: ; %cmp.false
; VI-NEXT: v_or_b32_sdwa v0, v31, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v33, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v32, v38 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v10, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v18, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v30, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB55_2
; VI-NEXT: .LBB55_4: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v30
; VI-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v1, 0x300
; VI-NEXT: v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v28
; VI-NEXT: v_or_b32_sdwa v28, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v26
; VI-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v24
; VI-NEXT: v_or_b32_sdwa v24, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v22
; VI-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v20
; VI-NEXT: v_or_b32_sdwa v20, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v18
; VI-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v16
; VI-NEXT: v_or_b32_sdwa v16, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v14
; VI-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v12
; VI-NEXT: v_or_b32_sdwa v12, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v10
; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v8
; VI-NEXT: v_or_b32_sdwa v8, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v32
; VI-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v34
; VI-NEXT: v_or_b32_sdwa v10, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_add_u16_e32 v0, 3, v33
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
; VI-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_add_u16_e32 v8, 0x300, v12
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v1, 3, v31
; VI-NEXT: v_or_b32_e32 v3, v8, v3
; VI-NEXT: v_add_u16_e32 v8, 0x300, v16
; VI-NEXT: v_or_b32_sdwa v1, v35, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_e32 v4, v8, v4
; VI-NEXT: v_add_u16_e32 v8, 0x300, v20
; VI-NEXT: v_add_u16_e32 v1, 0x300, v1
; VI-NEXT: v_or_b32_e32 v5, v8, v5
; VI-NEXT: v_add_u16_e32 v8, 0x300, v24
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_u16_e32 v1, 0x300, v10
; VI-NEXT: v_or_b32_e32 v6, v8, v6
; VI-NEXT: v_add_u16_e32 v8, 0x300, v28
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v32i8_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v32, v2
; GFX9-NEXT: v_mov_b32_e32 v33, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v34, v6
; GFX9-NEXT: v_mov_b32_e32 v31, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v9
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v11
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v19
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v2
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB55_3
; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB55_4
; GFX9-NEXT: .LBB55_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB55_3: ; %cmp.false
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: v_or_b32_sdwa v1, v31, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v34, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
; GFX9-NEXT: v_or_b32_sdwa v2, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
; GFX9-NEXT: v_or_b32_sdwa v3, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v14, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v5, v18, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v8, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr13
; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB55_2
; GFX9-NEXT: .LBB55_4: ; %cmp.true
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v0, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_or_b32_sdwa v0, v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v10
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v36, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v10, v35, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v10, v0, s6
; GFX9-NEXT: v_perm_b32 v1, v9, v1, s6
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v11, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v15, v4, s6
; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v32i8_to_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4
; GFX11-NEXT: scratch_load_u16 v2, off, s32
; GFX11-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
; GFX11-NEXT: v_lshlrev_b16 v37, 8, v1
; GFX11-NEXT: v_lshlrev_b16 v35, 8, v3
; GFX11-NEXT: v_lshlrev_b16 v38, 8, v5
; GFX11-NEXT: v_lshlrev_b16 v36, 8, v7
; GFX11-NEXT: v_lshlrev_b16 v48, 8, v9
; GFX11-NEXT: v_lshlrev_b16 v9, 8, v11
; GFX11-NEXT: v_lshlrev_b16 v39, 8, v13
; GFX11-NEXT: v_lshlrev_b16 v11, 8, v15
; GFX11-NEXT: v_lshlrev_b16 v15, 8, v17
; GFX11-NEXT: v_lshlrev_b16 v13, 8, v19
; GFX11-NEXT: v_lshlrev_b16 v49, 8, v21
; GFX11-NEXT: v_lshlrev_b16 v17, 8, v23
; GFX11-NEXT: v_lshlrev_b16 v21, 8, v25
; GFX11-NEXT: v_lshlrev_b16 v19, 8, v27
; GFX11-NEXT: v_lshlrev_b16 v23, 8, v29
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b16 v25, 8, v2
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB55_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execnz .LBB55_4
; GFX11-NEXT: .LBB55_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3: ; %cmp.false
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v33
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v34
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v32
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v31
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v0, v0, v37
; GFX11-NEXT: v_or_b32_e32 v1, v1, v35
; GFX11-NEXT: v_or_b32_e32 v2, v2, v38
; GFX11-NEXT: v_or_b32_e32 v3, v3, v36
; GFX11-NEXT: v_or_b32_e32 v4, v4, v48
; GFX11-NEXT: v_or_b32_e32 v5, v5, v9
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v12
; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v16
; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v20
; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v22
; GFX11-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX11-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v26
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v28
; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v30
; GFX11-NEXT: v_or_b32_e32 v3, v3, v39
; GFX11-NEXT: v_or_b32_e32 v5, v5, v15
; GFX11-NEXT: v_or_b32_e32 v6, v6, v13
; GFX11-NEXT: v_or_b32_e32 v7, v7, v49
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
; GFX11-NEXT: v_or_b32_e32 v9, v9, v21
; GFX11-NEXT: v_or_b32_e32 v10, v10, v19
; GFX11-NEXT: v_or_b32_e32 v11, v11, v23
; GFX11-NEXT: v_or_b32_e32 v12, v12, v25
; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
; GFX11-NEXT: ; implicit-def: $vgpr33
; GFX11-NEXT: ; implicit-def: $vgpr34
; GFX11-NEXT: ; implicit-def: $vgpr32
; GFX11-NEXT: ; implicit-def: $vgpr31
; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: ; implicit-def: $vgpr16
; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: ; implicit-def: $vgpr37
; GFX11-NEXT: ; implicit-def: $vgpr35
; GFX11-NEXT: ; implicit-def: $vgpr38
; GFX11-NEXT: ; implicit-def: $vgpr36
; GFX11-NEXT: ; implicit-def: $vgpr48
; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: ; implicit-def: $vgpr39
; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: ; implicit-def: $vgpr15
; GFX11-NEXT: ; implicit-def: $vgpr13
; GFX11-NEXT: ; implicit-def: $vgpr49
; GFX11-NEXT: ; implicit-def: $vgpr17
; GFX11-NEXT: ; implicit-def: $vgpr21
; GFX11-NEXT: ; implicit-def: $vgpr19
; GFX11-NEXT: ; implicit-def: $vgpr23
; GFX11-NEXT: ; implicit-def: $vgpr25
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB55_2
; GFX11-NEXT: .LBB55_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-NEXT: v_add_nc_u16 v2, v24, 3
; GFX11-NEXT: v_add_nc_u16 v3, v26, 3
; GFX11-NEXT: v_add_nc_u16 v4, v20, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v1, v25, v1
; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-NEXT: v_or_b32_e32 v2, v21, v2
; GFX11-NEXT: v_add_nc_u16 v7, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v19, v3
; GFX11-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v49, v4
; GFX11-NEXT: v_add_nc_u16 v6, 0x300, v2
; GFX11-NEXT: v_or_b32_e32 v2, v17, v5
; GFX11-NEXT: v_add_nc_u16 v17, 0x300, v0
; GFX11-NEXT: v_add_nc_u16 v0, v16, 3
; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v1, v12, 3
; GFX11-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: v_add_nc_u16 v12, 0x300, v2
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_or_b32_e32 v0, v15, v0
; GFX11-NEXT: v_add_nc_u16 v2, v8, 3
; GFX11-NEXT: v_or_b32_e32 v1, v39, v1
; GFX11-NEXT: v_add_nc_u16 v14, v31, 3
; GFX11-NEXT: v_add_nc_u16 v10, v10, 3
; GFX11-NEXT: v_add_nc_u16 v8, 0x300, v0
; GFX11-NEXT: v_or_b32_e32 v0, v13, v3
; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v1
; GFX11-NEXT: v_or_b32_e32 v1, v11, v4
; GFX11-NEXT: v_add_nc_u16 v4, v32, 3
; GFX11-NEXT: v_add_nc_u16 v11, v33, 3
; GFX11-NEXT: v_add_nc_u16 v13, v34, 3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-NEXT: v_or_b32_e32 v2, v48, v2
; GFX11-NEXT: v_or_b32_e32 v4, v38, v4
; GFX11-NEXT: v_or_b32_e32 v11, v37, v11
; GFX11-NEXT: v_or_b32_e32 v13, v35, v13
; GFX11-NEXT: v_or_b32_e32 v14, v36, v14
; GFX11-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-NEXT: v_add_nc_u16 v11, 0x300, v13
; GFX11-NEXT: v_add_nc_u16 v13, 0x300, v14
; GFX11-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-NEXT: v_add_nc_u16 v14, 0x300, v1
; GFX11-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-NEXT: v_perm_b32 v0, v11, v10, 0x5040100
; GFX11-NEXT: v_perm_b32 v1, v13, v4, 0x5040100
; GFX11-NEXT: v_perm_b32 v2, v9, v2, 0x5040100
; GFX11-NEXT: v_perm_b32 v3, v14, v3, 0x5040100
; GFX11-NEXT: v_perm_b32 v4, v15, v8, 0x5040100
; GFX11-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v19, v7, 0x5040100
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <32 x i8> %a, splat (i8 3)
%a2 = bitcast <32 x i8> %a1 to <16 x bfloat>
br label %end
cmp.false:
%a3 = bitcast <32 x i8> %a to <16 x bfloat>
br label %end
end:
%phi = phi <16 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <16 x bfloat> %phi
}