| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s |
| |
| define <7 x float> @bitcast_v7i32_to_v7f32(<7 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v7i32_to_v7f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v7i32_to_v7f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v7i32_to_v7f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v7i32_to_v7f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB0_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <7 x i32> %a, splat (i32 3) |
| %a2 = bitcast <7 x i32> %a1 to <7 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <7 x i32> %a to <7 x float> |
| br label %end |
| |
| end: |
| %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <7 x float> %phi |
| } |
| |
| define <7 x i32> @bitcast_v7f32_to_v7i32(<7 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v7f32_to_v7i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v7f32_to_v7i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v7f32_to_v7i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v7f32_to_v7i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5 |
| ; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3 |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <7 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <7 x float> %a1 to <7 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <7 x float> %a to <7 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <7 x i32> %phi |
| } |
