tree 055b71c73d3c9bdad81c572562273882c3496538
parent 69d757c0e8ffc5b49fda10df38e470a56d616ef4
author Francesco Petrogalli <francesco.petrogalli@arm.com> 1580243872 +0000
committer Francesco Petrogalli <francesco.petrogalli@arm.com> 1582315354 +0000

[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

1. Masked load and stores:
     * Sign and zero extended load and truncated stores.
     * No extension or truncation.
2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254