)]}'
{
  "commit": "dc2ed0043295a397d680db091c2033a51d21e32e",
  "tree": "0403d11d1c9e2d3ff2b8c22175605b09b9978027",
  "parents": [
    "4e5e65e55dc5a5ffc6e3db321df7f118e1c42d38"
  ],
  "author": {
    "name": "Luke Lau",
    "email": "luke@igalia.com",
    "time": "Fri Sep 05 08:25:48 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Sep 05 00:25:48 2025 +0000"
  },
  "message": "[RISCV] Handle non uimm5 VL constants in isVLKnownLE (#156639)\n\nIf a VL operand is \u003e 31 then it will be materialized into an ADDI $x0,\nimm. We can reason about it by peeking at the virtual register\ndefinition which allows RISCVVectorPeephole and RISCVVLOptimizer to\ncatch more cases.\n\nThere\u0027s a separate issue with RISCVVLOptimizer where the materialized\nimmediate may not always dominate the instruction we want to reduce the\nVL of, but this is left to another patch.",
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