fix merge conflict errors
diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h
index ac494ae..6bf505e 100644
--- a/llvm/include/llvm/Passes/PassBuilder.h
+++ b/llvm/include/llvm/Passes/PassBuilder.h
@@ -994,6 +994,8 @@
const PassBuilder &);
Expected<bool> parseMachineBlockPlacementPassOptions(StringRef Params,
const PassBuilder &);
+Expected<bool> parseVirtRegRewriterPassOptions(StringRef Params,
+ const PassBuilder &);
}
#endif
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 93d4546..57b5ee1 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1465,8 +1465,8 @@
return AllowTailMerge;
}
-Expected<bool> llvm::parseVirtRegRewriterPassOptions(const PassBuilder &PB,
- StringRef Params) {
+Expected<bool> llvm::parseVirtRegRewriterPassOptions(StringRef Params,
+ const PassBuilder &) {
bool ClearVirtRegs = true;
if (!Params.empty()) {
ClearVirtRegs = !Params.consume_front("no-");
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1307b0e..e8dc939 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2168,7 +2168,8 @@
addPass(GCNPreRALongBranchRegPass());
- addPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}));
+ addRegAllocPassOrOpt(
+ addPass, []() { return RAGreedyPass({onlyAllocateSGPRs, "sgpr"}); });
// Commit allocated register changes. This is mostly necessary because too
// many things rely on the use lists of the physical registers, such as the
@@ -2188,21 +2189,20 @@
addPass(SIPreAllocateWWMRegsPass());
// For allocating other wwm register operands.
- // addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
- addPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}));
+ addRegAllocPassOrOpt(
+ addPass, []() { return RAGreedyPass({onlyAllocateWWMRegs, "wwm"}); });
addPass(SILowerWWMCopiesPass());
addPass(VirtRegRewriterPass(false));
addPass(AMDGPUReserveWWMRegsPass());
// For allocating per-thread VGPRs.
- // addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
- addPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}));
-
+ addRegAllocPassOrOpt(
+ addPass, []() { return RAGreedyPass({onlyAllocateVGPRs, "vgpr"}); });
addPreRewrite(addPass);
addPass(VirtRegRewriterPass(true));
- // TODO: addPass(AMDGPUMarkLastScratchLoadPass());
+ addPass(AMDGPUMarkLastScratchLoadPass());
return Error::success();
}
@@ -2252,47 +2252,6 @@
addPass(BranchRelaxationPass());
}
-Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
- AddMachinePass &addPass) const {
- addPass(GCNPreRALongBranchRegPass());
-
- addRegAllocPassOrOpt(
- addPass, []() { return RAGreedyPass({onlyAllocateSGPRs, "sgpr"}); });
-
- // Commit allocated register changes. This is mostly necessary because too
- // many things rely on the use lists of the physical registers, such as the
- // verifier. This is only necessary with allocators which use LiveIntervals,
- // since FastRegAlloc does the replacements itself.
- // TODO: addPass(VirtRegRewriterPass(false));
-
- // At this point, the sgpr-regalloc has been done and it is good to have the
- // stack slot coloring to try to optimize the SGPR spill stack indices before
- // attempting the custom SGPR spill lowering.
- addPass(StackSlotColoringPass());
-
- // Equivalent of PEI for SGPRs.
- addPass(SILowerSGPRSpillsPass());
-
- // To Allocate wwm registers used in whole quad mode operations (for shaders).
- addPass(SIPreAllocateWWMRegsPass());
-
- // For allocating other wwm register operands.
- addRegAllocPassOrOpt(
- addPass, []() { return RAGreedyPass({onlyAllocateWWMRegs, "wwm"}); });
- addPass(SILowerWWMCopiesPass());
- addPass(VirtRegRewriterPass(false));
- addPass(AMDGPUReserveWWMRegsPass());
-
- // For allocating per-thread VGPRs.
- addRegAllocPassOrOpt(
- addPass, []() { return RAGreedyPass({onlyAllocateVGPRs, "vgpr"}); });
-
- // TODO: addPreRewrite();
- addPass(VirtRegRewriterPass(false));
-
- // TODO: addPass(AMDGPUMarkLastScratchLoadPass());
- return Error::success();
-}
bool AMDGPUCodeGenPassBuilder::isPassEnabled(const cl::opt<bool> &Opt,
CodeGenOptLevel Level) const {
