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fuchsia / third_party / llvm-project / a336055ddb4290b953871d1714159de4b70670a8 / . / llvm / test / Transforms / LoopVectorize / RISCV
tree: 858dbf602cfab28f0e1a9efed4aee8cb70b770c7 [path history] [tgz]
  1. defaults.ll
  2. divrem.ll
  3. force-vect-msg.ll
  4. illegal-type.ll
  5. inloop-reduction.ll
  6. interleaved-accesses-zve32x.ll
  7. interleaved-accesses.ll
  8. interleaved-cost.ll
  9. lit.local.cfg
  10. lmul.ll
  11. low-trip-count.ll
  12. mask-index-type.ll
  13. masked_gather_scatter.ll
  14. ordered-reduction.ll
  15. pr87378-vpinstruction-or-drop-poison-generating-flags.ll
  16. reg-usage.ll
  17. riscv-interleaved.ll
  18. riscv-unroll.ll
  19. riscv-vector-reverse.ll
  20. safe-dep-distance.ll
  21. scalable-basics.ll
  22. scalable-reductions.ll
  23. scalable-tailfold.ll
  24. scalable-vf-hint.ll
  25. select-cmp-reduction.ll
  26. short-trip-count.ll
  27. strided-accesses.ll
  28. uniform-load-store.ll
  29. unroll-in-loop-vectorizer.ll
  30. vectorize-force-tail-with-evl-gather-scatter.ll
  31. vectorize-force-tail-with-evl-interleave.ll
  32. vectorize-force-tail-with-evl-iv32.ll
  33. vectorize-force-tail-with-evl-masked-loadstore.ll
  34. vectorize-force-tail-with-evl-no-masking.ll
  35. vectorize-force-tail-with-evl-reverse-load-store.ll
  36. vectorize-vp-intrinsics.ll
  37. vplan-vp-intrinsics.ll
  38. zvl32b.ll