llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+v %s -o - \
; RUN:     -verify-machineinstrs | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+v %s -o - \
; RUN:     -verify-machineinstrs | FileCheck %s

define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl1re32.v v8, (a1)
; CHECK-NEXT:    vl1re32.v v9, (a2)
; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v9
; CHECK-NEXT:    vs1r.v v8, (a0)
; CHECK-NEXT:    ret
  %va = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pa
  %vb = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pb
  %vc = add <vscale x 2 x i32> %va, %vb
  store <vscale x 2 x i32> %vc, <vscale x 2 x i32> *%pc
  ret void
}

define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl2re32.v v8, (a1)
; CHECK-NEXT:    vl2re32.v v10, (a2)
; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v10
; CHECK-NEXT:    vs2r.v v8, (a0)
; CHECK-NEXT:    ret
  %va = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pa
  %vb = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pb
  %vc = add <vscale x 4 x i32> %va, %vb
  store <vscale x 4 x i32> %vc, <vscale x 4 x i32> *%pc
  ret void
}

define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl4re32.v v8, (a1)
; CHECK-NEXT:    vl4re32.v v12, (a2)
; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v12
; CHECK-NEXT:    vs4r.v v8, (a0)
; CHECK-NEXT:    ret
  %va = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pa
  %vb = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pb
  %vc = add <vscale x 8 x i32> %va, %vb
  store <vscale x 8 x i32> %vc, <vscale x 8 x i32> *%pc
  ret void
}

define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <vscale x 16 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl8re32.v v8, (a1)
; CHECK-NEXT:    vl8re32.v v16, (a2)
; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v16
; CHECK-NEXT:    vs8r.v v8, (a0)
; CHECK-NEXT:    ret
  %va = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pa
  %vb = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pb
  %vc = add <vscale x 16 x i32> %va, %vb
  store <vscale x 16 x i32> %vc, <vscale x 16 x i32> *%pc
  ret void
}

define void @vadd_vint32mf2(<vscale x 1 x i32> *%pc, <vscale x 1 x i32> *%pa, <vscale x 1 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32mf2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a1)
; CHECK-NEXT:    vle32.v v9, (a2)
; CHECK-NEXT:    vadd.vv v8, v8, v9
; CHECK-NEXT:    vse32.v v8, (a0)
; CHECK-NEXT:    ret
  %va = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pa
  %vb = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pb
  %vc = add <vscale x 1 x i32> %va, %vb
  store <vscale x 1 x i32> %vc, <vscale x 1 x i32> *%pc
  ret void
}