commit | 822b9c971be6784fe3dc04f4a7926834c1c818d3 | [log] [tgz] |
---|---|---|
author | Roman Lebedev <lebedev.ri@gmail.com> | Sat May 18 12:59:56 2019 +0000 |
committer | Roman Lebedev <lebedev.ri@gmail.com> | Sat May 18 12:59:56 2019 +0000 |
tree | ab06903c53a401fb1d747ee6f5c3401f67374888 | |
parent | f40c18b628f3b0008acf4f9ac0102f103b690cc2 [diff] |
UpdateTestChecks: arm64-eabi handlind Summary: Was looking into supporting `(srl (shl x, c1), c2)` with c1 != c2 in dagcombiner, this test changes, but makes `update_llc_test_checks.py` unhappy Reviewers: RKSimon Reviewed By: RKSimon Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62097 llvm-svn: 361100