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fuchsia / third_party / llvm-project / 3e4788377bb29ed389b46521fcba0d06aa985bcf / . / llvm / test / Transforms / LoopVectorize / RISCV
tree: e78cdbc96b8e2becf6272dbbe36b4efc2a4d797d [path history] [tgz]
  1. blocks-with-dead-instructions.ll
  2. dead-ops-cost.ll
  3. defaults.ll
  4. divrem.ll
  5. evl-compatible-loops.ll
  6. first-order-recurrence-scalable-vf1.ll
  7. force-vect-msg.ll
  8. illegal-type.ll
  9. induction-costs.ll
  10. inloop-reduction.ll
  11. interleaved-accesses-zve32x.ll
  12. interleaved-accesses.ll
  13. interleaved-cost.ll
  14. lit.local.cfg
  15. lmul.ll
  16. low-trip-count.ll
  17. mask-index-type.ll
  18. masked_gather_scatter.ll
  19. only-compute-cost-for-vplan-vfs.ll
  20. ordered-reduction.ll
  21. pr87378-vpinstruction-or-drop-poison-generating-flags.ll
  22. pr88802.ll
  23. reg-usage.ll
  24. riscv-interleaved.ll
  25. riscv-unroll.ll
  26. riscv-vector-reverse.ll
  27. safe-dep-distance.ll
  28. scalable-basics.ll
  29. scalable-reductions.ll
  30. scalable-tailfold.ll
  31. scalable-vf-hint.ll
  32. select-cmp-reduction.ll
  33. short-trip-count.ll
  34. strided-accesses.ll
  35. truncate-to-minimal-bitwidth-cost.ll
  36. uniform-load-store.ll
  37. unroll-in-loop-vectorizer.ll
  38. vectorize-force-tail-with-evl-cond-reduction.ll
  39. vectorize-force-tail-with-evl-gather-scatter.ll
  40. vectorize-force-tail-with-evl-inloop-reduction.ll
  41. vectorize-force-tail-with-evl-interleave.ll
  42. vectorize-force-tail-with-evl-intermediate-store.ll
  43. vectorize-force-tail-with-evl-iv32.ll
  44. vectorize-force-tail-with-evl-masked-loadstore.ll
  45. vectorize-force-tail-with-evl-no-masking.ll
  46. vectorize-force-tail-with-evl-ordered-reduction.ll
  47. vectorize-force-tail-with-evl-reduction.ll
  48. vectorize-force-tail-with-evl-reverse-load-store.ll
  49. vectorize-force-tail-with-evl-safe-dep-distance.ll
  50. vectorize-vp-intrinsics.ll
  51. vf-will-not-generate-any-vector-insts.ll
  52. vplan-vp-intrinsics-reduction.ll
  53. vplan-vp-intrinsics.ll
  54. zvl32b.ll