[RISCV] Add seto pattern expansion
Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and
`fcmp ord` would be inefficient due to an unoptimized double negation.
Differential Revision: https://reviews.llvm.org/D59699
llvm-svn: 357378
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a41a87a..63117ba 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -137,9 +137,9 @@
setOperationAction(ISD::CTPOP, XLenVT, Expand);
ISD::CondCode FPCCToExtend[] = {
- ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
- ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
- ISD::SETGT, ISD::SETGE, ISD::SETNE};
+ ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
+ ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
+ ISD::SETGE, ISD::SETNE};
ISD::NodeType FPOpToExtend[] = {
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index fdb9a41..fe38c4f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -270,6 +270,10 @@
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
+def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
+ (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
+ (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
+
def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
(SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
(FEQ_D FPR64:$rs2, FPR64:$rs2)),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 17ba146..7c957a9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -324,6 +324,10 @@
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
+def : Pat<(seto FPR32:$rs1, FPR32:$rs2),
+ (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
+ (FEQ_S FPR32:$rs2, FPR32:$rs2))>;
+
def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
(SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
(FEQ_S FPR32:$rs2, FPR32:$rs2)),
diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
index 275c4aa..1c8b867 100644
--- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
@@ -322,8 +322,6 @@
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1: # %if.else
@@ -344,8 +342,6 @@
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1: # %if.else
@@ -377,8 +373,6 @@
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp)
@@ -396,8 +390,6 @@
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp)
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 25c8f6d..0046b59 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -159,8 +159,6 @@
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
@@ -174,8 +172,6 @@
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret
%1 = fcmp one double %a, %b
@@ -196,8 +192,6 @@
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -208,8 +202,6 @@
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 4503c23..321adce 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -221,8 +221,6 @@
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1:
@@ -243,8 +241,6 @@
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1:
@@ -270,8 +266,6 @@
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1
@@ -289,8 +283,6 @@
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1
diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
index 678d738..425da73 100644
--- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -295,8 +295,6 @@
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: # %if.else
@@ -317,8 +315,6 @@
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1: # %if.else
@@ -346,8 +342,6 @@
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp)
@@ -365,8 +359,6 @@
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp)
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
index 16f4418..43a849b 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -124,8 +124,6 @@
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret
;
@@ -138,8 +136,6 @@
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b
@@ -155,8 +151,6 @@
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ord:
@@ -166,8 +160,6 @@
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 3659ed2..ec81c53 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -175,8 +175,6 @@
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB6_2
; RV32IF-NEXT: # %bb.1:
@@ -194,8 +192,6 @@
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB6_2
; RV64IF-NEXT: # %bb.1:
@@ -216,8 +212,6 @@
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1
@@ -232,8 +226,6 @@
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1
