)]}' { "log": [ { "commit": "205022c08c96da668cf0ed919f42e147dddd0bd0", "tree": "5593ae3802ebcabaef11f25088a64bcba892afbb", "parents": [ "38e21134f7363a02b0c348c3fe3ec7e78b3fba9f" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 26 14:04:53 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 26 14:07:50 2026 -0700" }, "message": "[libyuv] Add AVX-512 VNNI row functions for ARGB to YUV and Gray\n\nAdd AVX-512 VNNI (VPDPBUSD / _mm512_dpbusd_epi32) row kernels for 64-bit\nx86 targets alongside existing AVX-512BW implementations in both\nrow_gcc.cc (inline assembly) and row_win.cc (C++ intrinsics):\n\n- ARGBToYMatrixRow_AVX512VNNI and ARGBToYMatrixRow_Any_AVX512VNNI:\n Pre-computes the 32-bit signed-pixel bias once per row and replaces\n vpmaddubsw + vpmaddwd + vpaddw with a single vpdpbusd per 16 pixels.\n- ARGBToUV444MatrixRow_AVX512VNNI and\n ARGBToUV444MatrixRow_Any_AVX512VNNI: Loads 64 ARGB pixels once instead\n of twice and computes 32-bit U and V dot products directly via\n vpdpbusd with signed UV matrix coefficients.\n- ARGBToUVMatrixRow_AVX512VNNI: Computes 2x2 box-filtered ARGB to U and\n V conversion using vpdpbusd with k-masked tail handling for arbitrary\n widths.\n- ARGBGrayRow_AVX512VNNI: Computes BT.601 grayscale luminance using a\n single vpdpbusd per 16 pixels, broadcasts Y to RGB via vpshufb, and\n preserves alpha via vpternlogd with k-masked tail handling.\n- Wire runtime dispatch via TestCpuFlag(kCpuHasAVX512VNNI) across\n convert.cc, convert_from_argb.cc, and planar_functions.cc.\n\nAdd AVX512VNNIVBMI variants of the Y, UV444 and UV kernels. These use\nboth AVX-512 VNNI (vpdpbusd) and AVX-512 VBMI (vpermt2b) and are only\nselected when the CPU has both features; there are no VBMI versions\nwithout VNNI. The AVX512VNNI kernels remain for CPUs with VNNI but no\nVBMI (Cascade Lake, Cooper Lake).\n\n- The 32-bit sums are always in [0, 65535], so Y, U and V are byte 1 of\n each int32. Two vpermt2b gather 64 results from 4 accumulators,\n replacing vpackusdw/vpackssdw + vpsrlw + vpackuswb + vpermd.\n- U and V accumulators start at ~kAddUV so they hold ~(kAddUV - dot).\n The inverse is folded into the vpternlogd that merges the two\n 256-bit halves. kAddUV is loaded from ArgbConstants rather than\n hard coded as 0x8000.\n- Y folds the source loads into vpxorq.\n- row_win.cc hides the vpermt2b indices from clang, which otherwise\n constant folds them into a longer vpshufb + vpor + vpermd sequence.\n\nPerformance (1280x720, 5000 iterations, AVX512BW -\u003e AVX512VNNI):\nuArch / Benchmark AVX512BW AVX512VNNI Speedup\n--------------------------- -------- ---------- -------\nIntel Ice Lake ARGBToI420 941 ms 862 ms +9.2%\nIntel Ice Lake ARGBToI422 1059 ms 947 ms +11.8%\nIntel Ice Lake ARGBToI444 1140 ms 1038 ms +9.8%\nIntel Ice Lake ARGBGray 357 ms 273 ms +30.8%\nIntel Sapphire Rapids GrayTo 317 ms 218 ms +45.4%\nIntel Emerald Rapids GrayTo 310 ms 213 ms +45.5%\nIntel Granite Rapids GrayTo 349 ms 241 ms +44.8%\nAMD Zen 4 ARGBToI420 648 ms 517 ms +25.3%\nAMD Zen 4 ARGBToI444 695 ms 526 ms +32.1%\nAMD Zen 4 ARGBGray 403 ms 227 ms +77.5%\nAMD Zen 5 ARGBToI422 460 ms 403 ms +14.1%\nAMD Zen 5 ARGBToI444 382 ms 321 ms +19.0%\n\nPerformance (row_gcc, AVX512VNNI -\u003e AVX512VNNIVBMI):\nuArch / Benchmark AVX512VNNI VNNIVBMI Speedup\n---------------------------- ---------- -------- -------\nAMD Zen 6 ARGBToI420 1280x720 327 ms 284 ms +15.1%\nAMD Zen 6 ARGBToI422 1280x720 372 ms 330 ms +12.7%\nAMD Zen 6 ARGBToI444 1280x720 357 ms 334 ms +6.9%\nAMD Zen 6 ARGBToI400 256x24 94 ms 76 ms +23.7%\nAMD Zen 5 ARGBToI422 1280x720 406 ms 350 ms +16.0%\nAMD Zen 5 ARGBToI444 1280x720 330 ms 301 ms +9.6%\nAMD Zen 5 ARGBToI400 256x24 100 ms 90 ms +11.1%\nAMD Zen 4 ARGBToI420 1280x720 631 ms 540 ms +16.9%\nAMD Zen 4 ARGBToI422 1280x720 993 ms 825 ms +20.4%\nAMD Zen 4 ARGBToI400 256x24 245 ms 218 ms +12.4%\nIntel GNR ARGBToI422 256x24 654 ms 616 ms +6.2%\nIntel SPR ARGBToI422 256x24 653 ms 613 ms +6.5%\nIntel GNR, EMR, SPR and Ice Lake are within +/-3% at 1280x720.\n\nR\u003drrwinterton@gmail.com\n\nBug: none\nTest: out/Release/libyuv_unittest --gtest_filter\u003d*ARGBToI4*:*ARGBGray*\nTest: LIBYUV_DISABLE_AVX512VBMI\u003d1 out/Release/libyuv_unittest\nTest: sde64 -gnr / -clx with is_msan\u003dtrue (row_win.cc)\nChange-Id: Ia7a37b39dd2948fe4055a8a7694dd1ff8ac3e55c\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8647811\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "38e21134f7363a02b0c348c3fe3ec7e78b3fba9f", "tree": "b3559951a6740d2a4ae462d1937dfb26c5a16178", "parents": [ "47ba8e2160b71a7cf95c0720cd8944ab771e533e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Sat Oct 24 04:43:06 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 26 11:24:16 2026 -0700" }, "message": "[libyuv] Add ARGBOr and ARGBAlphaBlend with multi-platform SIMD\n\nAdd two new planar/row compositing functions for 32-bit ARGB/BGRA\nscanlines:\n\n- ARGBOr / ARGBOrRow_*: Applies a bitwise OR with a 32-bit ARGB mask\n to every pixel (e.g., 0xFF000000 to force opaque alpha for BGRx to\n BGRA conversion). Implemented for C, SSE2, AVX2, AVX-512BW, NEON\n (32/64-bit), SVE2, SME, RVV, WASMSIMD, LSX, LASX, HVX, and Windows\n intrinsics (row_win.cc).\n- ARGBAlphaBlend / ARGBAlphaBlendRow_*: Implements straight-alpha\n (unattenuated) Porter-Duff source-over blending matching PDFium\u0027s\n CompositeRowBgra2Bgra:\n dst_a \u003d back_a + src_a - (back_a * src_a) / 255\n ratio \u003d (src_a * 255) / dst_a\n dst_c \u003d (back_c * (255 - ratio) + src_c * ratio) / 255\n Implemented with bit-exact division by 255 across all 65,536\n (back_a, src_a) pairs for C, SSSE3, AVX2, AVX-512BW, NEON\n (32/64-bit), SVE2, SME, RVV, WASMSIMD, LSX, LASX, HVX, and Windows\n intrinsics (row_win.cc).\n\nARGBOr Performance (2048x64 BGRx-\u003eBGRA scanlines, us per call):\nuArch Before Highway libyuv vs Hwy\n------------------------ ------ ------- ------- ------\nQualcomm Hexagon v81 HVX 259.63 260.97 15.78 16.54x\nSiFive X280 (RVV) 1107.57 72.49 50.70 1.43x\nSiFive X390 (RVV) 1108.82 70.42 52.26 1.35x\n\nARGBAlphaBlend Performance (2048x64 BGRA scanlines, us per call):\nuArch Before Highway libyuv vs Hwy\n------------------------ ------ ------- ------- ------\nIntel Lion Cove (AVX2) 429.79 141.97 41.89 3.39x\nIntel Cougar Cove (AVX2) 516.83 181.98 51.33 3.55x\nIntel Golden Cove (AVX2) 560.31 206.28 67.08 3.08x\nAMD Zen 3 (AVX2) 1025.73 251.09 98.99 2.54x\nWasm SIMD128 (V8) 1014.14 964.83 385.80 2.50x\nApple M6 Super (NEON) 221.90 118.42 46.35 2.55x\nApple M5 Super (NEON) 241.90 130.07 49.60 2.62x\nARM C1-Ultra (SME2) 384.63 112.52 63.62 1.77x\nQualcomm Oryon V3-L (SME) 388.13 154.87 87.65 1.77x\nQualcomm Oryon-L (NEON) 318.28 149.36 57.23 2.61x\nARM Cortex-X4 (SVE2) 675.47 213.56 102.53 2.08x\nARM Cortex-A720 (NEON) 795.85 586.55 235.81 2.49x\nARM Cortex-A520 (NEON) 2360.95 2122.99 787.65 2.70x\nARM Cortex-A35 (ARMv7) 4907.31 5895.04 1474.51 4.00x\nSiFive X280 (RVV) 4145.06 1096.42 596.82 1.84x\nSiFive X390 (RVV) 4144.57 1084.93 597.62 1.82x\nQualcomm Hexagon v81 HVX 4912.03 5786.25 952.19 6.08x\nCoral V4 RVV (1024 px) 50276 c 48992 c 4299 c 11.40x\n\nR\u003dwtc@google.com\n\nBug: none\nChange-Id: If661239826a033e89d4b5c1adc0bfdf048a7a726\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8647895\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "47ba8e2160b71a7cf95c0720cd8944ab771e533e", "tree": "290bcd52a3377e5df3a5df9c499f3e140bd76dad", "parents": [ "64ddbbcddebb945be8c37253978d28af1033b5be" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 20 16:15:50 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Oct 20 21:39:37 2026 -0700" }, "message": "Handle SsimWindowRow remainder in SIMD for AVX512BW, SVE2, SME, RVV\n\nBecause each 8x8 SSIM window spans two 4x4 tiles horizontally,\nnum_windows \u003d (width - 5) \u003e\u003e 2, so aligned widths that are multiples\nof 64 (e.g. 64, 128, 640, 1280, 1920) always have remainder 15\n(num_windows \u0026 15 \u003d\u003d 15).\n\n- Update SsimWindowRow_AVX512BW (compare_gcc.cc and compare_win.cc)\n to handle any remainder (1..15 windows) via k-masking (load_mask\n for the (rem + 1) * 4 tile words and win_mask for the rem window\n scores) and set win_simd_size \u003d 1.\n- Add SsimWindowRow_SVE2, SsimWindowRow_SME, and SsimWindowRow_RVV\n with win_simd_size \u003d 1 using predicated/vl-controlled loops so no\n C code (Ssim4x4Row_C or SsimWindowRow_C) is executed on AVX-512BW,\n SVE2, SME, or RVV CPUs for any image dimensions.\n- Remove LIBYUV_TARGET_AVX512BW __attribute__((target(...))) from\n compare_gcc.cc and GCC_HAS_AVX512 from cpu_support.h, using %%zmm0\n directly in inline assembly.\n\nSSIM Performance (Before vs After):\nuArch / Target Before After Speedup\n-------------------------- --------- --------- -------\nCoral RVV Verilator (64x16) 5302 cyc 2219 cyc 2.39x\nCoral RVV WindowRow (15w) 1854 cyc 308 cyc 6.02x\nApple M6 SME (64x36 10kx) 16.41 ms 4.69 ms 3.50x\nApple M6 SME (720p 1000x) 350.76 ms 66.09 ms 5.31x\n\nR\u003drrwinterton@gmail.com\n\nBug: libyuv:352521931\nChange-Id: Ic7d55184c60611af4a57d113cc4ee3d211debadf\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8621918\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "64ddbbcddebb945be8c37253978d28af1033b5be", "tree": "7ef866d6170c805faaf24df63b5ad9e7a76bc3c9", "parents": [ "94d970860e2ced833ca6ae9de26085bb5f3644cf" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 20 14:30:12 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Oct 20 15:00:52 2026 -0700" }, "message": "[libyuv] Optimize SsimWindowRow with SIMD and use compare_win on x86\n\n- Route 32-bit x86 (__i386__ / _M_IX86) to compare_win.cc intrinsics\n and restrict compare_gcc.cc to 64-bit x86 (__x86_64__), avoiding\n x87 float rounding and enabling SSE2, AVX2, and AVX-512 on 32-bit\n and 64-bit MinGW, GCC, Clang, and MSan (LIBYUV_ENABLE_ROWWIN).\n- Enable AVX-512BW on GCC \u003e\u003d 6 (GCC_HAS_AVX512) and add\n LIBYUV_TARGET_AVX512BW attributes to compare_gcc.cc and\n compare_win.cc.\n- Refactor SsimWindowRow_C and Ssim8x8_C to use int32_t and float,\n and add SsimWindowRow_SSE2, SsimWindowRow_AVX2, and\n SsimWindowRow_AVX512BW in both compare_win.cc and compare_gcc.cc.\n- Update TestSsimAnyWidth, Ssim, and BenchmarkSsim_Opt in\n compare_test.cc to use EXPECT_NEAR and deterministic test patterns\n (identical, different, similar).\n- Update util/compare.cc and linux.mk to compute I420Ssim.\n\nPerformance (BenchmarkSsim_Opt, 1280x720):\nuArch Before After Improvement\nIntel Lion Cove (x64 AVX2) 120.2 us 68.1 us 1.76x\nIntel Skymont (x64 SSE2) 249.6 us 146.8 us 1.70x\nAMD Zen 3 (x64 AVX2) 314.9 us 150.2 us 2.10x\nIntel Lion Cove (MinGW686) 203.7 us 77.9 us 2.61x\nIntel Skymont (MinGW686) 338.8 us 167.5 us 2.02x\nAMD Zen 3 (i686 AVX2) 738.4 us 206.5 us 3.58x\n\nQuality (util/compare on 640x360 I420 test images):\nImage Comparison MSE PSNR SSIM\nIdentical (orig vs orig) 0.00 128.00 dB 1.000000\nSimilar (light +/-3 noise) 4.57 41.53 dB 0.956556\nDegraded (16x16 blocky) 98.18 28.21 dB 0.858893\nVery different (inverted) 11160.29 7.65 dB 0.000181\n\nCo-authored-by: Martin Storsjö \u003cmartin@martin.st\u003e\nBug: b/493910265\nTest: out/Release/libyuv_unittest --gtest_filter\u003d*Ssim*\nChange-Id: I8603dab3f752af32d07ae9039502ca5da5a05425\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8618641\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "94d970860e2ced833ca6ae9de26085bb5f3644cf", "tree": "49a4529d900794caefdcd362513991986ee61c5c", "parents": [ "f249eaa72ffef5766df707bf90cc378243fbbcdd" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue Oct 20 13:31:05 2026 +0300" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 20 14:11:22 2026 -0700" }, "message": "Don\u0027t require exact float matches in TestSsimAnyWidth\n\nFloat computations can get different rounding depending on\nthe implementation. In particular, if the C code is built with\na compiler that uses x87 for float math, it is common that\nthere is a small variance in the results.\n\nThis fixes test failures on GCC i686 mingw targets, where it\npreviously failed like this:\n\n unit_test/compare_test.cc:725: Failure\n Expected equality of these values:\n c_ssim\n Which is: -0.076010095487114751\n opt_ssim\n Which is: -0.076010095487114751\n width 17 offset 1\n [...]\n\nChange-Id: Id109058a89da78e38a8a7224a071a5c2075c66d6\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8615658\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "f249eaa72ffef5766df707bf90cc378243fbbcdd", "tree": "7488ebf5dea112a727c4914a6ed4c0c3bb4435c2", "parents": [ "378bc91324587eedaadde88c81a5d05fada8a581" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 19 16:24:54 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Oct 19 16:46:40 2026 -0700" }, "message": "[libyuv] Fix top 20 bugs and performance issues\n\n1. Fix multi-bit TestCpuFlag(A | B) checks in AYUVToNV12, AYUVToNV21,\n RAWToRGBA, NV12ToRGB24Matrix, NV21ToRGB24Matrix, MergeRGBPlane, and\n MergeXR30Plane to compare \u003d\u003d (A | B) so AVX-512 VBMI/BW kernels are\n not dispatched when AVX512VBMI or AVX512VL is absent.\n2. Fix 2-byte SVE2 heap buffer overflow on odd widths in\n I422ToARGB1555Row_SVE_SC and I422ToARGB4444Row_SVE_SC using\n trn1/trn2 + st2b under .b predicates.\n3. Fix ARGBPolynomialRow_SSE2 to use packssdw before packuswb, and add\n missing vzeroupper to SplitRGBRow_AVX2.\n4. Fix CalcFrameSsim to return 0.0 instead of 0.0 / 0 (NaN) when\n width \u003c\u003d 8 || height \u003c\u003d 8 so I420Ssim stays finite on small frames.\n5. Fix negative-height vertical inversion in ConvertFromI420,\n SplitARGBPlane (when dst_a is NULL), I422Rotate, I010Rotate, and\n I210Rotate.\n6. Fix horizontal flip (negative x/dx) in ScaleFilterCols_NEON (signed\n sbfx #16, #16 offset extraction) and ScaleAddCols1_16_C (shift\n x \u003e\u003e\u003d 16 before indexing src_ptr).\n7. Fix ConvertToARGB odd crop_x chroma alignment in NV12/NV21, src_u\n offset in I420/YV12/J420/H420/U420, and FOURCC_U422 calling\n U422ToARGB instead of H422ToARGB.\n8. Remove dead 14-instruction block in ScaleRowUp2_Bilinear_16_SSE2.\n9. Fix UVScale_16 for src_width \u003d\u003d 1 (P010ToP410/P210ToP410), enable\n and fix column order in TransposeWx4_32_SVE2, fix ByteToFloatRow\n NEON Any BPP (3 -\u003e 4), fix AB64ToARGBRow_Any_*, ScaleColsUp2_SSE2,\n ScaleUVRowDown2Box_SME, and UYVYToARGBRow_SME macro guards, fix SVE2\n loop tail branches (b.lt/b.ge), and remove duplicate HAS_* macros.\n10. Fix ConvertFP16ToFP32Column_NEON loop condition and unsigned b.lo\n underflow on widths \u003c 8 or not multiples of 8.\n11. Fix UYVYToNV12 IS_ALIGNED(awidth, ...) checks and WASM SIMD\n IS_ALIGNED(width, 16) checks in I420ToRGB24Matrix /\n I422ToRGB24Matrix.\n12. Wire SplitUVRow_SVE2, SplitUVRow_LSX, and SplitUVRow_LASX in\n NV24ToARGB.\n13. Fix MJpegDecoder heap buffer overflows in LoadFrame (reallocate\n databuf_[i] when scanlines_size changes), DecodeToBuffers, and\n DecodeToCallback (clamp scanlines_to_copy to lines_left and align\n skip to max_v_samp_factor).\n14. Replace width \u0026 (vl - 1) tail calculations with post-loop remainder\n across 18 SVE2 functions in row_sve.h for non-power-of-2 SVE VL,\n and remove duplicate label 2: in UYVYToARGBRow_SVE_SC.\n15. Handle width \u0026 15 tail pixels in DetileToYUY2_C and validate\n IS_POWEROFTWO(tile_height) in DetileSplitUVPlane and DetileToYUY2.\n16. Avoid signed 32-bit overflow in DivideRow_16_C and C16TO8, fix\n ClampFloatToZero_SSE2 pointer increment (lea 0x4) and loop counter\n (sub $0x1), and initialize xmm3 in ARGBCopyYToAlphaRow_SSE2.\n17. Check max leaf 7 subleaf and max extended CPUID leaf in GetCpuFlags\n before querying subleaf 7:1 and extended leaf 0x80000021.\n18. Free plane_u on error in I422ToNV21, and fix 4x/2x scratch row\n over-allocation in ScaleARGBBilinearDown and ScaleUVBilinearDown.\n19. Add ARGBSetRow_RVV and ARGBShuffleRow_RVV in row_rvv.cc.\n20. Fix NEON mask (15 -\u003e 7) in ScaleUVRowUp2_Linear_Any_NEON /\n _16_Any_NEON, use SIMD InterpolateRow + SplitUVRow in NV16ToI420,\n wire SSSE3/SSE2 in ARGBToI400Matrix / ARGBToYUY2Matrix /\n ARGBToUYVYMatrix and RGB24Mirror, and split HalfFloatRow multiply\n into (src * scale) * 2^-112 to avoid 50x Intel denormal stalls.\n\nBug: b/574714081\nTest: libyuv_unittest\nChange-Id: Iec3ae5c58d52bee3ef13cf9b765ac84b733aa576\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8601931\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "378bc91324587eedaadde88c81a5d05fada8a581", "tree": "6cb3cd6f4a3fd8baae4804d3705c7f0a30824654", "parents": [ "700f153cb8dd3719e9bc1eca61a2fcb20f5075e3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 16 16:51:17 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 19 15:56:38 2026 -0700" }, "message": "[libyuv] Multi-platform ScaleUVAddCols3 for ScaleUVBox at 3x\n\nBased on Philipp Hancke\u0027s AVX2 column kernel for ScaleUVBox at 3x\n(https://crrev.com/c/8427347).\n\nAdd ScaleUVAddCols3 for exact 3x horizontal downscaling (dx \u003d\u003d 0x30000\nand boxheight \u003c\u003d 85) in ScaleUVBox, plus ScaleAddRow_AVX512BW and\nScaleAddRow_WASMSIMD dispatch, and port 3x/box scaling kernels in\nscale_win.cc to 32/64-bit C++ intrinsics matching scale_gcc.cc:\n- ScaleUVAddCols3_C (portable C)\n- ScaleUVAddCols3_AVX2 and ScaleUVAddCols3_Any_AVX2 (scale_gcc.cc and\n scale_win.cc)\n- ScaleUVAddCols3_AVX512VBMI (scale_gcc.cc and scale_win.cc)\n- ScaleAddRow_SSE2, ScaleAddRow_AVX2, ScaleAddRow_AVX512BW,\n ScaleAddCols1_AVX512BW, ScaleAddCols2_AVX512BW, ScaleRowDown38_SSSE3,\n ScaleRowDown38_2_Box_SSSE3, and ScaleRowDown38_3_Box_SSSE3 in\n scale_win.cc for 32/64-bit Visual C and LIBYUV_ENABLE_ROWWIN\n- ScaleUVAddCols3_NEON (32-bit ARM and 64-bit AArch64) and\n ScaleUVAddCols3_Any_NEON\n- ScaleUVAddCols3_SME (ARMv9 Streaming SVE with whilelt predicate tail)\n- ScaleUVAddCols3_RVV (RISC-V Vector vlseg3e32.v inline asm)\n- ScaleUVAddCols3_LSX and ScaleUVAddCols3_Any_LSX (LoongArch LSX)\n- ScaleAddRow_WASMSIMD, ScaleAddRow_Any_WASMSIMD,\n ScaleUVAddCols3_WASMSIMD, and ScaleUVAddCols3_Any_WASMSIMD\n- ScaleUVAddCols3_HVX (Hexagon HVX vrdelta + vmpy_VuhRuh)\n\nCo-authored-by: Philipp Hancke \u003cphilipp.hancke@googlemail.com\u003e\nBug: libyuv:564129034\nR\u003drrwinterton@gmail.com\nChange-Id: Ib9e14f3efcb097842c3d0e9fc9b473b6e2f81871\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8596436\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "700f153cb8dd3719e9bc1eca61a2fcb20f5075e3", "tree": "4235926ddac459b7c5819325aee016b60707525f", "parents": [ "2404f9730e2e48946d29c6d28e3b630302a8d842" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Sat Oct 17 03:04:32 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 19 14:16:18 2026 -0700" }, "message": "[libyuv] Add Qualcomm Hexagon HVX SIMD support\n\nImplement Qualcomm Hexagon Vector Extensions (HVX) 128-byte SIMD\noptimizations and runtime CPU detection for Hexagon DSP targets:\n- CPU detection: Add kCpuHasHexagon and kCpuHasHVX flags,\n LIBYUV_DISABLE_HVX environment variable support, and Hexagon\n unit_test mmap/munmap shims.\n- Rotate/Transpose (rotate_hvx.cc): Implement TransposeWxH_HVX,\n TransposeUVWxH_HVX, TransposeWxH_16_HVX, and TransposeWxH_32_HVX\n using power-of-2 vdeal/vshuff butterfly networks.\n- Compare (compare_hvx.cc): Implement HammingDistance_HVX,\n SumSquareError_HVX, HashDjb2_HVX, and Ssim4x4Row_HVX.\n- Scale (scale_hvx.cc): Implement 16 scale row kernels including\n ScaleAddRow_HVX, ScaleRowDown2*_HVX (8-bit and 16-bit),\n ScaleRowDown4*_HVX, ScaleARGBRowDown2*_HVX, and\n ScaleUVRowDown2*_HVX.\n- Row functions (row_hvx.cc): Implement 58 row kernels covering\n copy/set/mirror, split/merge, 8/16-bit conversions, YUV-to-ARGB,\n ARGB-to-YUV, ARGB channel swizzles, blend, attenuate, and\n interpolate using hardware-predicated partial loads/stores.\n\nR\u003drrwinterton@gmail.com\n\nBug: None\nTest: libyuv_unittest on Hexagon v81 simulator and Snapdragon 8 Elite\nChange-Id: Ib6713de51f6246d95e58c95e629ff03f18e3b91e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8604586\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "2404f9730e2e48946d29c6d28e3b630302a8d842", "tree": "8f6241547b915fa1d5b909efe944971321d028c7", "parents": [ "ec29aca502fa3611fd4691ebd25130846f3cee2a" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 18:39:22 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 16 17:25:23 2026 -0700" }, "message": "[libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm\n\nReduce loop unrolling across LoongArch LSX (128-bit) and LASX (256-bit)\ncompare, row, rotate, and scale kernels to match SSE2/SSSE3 and AVX2\n(1-2 vectors per iteration), rewrite intrinsics/macro implementations\ninto GCC/Clang inline assembly, update all _Any wrapper masks and\nIS_ALIGNED dispatch checks, and port all remaining LSX Convert (+19) and\nRotate (+2) kernels to LASX for full parity:\n\nISA | Compare | Convert | Rotate | Scale\n-----------------|---------|---------|---------|--------\nMIPS/Loong (Any) | 1 | 68 | 4 | 20\n LSX | 1 | 68 | 4 | 20\n LASX | 1 | 68 | 4 | 0\n\nRemoves 1,935 macro/helper lines from loongson_intrinsics.h (-99.3%) and\nreduces total LoongArch compiled .text size by 9,799 bytes (-25.1%\noverall, -37.4% row_lsx.cc, -52.3% scale_lsx.cc, -31.2% rotate_lsx.cc,\n-4.9% row_lasx.cc while adding +25 LASX functions):\n\nFile | Before | After | Change\n-------------------|----------|----------|--------\nscale_lsx.cc.o | 6,055 B | 2,888 B | -52.3%\nrow_lsx.cc.o | 17,252 B | 10,792 B | -37.4%\nrotate_lsx.cc.o | 1,488 B | 1,024 B | -31.2%\nrow_lasx.cc.o | 13,740 B | 13,072 B | -4.9%\nrotate_lasx.cc.o | 544 B | 1,504 B | +176.5%\nTOTAL .text | 39,079 B | 29,280 B | -25.1%\n\nR\u003dwtc@google.com, yuanhecai@loongson.cn\n\nTest: qemu-loongarch64 -cpu la464 libyuv_unittest (LASX and LIBYUV_DISABLE_LASX\u003d1)\nChange-Id: I11c1143ad2aad0399f10b2c3fc9bc4c02c740c59\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8564659\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "ec29aca502fa3611fd4691ebd25130846f3cee2a", "tree": "e36bcd6fe281e55f33ec103f95ed62f59da21913", "parents": [ "0b9e5c922deec7c9921ae385f6242a9a27754d6e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 15 15:33:21 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Oct 15 23:22:58 2026 -0700" }, "message": "[libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD\n\nRefactor CalcFrameSsim to decompose overlapping 8x8 SSIM windows\n(stepped by 4 pixels horizontally and vertically) into non-overlapping\n4x4 pixel tiles across a 2-row rotating buffer (row0, row1), reducing\nmemory reads and pixel accumulation work by 4x:\n- Ssim4x4Row_* computes 4 uint32_t stats {sum_a, sum_b, sum_sq_ab,\n sum_axb} per 4x4 pixel tile across a 4-row strip (also sized to fit\n future 10-bit/12-bit formats like I010 without uint32_t overflow).\n- SsimWindowRow_C combines top and bottom 4x4 tile strips across\n adjacent horizontal pairs and returns the exact double SSIM sum,\n producing bit-identical results to Ssim8x8_C.\n- CalcFrameSsim rotates row0 and row1 (with thread-local buffers and\n continuity tracking under _OPENMP) and falls back to Ssim8x8_C only\n if buffer allocation fails.\n- Implement Ssim4x4Row across all SIMD architectures:\n - x86/x64: Ssim4x4Row_SSE2, Ssim4x4Row_AVX2, and Ssim4x4Row_AVX512BW\n (with k-masked tail handling for 4..60 pixels) in both\n compare_gcc.cc and compare_win.cc.\n - ARM: Ssim4x4Row_NEON (compare_neon.cc, compare_neon64.cc),\n Ssim4x4Row_NEON_DotProd (compare_neon64.cc), Ssim4x4Row_SVE2\n (row_sve.h, row_sve.cc), and Ssim4x4Row_SME (row_sme.cc).\n - RISC-V: Ssim4x4Row_RVV (row_rvv.cc).\n - LoongArch: Ssim4x4Row_LSX (row_lsx.cc) and Ssim4x4Row_LASX\n (row_lasx.cc).\n - WebAssembly: Ssim4x4Row_WASMSIMD (compare_wasm.cc).\n- Enable BenchmarkSsim_Opt and add BenchmarkSsim_Unaligned and\n TestSsimAnyWidth in unit_test/compare_test.cc.\n\nBenchmarkSsim_Opt (1280x720, single core, us/frame):\nuArch Before (C) After (us) Improvement\n-------------------------------- ---------- ----------- -----------\nIntel Lion Cove (AVX2) 356.33 119.09 2.99x\nAMD Zen 6 (AVX512BW) 455.86 124.67 3.66x\nAMD Zen 5 (AVX512BW) 518.91 128.29 4.04x\nIntel Emerald Rapids (AVX512BW) 601.58 180.41 3.33x\nIntel Cougar Cove (AVX2) 608.11 183.34 3.32x\nIntel Granite Rapids (AVX512BW) 596.57 187.04 3.19x\nIntel Golden Cove (AVX2) 534.58 187.93 2.84x\nIntel Sapphire Rapids (AVX512BW) 634.36 189.92 3.34x\nAMD Zen 4 (AVX512BW) 713.06 223.65 3.19x\nIntel Skymont (SSE2) 445.99 250.52 1.78x\nIntel Ice Lake (AVX512BW) 845.16 267.23 3.16x\nAMD Zen 3 (AVX2) 741.02 267.38 2.77x\nAMD Zen 2 (AVX2) 907.04 301.02 3.01x\nIntel Skylake-X (AVX512BW) 1097.86 301.63 3.64x\nIntel Darkmont (SSE2) 772.18 383.39 2.01x\nIntel Gracemont (SSE2) 961.80 421.83 2.28x\nIntel Haswell (AVX2) 1159.74 479.14 2.42x\nIntel Ivy Bridge (SSE2) 1296.99 597.32 2.17x\nApple M6 Super (SME) 404.66 90.09 4.49x\nApple M6 Perf (DotProd) 444.72 104.59 4.25x\nQualcomm Oryon-L (DotProd) 490.76 108.79 4.51x\nQualcomm Oryon V3-L (SVE2) 663.13 150.75 4.40x\nARM Cortex-X4 (DotProd) 620.21 177.29 3.50x\nARM Neoverse-V2 (SVE2) 682.93 205.18 3.33x\nARM Cortex-X3 (DotProd) 737.38 226.24 3.26x\nARM C1-Ultra (DotProd) 596.71 229.10 2.60x\nARM Cortex-X2 (DotProd) 820.94 247.94 3.31x\nQualcomm Oryon-M (DotProd) 1146.09 257.89 4.44x\nQualcomm Oryon V3-M (SME) 1068.78 276.23 3.87x\nARM Cortex-A720 (DotProd) 993.59 292.62 3.40x\nARM Cortex-X1 (DotProd) 912.19 326.44 2.79x\nARM Cortex-A715 (DotProd) 1135.67 340.12 3.34x\nARM Cortex-A710 (DotProd) 1222.04 342.51 3.57x\nARM Neoverse-N1 (DotProd) 1406.72 376.46 3.74x\nARM Cortex-A725 (SVE2) 1104.13 376.86 2.93x\nARM C1-Pro (SVE2) 1073.69 413.97 2.59x\nARM Cortex-A76 (DotProd) 1491.02 423.58 3.52x\nARM Cortex-A78 (DotProd) 1503.73 485.00 3.10x\nAmpereOne (DotProd) 1518.61 518.40 2.93x\nApple M6 Eff (DotProd) 4051.10 572.93 7.07x\nARM Cortex-A75 (NEON) 2055.04 812.09 2.53x\nARM Cortex-A520 (DotProd) 3307.98 963.86 3.43x\nARM Cortex-A73 (NEON) 3120.09 1180.17 2.64x\nQualcomm Kryo Perf (NEON) 4921.16 1459.77 3.37x\nARM Cortex-A510 (DotProd) 4645.10 1641.06 2.83x\nARM Cortex-A55 (DotProd) 4571.02 1672.09 2.73x\nQualcomm Kryo Eff (NEON) 6000.96 1796.17 3.34x\nARM Cortex-A55r0 (NEON) 10486.61 4358.61 2.41x\nARM Cortex-A53 (NEON) 10121.34 5700.99 1.78x\n\nR\u003drrwinterton@gmail.com\n\nBug: None\nTest: out/Release/libyuv_unittest --gtest_filter\u003d*Ssim*\nChange-Id: Ibb95ae74424ecdda073ab7ab10ab1cf610b121b6\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8593040\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "0b9e5c922deec7c9921ae385f6242a9a27754d6e", "tree": "32f2a9014ceb73c4878e691fbfea79c2b8971a2a", "parents": [ "58d817ed81e8fe8b06a58576d639cd56b19526d3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Oct 14 23:01:28 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Oct 14 23:16:54 2026 -0700" }, "message": "Avoid signed int overflow in scale functions using uint32_t\n\nUse uint32_t for the 16.16 fixed-point row coordinate (uy) and max_y\nin the vertical loops of ScalePlane*, ScaleUV*, and the Up2 linear\nhelpers. With src_height up to 32768, (src_height \u003c\u003c 16) and y +\u003d dy\noverflow signed int (e.g. for dst_height \u003d\u003d 2 the post-read step\nreaches 5/4 * (src_height \u003c\u003c 16), which exceeds INT_MAX for any\nsrc_height \u003e\u003d 26215, and for kFilterNone the final increment after\nthe last row reaches (src_height \u003c\u003c 16) + dy / 2). uint32_t cannot\noverflow for these ranges (uy \u003c\u003d 0xFFFF0000) and stays in a single\n32-bit register on 32-bit targets (x86, Arm, WASM), unlike int64_t.\n\nUndo the interim +/-32767 height cap from https://crrev.com/c/8524280\nso ScalePlane, ScalePlane_16, UVScale, and UVScale_16 accept\n|src_height| \u003c\u003d 32768 again.\n\nScaleUVBilinearUp2 and ScaleUVBilinearUp2_16 take ptrdiff_t strides\nso 2 * dst_stride does not overflow int for images over 2 GB.\n\nARGBScale, ARGBScaleClip, and UVScale_16 reject |src_width| \u003e 32768\nand |src_height| \u003e 32768, and ScalePlane, ScalePlane_16, and\nScaleSlope avoid FixedDiv(32768, 1) overflow when dst_width \u003d\u003d 1 or\ndst_height \u003d\u003d 1.\n\nBug: chromium:531172025, chromium:546841026, libyuv:573815252\n\nTest: libyuv_unittest --gtest_filter\u003d*ScalePlaneOversizeHeight*:*ScalePlaneBoxMaxSrcHeight*:*ScaleLargeImageOver2GB*:*ARGBScale*\nChange-Id: Ica2e05d7dfe94f81c6631c587f1ff46c2ad44735\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8528398\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "58d817ed81e8fe8b06a58576d639cd56b19526d3", "tree": "a23bc7c4aa5eb051cef6ecd2e48e5ca37611d88d", "parents": [ "b9d572cc63f26641422c061364e86c5050fcac78" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 19:27:07 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Oct 13 11:20:48 2026 -0700" }, "message": "Fix remaining inline asm input/output constraints and clobbers\n\nMark modified inline asm operands as read-write (+r / +c) and add missing\nvolatile/memory clobbers so compilers and LTO do not assume modified\nregisters remain unchanged across asm blocks:\n- HashDjb2_NEON (compare_neon64.cc): [src] \"+r\"(src) for post-increment ldr\n- FixedDiv1_X86 (scale_gcc.cc): \"+c\"(div) for sub $0x1, %1\n- P410ToARGBRow_SVE_SC \u0026 P410ToAR30Row_SVE_SC (row_sve.h): [vl] \"+r\"(vl)\n for tail cntw %x[vl]\n- SwapUVRow_RVV \u0026 ARGBMultiplyRow_RVV (row_rvv.cc): use asm volatile and\n \"memory\" clobber instead of VLA memory operands on mutated pointers\n\nR\u003drrwinterton@gmail.com\n\nBug: b/571179207\nTest: libyuv_unittest\nChange-Id: I3c2475d1e5bdab13e74643a028eebc350edcc1bb\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8565646\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "b9d572cc63f26641422c061364e86c5050fcac78", "tree": "6dd2abafd0052b02eab689c97a9f690bb94135a6", "parents": [ "63b56324de0d3afbd26653025bf4367b68137245" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 17:12:52 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Oct 12 18:14:41 2026 -0700" }, "message": "Add 25 native k-masked AVX-512 row kernels\n\nR\u003drrwinterton@gmail.com\n\nBug: None\nChange-Id: I2ee9b2c2d939f63f49d2f951f2d552ca6863d78b\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8564927\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "63b56324de0d3afbd26653025bf4367b68137245", "tree": "4c269f4c3cf7533fd0bd91e7b892e28bcfaf700d", "parents": [ "1e2e3a35993609da1d89ac170b907719d555f4b3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 13:37:50 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 15:33:19 2026 -0700" }, "message": "[libyuv] Replace AVX-512 _Any wrappers with k-mask tail handling\n\nReplace stack-buffer memcpy _Any wrappers with native AVX-512 k-mask\ntail handling across 8 AVX-512 row kernels (unlocking composite\nRGBToUVMatrixRow_AVX512BW as well) and remove IS_ALIGNED dispatch\nconstraints:\n- MirrorSplitUVRow_AVX512BW: Masked 16-bit load (vmovdqu16 %{k1%}%{z%}),\n dynamic reverse index (vpsubw + vpermw via kMirrorUVPermute_AVX512),\n and vpmovwb %{k1%} U/V stores; unlocks unaligned SplitRotateUV180.\n- ARGBToUVMatrixRow_AVX512BW: Fix MASK\u003d63 vs 32-pixel loop bug;\n zero-load tail dwords per row, duplicate odd final pixel via knotw +\n vpshufd, and store masked U/V bytes.\n- I422ToARGBRow_AVX512BW \u0026 I422ToAR30Row_AVX512BW: Add masked Y/U/V\n loads (READYUV422_MASK_AVX512BW) and masked ARGB/AR30 stores.\n- CopyRow_AVX512BW: Add 64-byte full vector step + bzhi masked tail.\n- BlendPlaneRow_AVX512BW, ARGBShuffleRow_AVX512BW, RGBToARGBRow_AVX512BW\n (RAWToARGBRow_AVX512BW / RGB24ToARGBRow_AVX512BW): Masked loads and\n stores in both row_gcc.cc inline assembly and row_win.cc intrinsics.\n\nReduces x86-64 binary .text size by 2,592 bytes with 0 bytes added to\n.rodata.\n\nPerformance on Intel Sapphire Rapids (1275x1650, 1000 iterations):\nFunction (Test) | Before | After | Speedup\n-------------------------|---------|---------|--------\nNV12Rotate180_Opt | 429 ms | 260 ms | 1.65x\nRGB24ToI420_Opt | 615 ms | 531 ms | 1.16x\nI420ToAR30_Opt | 425 ms | 383 ms | 1.11x\nARGBToI420_Opt | 427 ms | 411 ms | 1.04x\nI420ToARGB_Opt | 423 ms | 411 ms | 1.03x\nRGB24ToARGB_Opt | 493 ms | 490 ms | 1.01x\nARGBToBGRA_Opt | 544 ms | 542 ms | 1.00x\nCopyPlane_Opt | 246 ms | 245 ms | 1.00x\nBlendPlane_Opt | 259 ms | 258 ms | 1.00x\nRAWToARGB_Opt | 486 ms | 486 ms | 1.00x\n\nR\u003drrwinterton@gmail.com\n\nTest: LIBYUV_WIDTH\u003d1275 LIBYUV_HEIGHT\u003d1650 LIBYUV_REPEAT\u003d1000 out/Release/libyuv_unittest\nChange-Id: Ib5e5ae52076352649108b20f8df2b12d81860fb1\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8563977\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "1e2e3a35993609da1d89ac170b907719d555f4b3", "tree": "313229116ae21b74e71e2440d3e42b047de62a39", "parents": [ "16af162cf9ed6cb8263327c07df0b769e3a9fc17" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Oct 07 15:02:36 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Oct 12 11:23:37 2026 -0700" }, "message": "Avoid integer overflow if src_height \u003d\u003d +/-32768\n\nThe ScalePlaneBox(), ScalePlaneBox_16(), and ScaleUVBox() functions all\ncontain the following expression:\n\n const int max_y \u003d (src_height \u003c\u003c 16);\n\nwhere src_height is a positive int. This expression overflows if\nsrc_height \u003e\u003d 32768.\n\nTracing the callers, we make sure ScalePlane(), ScalePlane_16(), and\nUVScale() reject src_height \u003c -32767 || src_height \u003e 32767 as invalid\ninput. (These functions negate a negative src_height before calling a\nfunction that executes expression src_height \u003c\u003c 16.)\n\nAlthough UVScale_16() do not execute the expression src_height \u003c\u003c 16,\nmake the same change to UVScale_16() for consistency with UVScale().\n\nBug: chromium:531172025\nChange-Id: Id5b10f11f46f593945cf6bf1435b6027a6629815\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8524280\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "16af162cf9ed6cb8263327c07df0b769e3a9fc17", "tree": "c2420bdd6ce12d68c362f4e2165331691e6c2448", "parents": [ "eeb06a6451ba2e21f8ff272c7b42fc62b9faecc5" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 12 04:12:23 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Oct 12 10:57:34 2026 -0700" }, "message": "[libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes\n\nImplement SIMD 16-bit plane rotation (TransposePlane_16,\nRotatePlane90_16, RotatePlane180_16, RotatePlane270_16) used by\nI010Rotate, I210Rotate, and I410Rotate, keeping tile sizes compact\nwith full-register writes and zero cross-lane shuffles:\n- AVX2: 8x16 tile in ymm0..ymm15 with _Any tail (low-end x86 SIMD)\n- AVX-512BW: 8x32 tile in zmm0..zmm15 with k1/k2 right/bottom masks\n- NEON (ARM64/ARM32): 8x16 tile in v0..v23 / q0..q11 with _Any tail\n- SME: 8xVL tile using ZA16 horizontal/vertical array slices\n- RVV: 8xVL tile using widening unpacks with hardware vl tail\n- WASM SIMD: 8x8 tile in v128 with _Any tail\n\nAlso update 32-bit ARGBRotate x86 transposes to compact vertical\nin-lane tiles with full-register writes and zero cross-lane shuffles:\n- TransposeWxH_32_AVX2: 4x8 tile in ymm0..ymm7 with vpmaskmovd tails\n- TransposeWxH_32_AVX512BW: 4x16 tile in zmm0..zmm7 with k1/k2 tails\n\nAdd RotatePlane16_SplitMergeUV_Opt and RotatePlane16_SplitMergeUV_Odd\nunit tests comparing 16-bit rotation against SplitUVPlane +\nRotatePlane + MergeUVPlane across 0/90/180/270 degrees.\n\nPerformance on 1275x1650 (1000 iterations, before -\u003e after):\nCPU 90 degree 180 degree\nCoral RVV (Verilator) 7306 -\u003e 1415c (5.16x) 2274 -\u003e 719c (3.16x)\nAMD Rome (Zen 2) 821 -\u003e 215ms (3.82x) 259 -\u003e 181ms (1.44x)\nAMD Genoa (Zen 4) 483 -\u003e 129ms (3.73x) 149 -\u003e 111ms (1.34x)\nAMD Turin (Zen 5) 321 -\u003e 101ms (3.18x) 109 -\u003e 78ms (1.40x)\nAMD Milan (Zen 3) 505 -\u003e 189ms (2.67x) 199 -\u003e 118ms (1.69x)\nIntel Skylake-X 1076 -\u003e 447ms (2.41x) 353 -\u003e 317ms (1.11x)\nWASM SIMD (d8) 415 -\u003e 203ms (2.04x) 370 -\u003e 106ms (3.49x)\nIntel Emerald Rapids 735 -\u003e 422ms (1.74x) 238 -\u003e 233ms (1.02x)\nIntel Haswell 1120 -\u003e 648ms (1.73x) 438 -\u003e 393ms (1.11x)\nIntel Ice Lake 774 -\u003e 474ms (1.63x) 279 -\u003e 290ms (0.96x)\nARM Neoverse-N1 864 -\u003e 544ms (1.59x) 404 -\u003e 266ms (1.52x)\nAmpere Siryn 862 -\u003e 576ms (1.50x) 568 -\u003e 329ms (1.72x)\nGoogle Axion (Maple) 554 -\u003e 379ms (1.46x) 199 -\u003e 142ms (1.41x)\nIntel Sapphire Rapids 1126 -\u003e 772ms (1.46x) 301 -\u003e 288ms (1.04x)\nIntel Granite Rapids 730 -\u003e 565ms (1.29x) 280 -\u003e 280ms (1.00x)\nNVIDIA Grace 462 -\u003e 365ms (1.26x) 192 -\u003e 126ms (1.52x)\nARM Cortex-A53 28290 -\u003e 24386ms (1.16x) 7178 -\u003e 5075ms (1.41x)\nGoogle Axion 2 (Tamar) 523 -\u003e 453ms (1.15x) 217 -\u003e 112ms (1.93x)\n\nTest: libyuv_unittest --gtest_filter\u003d*Rotate*\nBug: b/42280942\nChange-Id: I91ba6cac22185b5d294fcb98344fdb8a23cc94ff\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8545294\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "eeb06a6451ba2e21f8ff272c7b42fc62b9faecc5", "tree": "393763a9850c64ad7cbe70dc3a286db73d3a0c9e", "parents": [ "4ce4edd50e5dc146c66648628848a9e08968a277" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 08 03:05:41 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 08 16:20:46 2026 -0700" }, "message": "[libyuv] Optimize ARGBRotate for Intel SSE2, AVX2, and AVX-512\n\nOptimize 32-bit ARGBRotate (0, 90, 180, 270) across Intel x86/x64\narchitectures (SSE2, AVX2, AVX512BW), with matching kernels for ARM\n(NEON, SVE2, SME), WASM, LoongArch (LSX, LASX), and RISC-V (RVV):\n\n- Replace column-by-column ScaleARGBRowDownEven gather loops in\n ARGBTranspose (90/270) with full-plane horizontal tile transposes:\n - AVX512BW (TransposeWxH_32_AVX512BW / TransposeNx4_32_AVX512BW):\n Transpose 16x16 blocks across zmm0..zmm31 using 4-stage\n vpunpckldq/hdq, vpunpcklqdq/hqdq, and vshufi32x4 butterflies with\n k-masked right and bottom tails, eliminating Any wrappers and scalar\n C edge fallbacks.\n - AVX2 (TransposeWxH_32_AVX2 / TransposeNx4_32_AVX2):\n Transpose 8x8 blocks across ymm0..ymm15 using vpunpck* and\n vperm2i128 with vpmaskmovd masked tails.\n - SSE2 (Transpose4x4_32_SSE2 / Transpose4x4_32_Any_SSE2):\n Transpose 4x4 blocks in xmm registers.\n- Implement ARGBRotate180 directly via ARGBMirror with negative height,\n avoiding intermediate row buffer allocations and extra copies.\n- Implement ARGBRotate0 via ARGBCopy.\n\nSpeedup vs Before (1275x1650, US Letter 150 DPI, 1000 iterations):\nCPU | 0 deg | 90 deg | 180 deg | 270 deg\n---------------------|---------|---------|---------|--------\nIntel Ice Lake | 1.02x | 1.34x | 1.18x | 1.33x\nIntel Skylake-X | 1.02x | 1.20x | 1.07x | 1.13x\nIntel Emerald Rapids | 1.01x | 1.07x | 1.00x | 1.07x\nIntel AVX-512 vs C | 1.00x | 2.67x | 2.41x | 2.63x\n\nR\u003drrwinterton@gmail.com\n\nBug: b/42280915\nTest: LIBYUV_WIDTH\u003d1275 LIBYUV_HEIGHT\u003d1650 LIBYUV_REPEAT\u003d1000 ./out/Release/libyuv_unittest --gtest_filter\u003d*ARGBRotate*\nChange-Id: Ib308a225c17e46eab083a9da4033598fcf0c303c\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8538986\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "4ce4edd50e5dc146c66648628848a9e08968a277", "tree": "e85154f2c37a95e917ec99d4cbdc53bca73dfeb7", "parents": [ "9456b062277d2809c97f4633c116ffa8d485afdd" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 08 13:25:43 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Oct 08 14:44:23 2026 -0700" }, "message": "Fix missing inline asm register clobbers\n\nChange-Id: Ic573c8d7d8921a1dd00e4481b854a8168d0c94f7\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8543110\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "9456b062277d2809c97f4633c116ffa8d485afdd", "tree": "2fb8b5456084a47090835ef427814192bcaee634", "parents": [ "1ddb18fb6b6cc91f852648a6e64d2dee31b11a80" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Oct 07 15:21:20 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Oct 07 16:10:15 2026 -0700" }, "message": "Remove the Abs() function in source/scale_uv.cc\n\nThe Abs() function is used at two places in source/scale_uv.cc as\nfollows:\n src_width \u003d Abs(src_width);\n\nHowever, before we reach those two places, we have rejected\nsrc_width \u003c\u003d 0 as invalid input. Therefore the two Abs(src_width) calls\nhave no effects.\n\nBug: None\nChange-Id: I04c48ad5d1270b9b93abb18f2b41b90ec818d5ea\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8531148\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "1ddb18fb6b6cc91f852648a6e64d2dee31b11a80", "tree": "a04a04489b54331343a9f24bdb783b84a7e38a3a", "parents": [ "98697ab033ff9fb56dbe42c6bb214e1d285640c4" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Oct 07 12:23:52 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Oct 07 12:44:53 2026 -0700" }, "message": "[libyuv] AVX512, NEON, WASM and RVV alpha copy and mirror rows\n\n1275x1650 (US Letter 150 DPI, 1000 iterations) speedup:\n\nCPU ARGBExtractAlpha ARGBCopyYToAlpha ARGBMirror RGB24Mirror\n-----------------------------------------------------------------------\nIntel Granite Rapids 1.00x 1.00x 1.00x 1.04x\nIntel Emerald Rapids 1.01x 0.97x 1.03x 1.07x\nIntel Sapphire Rapids 0.97x 1.01x 1.08x 1.26x\nIntel Ice Lake 0.99x 1.02x 0.97x 1.08x\nIntel Skylake-X 1.04x 1.03x 1.01x NA\nIntel Haswell NA NA NA NA\nAMD Turin (Zen 5) 1.01x 1.10x 1.25x 1.31x\nAMD Genoa (Zen 4) 0.97x 1.04x 1.09x 1.42x\nAMD Milan (Zen 3) NA NA NA NA\nAMD Rome (Zen 2) NA NA NA NA\nNVIDIA Grace (V2) 1.57x 2.51x NA NA\nGoogle Axion 2 1.12x 3.17x NA NA\nAmpere Siryn 1.06x 1.70x NA NA\nARM Neoverse-N1 1.49x 2.01x NA NA\nGoogle Axion (Maple) 1.47x 2.03x NA NA\nARM Cortex-A53 1.06x 1.69x NA NA\n\nAdd AVX512BW ARGBExtractAlphaRow, ARGBCopyYToAlphaRow and\nARGBMirrorRow, and AVX512VBMI RGB24MirrorRow, in row_gcc.cc and as\nintrinsics in row_win.cc. They are x64 only. The remainder is done\nwith a k-mask (bzhi) zero-masked load and a masked store, so they\nhandle any width without an Any wrapper and never access memory\noutside the row.\n\nRGB24MirrorRow_AVX512VBMI loads and stores 3 full zmm vectors per\n64 pixels using 3 vpermi2b. The one output byte that comes from the\nthird input vector is merged with a masked vpbroadcastb. The 1 to 63\npixel tail rebases the same tables by 192 - 3 * r; indices \u003e\u003d 128 are\ntaken from the third vector with vpmovb2m and a masked vpermb.\n\nAdd ARGBCopyYToAlphaRow_NEON for Arm 32 bit (vld4 + vst4) and\nAArch64 (zip + sli), and rewrite AArch64 ARGBExtractAlphaRow_NEON\nwith ldp + uzp2. Both prefetch source and destination, which is\n2.5x faster on Neoverse-N1 and 1.2x to 1.5x faster on Cortex-A53\nfor 1280x720. Add WASM SIMD ARGBExtractAlphaRow and\nARGBCopyYToAlphaRow, using a swizzle table for CopyYToAlpha. Rework\nthe RVV versions to use unit stride loads with vnsrl and vzext.vf4.\n\n\nR\u003drrwinterton@gmail.com\n\nBug: None\nChange-Id: I436f27d70a3db0a2b176c91eb789a9491133cfcb\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8523531\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "98697ab033ff9fb56dbe42c6bb214e1d285640c4", "tree": "1ba317ed847a44164868b5d4fa64e395ce6c8bf0", "parents": [ "5323bab29e8d2623e77be549450a4f852c95a18f" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 23:37:52 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 06 19:05:05 2026 -0700" }, "message": "[libyuv] Add WASM SIMD128 compare, rotate, scale and row functions\n\nd8 geomean speedup vs C compiled with -O2 -msimd128:\nFile AMD Zen 3 ARM Neoverse-V2\nrow_wasm.cc 5.67x 3.24x\nscale_wasm.cc 5.47x 3.17x\ncompare_wasm.cc 4.58x 5.77x\nrotate_wasm.cc 6.83x 6.03x\n\nBug: None\nChange-Id: Ia06c805dc4029f94842c40e7301b2933beb8c1e5\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8524106\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "5323bab29e8d2623e77be549450a4f852c95a18f", "tree": "6369ba2c8b33bac7e013dd1b628aaad240f62f84", "parents": [ "eb8eda9c7973704d1103a535059224df7a6063b5" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 18:10:39 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 06 12:19:58 2026 -0700" }, "message": "[libyuv] Clobber \"vl\" in RVV inline assembly only for GCC\n\nDefine RVV_VL_CLOBBER to expand to \"vl\", on GCC and empty on Clang in\nsource/row_rvv.cc and source/scale_rvv.cc, and replace \"vl\", \"vtype\",\nin the RVV inline assembly clobber lists with RVV_VL_CLOBBER.\n\nR\u003dmasterwilliams@google.com, rrwinterton@gmail.com\n\nTest: ninja -C out/riscv64 libyuv_unittest\nBug: b/443984359\nChange-Id: Ie65bde737bd0714c3e409a2b8ab5fcd98b6a7a32\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8516707\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "eb8eda9c7973704d1103a535059224df7a6063b5", "tree": "7508f9a7d5fd7f888bef803a9221c8edd5082b49", "parents": [ "2b7ecc0aad70fe1db1456b0d851525a500f91617" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 12:54:31 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Oct 05 17:45:41 2026 -0700" }, "message": "[libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row\n\nImplement RAWToRGB24Row_WASMSIMD and RAWToRGB24Row_Any_WASMSIMD in\nsource/row_wasm.cc for RGB24ToRAW and RAWToRGB24 conversions:\n- Process 16 pixels (48 bytes) per loop iteration using three 128-bit\n loads, three byte-wise shuffles, and four 2-way blends.\n- Use wasm_i8x16_relaxed_swizzle when __wasm_relaxed_simd__ is enabled\n (compiling to a single vpshufb on x86 without bounds-checking\n overhead) and fall back to wasm_i8x16_swizzle for baseline SIMD128.\n- Add kCpuHasWASM (0x100) and kCpuHasWASMSIMD (0x101) CPU feature\n flags and enable -msimd128 in BUILD.bazel, BUILD.gn, and\n CMakeLists.txt for WebAssembly targets.\n\nPerformance (RAWToRGB24_Opt, 1280x720, V8 d8):\nCPU WASM C SIMD128 Relaxed SIMD Spd Rlx Spd\n-------------------------------------------------------------------\nAMD Zen 4 595.0 us 137.0 us 84.0 us 4.34x 7.08x\nAMD Zen 3 708.0 us 148.0 us 107.0 us 4.78x 6.62x\nAMD Zen 5 375.0 us 107.0 us 67.0 us 3.50x 5.60x\nARM Neoverse-V2 638.0 us 118.0 us 116.0 us 5.41x 5.50x\nARM Neoverse-N1 1046.0 us 294.0 us 294.0 us 3.56x 3.56x\nIntel Ice Lake 707.0 us 209.0 us 220.0 us 3.38x 3.21x\nIntel Haswell 1110.0 us 344.0 us 360.0 us 3.23x 3.08x\nIntel Emerald Rapids 519.0 us 207.0 us 208.0 us 2.51x 2.50x\nIntel Sapphire Rapids 551.0 us 220.0 us 255.0 us 2.50x 2.16x\nARM Cortex-A53 14440.0 us 8660.0us 6920.0us 1.67x 2.09x\nIntel Granite Rapids 453.0 us 225.0 us 221.0 us 2.01x 2.05x\n\nBug: 42271072\nTest: libyuv_test --gunit_filter\u003d*RAWToRGB24*:*RGB24ToRAW*:*Cpu*\nChange-Id: Id902668263a2ab70aa300eeeea18851490c917b5\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8515581\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "2b7ecc0aad70fe1db1456b0d851525a500f91617", "tree": "49a3b9617a05deab47ae47f9cdfb7e4495721707", "parents": [ "42eb3a552f7cf75f8b17a9d67a4070f063ac0070" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 11:04:32 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 12:09:40 2026 -0700" }, "message": "RAWToRGB24 for NEON, x86, and LoongArch\n\nR\u003drrwinterton@gmail.com\n\nTest: libyuv_unittest --gtest_filter\u003d*RAWToRGB24*:*RGB24ToRAW*\nBug: None\nChange-Id: I4454f3785ba5c39dc776ba1f5151cd9d3e68055b\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8509286\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "42eb3a552f7cf75f8b17a9d67a4070f063ac0070", "tree": "57a2c2c56b2c5edcf698e35aacc7441d7fe4fdc5", "parents": [ "aa6cedb39c87910b4c28e5c71c2121fc45fd234b" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 21:06:09 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 05 10:56:34 2026 -0700" }, "message": "[libyuv] Add ScaleRowDown2Box_AVX512BW with tail masking\n\nAdd AVX-512BW implementations of ScaleRowDown2_AVX512BW,\nScaleRowDown2Linear_AVX512BW, ScaleRowDown2Box_AVX512BW, and\nScaleRowDown2Box_Odd_AVX512BW in scale_gcc.cc.\n\nUse 512-bit zmm vectors (64 source bytes -\u003e 32 destination pixels per\niteration) with vpmovwb narrowing stores, and handle remaining 1..31\ndestination pixels in-place using hardware mask register k1 (vmovdqu16\nzero-masked loads for 2-byte source pixel pairs and vpmovwb masked\nnarrowing store), eliminating the ScaleRowDown2*_Any_AVX2 fallback on\nAVX-512BW CPUs.\n\nHook up the new row functions in ScalePlaneDown2 (source/scale.cc) and\nI420Blend (source/planar_functions.cc).\n\nI420ScaleDownBy2_Box\n(LIBYUV_WIDTH\u003d638 LIBYUV_HEIGHT\u003d360 LIBYUV_REPEAT\u003d2000):\nCPU SSSE3 AVX2 AVX512 512/AVX2\nAMD Turin (Zen 5) 57 62 36 1.72x\nIntel Granite Rapids 76 76 45 1.69x\nAMD Genoa (Zen 4) 85 84 50 1.68x\nIntel Sapphire Rapids 68 73 44 1.66x\nIntel Emerald Rapids 69 66 48 1.38x\nIntel Ice Lake 128 128 96 1.33x\nIntel Skylake-X 153 150 121 1.24x\nAMD Milan (Zen 3) 95 95 96 -\nIntel Haswell 193 172 162 -\n\nR\u003drrwinterton@gmail.com\n\nBug: libyuv:960\nTest: libyuv_unittest --gtest_filter\u003d*ScalePlaneDown2*:*I420Blend*\nChange-Id: Ifbfcc4042c50d28022b12cb807dad56e66e7f301\nTAG\u003dagy\nCONV\u003d5f01827f-2aa8-4718-b8c1-7f282730918e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8504320\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "aa6cedb39c87910b4c28e5c71c2121fc45fd234b", "tree": "e63b316aa8d7331d705e395907879d36f5e979f6", "parents": [ "67b3c0dad84b574cfaf8f26d0c5f6e17a93ed206" ], "author": { "name": "Philipp Hancke", "email": "philipp.hancke@googlemail.com", "time": "Thu Oct 01 12:33:38 2026 +0200" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 02 15:37:21 2026 -0700" }, "message": "Add a box filter to ScaleUV\n\nkFilterBox only had 1/2 and 1/4 fast paths. Everything else fell\nthrough to ScaleUVSimple and point sampled, so NV12 chroma was\nunfiltered where I420 was not. 13.6 dB against 50.2 dB at 3x.\n\nScaleUVBox mirrors ScalePlaneBox. Row accumulation reuses ScaleAddRow\nand its SIMD variants, since summing is position wise and an\ninterleaved row is just src_cols * 2 samples. Only the column pass,\nwhich sums U and V at a stride of 2, is new.\n\nOutput is now byte identical to the I420 path. Tests compare against\nScalePlane rather than C against SIMD, which is what missed this.\n\nBug: libyuv:564129034\nChange-Id: I26221f5435dbfc845ad2fc13aa347ef56ccf7bc6\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8426668\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "67b3c0dad84b574cfaf8f26d0c5f6e17a93ed206", "tree": "ea993bb93928101a1e467bd89d1a06a94cfc36f3", "parents": [ "bad060c3a57876fb1c78abaf334949fa98cca8e5" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 18:41:09 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Oct 02 15:30:05 2026 -0700" }, "message": "Compare AVX512BW and AVX2, intrinsics for Visual C and ROWWIN\n\n- Add HammingDistance_AVX512BW, SumSquareError_AVX512BW and\n HashDjb2_AVX512BW for 32 and 64 bit, as inline assembly in\n compare_gcc.cc and intrinsics in compare_win.cc.\n- AVX512BW processes 64 bytes per loop with full vectors, and the\n remainder of 1 to 63 bytes with one masked load, so compare.cc passes\n any count and does not use C for the remainder. HashDjb2 loads the\n remainder into the high bytes, ending at src + count, so the same\n 33 ^ (63 - i) multipliers apply, and multiplies the hash by 33 ^ n.\n- Add SumSquareError_AVX2 and HashDjb2_AVX2 to compare_gcc.cc and\n HammingDistance_AVX2 to compare_win.cc, so both files have the same\n functions. Enable AVX2 in compare_gcc.cc for gcc as well as clang.\n- HashDjb2 AVX2 and AVX512BW split the 32 bit multipliers 33 ^ i into\n 16 bit halves and use vpmaddwd, instead of vpmulld which is 2 uops\n with 10 cycle latency. Bytes are zero extended with vpmovzxbw from\n memory. The hash \u003d hash * 33 ^ 64 + sum dependency uses scalar imul\n instead of vpmulld. AVX2 does 64 bytes per horizontal add.\n- Port compare_win.cc from 32 bit Visual C inline assembly to\n intrinsics and enable it for Visual C 32/64 bit and\n LIBYUV_ENABLE_ROWWIN, which MemorySanitizer also enables. Visual C 64\n bit and MemorySanitizer previously used C.\n- Fix HammingDistance_SSSE3 and HammingDistance_AVX2 to allow unaligned\n pointers. They used movdqa and crashed on unaligned src_a.\n- Add TestCompareAnyCount to test every count from 0 to 321, aligned\n and unaligned, ending at the end of a page.\n\nFunctions available:\nFunction compare_gcc compare_win\n 32/64 bit 32/64 bit\nHammingDistance_SSE42 asm intrinsics\nHammingDistance_SSSE3 asm -\nHammingDistance_AVX2 asm intrinsics\nHammingDistance_AVX512BW asm intrinsics\nSumSquareError_SSE2 asm intrinsics\nSumSquareError_AVX2 asm intrinsics\nSumSquareError_AVX512BW asm intrinsics\nHashDjb2_SSE41 asm intrinsics\nHashDjb2_AVX2 asm intrinsics\nHashDjb2_AVX512BW asm intrinsics\n\nPerformance, 1280x720, LIBYUV_REPEAT\u003d1000, best of 3, ms.\nBefore is main (SSE, and AVX2 Hamming only, in compare_gcc).\n\nBenchmarkDjb2_Opt main gcc gcc win win\n AVX2 AVX512 AVX2 AVX512\nIntel Haswell 179 77 - 75 -\nAMD Milan (Zen 3) 101 35 - 35 -\nIntel Skylake-X 214 63 55 67 59\nIntel Ice Lake 191 51 47 52 49\nIntel Sapphire Rapids 175 39 39 38 39\nIntel Granite Rapids 170 40 38 40 38\nAMD Genoa (Zen 4) 91 34 37 34 38\nAMD Turin (Zen 5) 80 29 22 28 23\nC 502 to 669\n\nBenchmarkSumSquareError main gcc gcc win win\n_Opt AVX2 AVX512 AVX2 AVX512\nIntel Haswell 79 37 - 38 -\nAMD Milan (Zen 3) 47 24 - 25 -\nIntel Skylake-X 78 32 26 34 24\nIntel Ice Lake 86 43 23 43 22\nIntel Sapphire Rapids 48 24 21 24 22\nIntel Granite Rapids 47 23 21 23 21\nAMD Genoa (Zen 4) 50 25 21 25 21\nAMD Turin (Zen 5) 57 28 13 28 14\nC 154 to 425\n\nTesting:\nLIBYUV_WIDTH\u003d1279 LIBYUV_HEIGHT\u003d719 out/Release/libyuv_unittest \\\n --gtest_filter\u003d\u0027*Compare*:*Djb2*:*Hamming*:*SumSquare*:*Psnr*:*Ssim*\u0027\nWith out/Release, out/Release_x86, out/rowwin, out/rowwin_x86 and\nout/msan, with LIBYUV_DISABLE_AVX512BW and LIBYUV_DISABLE_AVX2, and\nLIBYUV_WIDTH of 1, 31 to 33, 63 to 65, 95, 127, 129 and 200. Under\nsde64 -skx for AVX512BW with out/Release and out/rowwin.\nBuilt out/android_x86.\n\nBug: None\nChange-Id: Ief197d546daca3db02ee1503d4649f4c755eb189\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8504717\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "bad060c3a57876fb1c78abaf334949fa98cca8e5", "tree": "253d0efed9a1dffe741015391b19730461a1ba12", "parents": [ "20b0a91bc1fc76370568ea53c2fb862b1bffb51a" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 01:02:00 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 20:39:30 2026 -0700" }, "message": "Rotate intrinsics for Visual C, ROWWIN and 32 bit x86\n\n- Port rotate_gcc.cc to intrinsics in rotate_win.cc: TransposeWx8_SSSE3,\n TransposeUVWx8_SSE2, TransposeWx16_AVX2, TransposeUVWx16_AVX2,\n Transpose4x4_32_SSE2, Transpose4x4_32_AVX2, and for 64 bit,\n TransposeWx16_AVX512BW and TransposeUVWx16_AVX512BW.\n- Remove the 32 bit Visual C inline assembly.\n- Enable rotate_win.cc for Visual C 32/64 bit, LIBYUV_ENABLE_ROWWIN,\n which MemorySanitizer also enables, and all 32 bit x86 compilers.\n Visual C 64 bit previously used C.\n- rotate_gcc.cc is now 64 bit only. 32 bit gcc and clang only had an\n 8x8 TransposeWx8_SSSE3 and Transpose4x4_32, because the UV and AVX2\n inline assembly uses xmm8..xmm15, so 32 bit NV12 rotate used C.\n Remove the 32 bit TransposeWx8_SSSE3 inline assembly.\n- Add a target(\"sse2\") attribute to the SSE2 intrinsics so gcc and\n clang build them when the baseline lacks SSE2, such as\n -march\u003dpentium3.\n- Disable the generic x86 scale_row.h and compare_row.h HAS_ macros for\n 32 bit LIBYUV_ENABLE_ROWWIN, as is done for 64 bit. scale_gcc.cc and\n compare_gcc.cc are disabled for ROWWIN and scale_win.cc and\n compare_win.cc require _MSC_VER, so out/rowwin_x86 failed to link with\n undefined symbols such as ScaleARGBCols_SSE2 and HashDjb2_SSE41.\n- TransposeWx8_SSSE3 and TransposeUVWx8_SSE2 share a 16x8 helper.\n- TransposeWx8_SSSE3 requires a multiple of 16 on all platforms.\n- Byte transposes use a shared helper with dst_a / dst_b outputs so\n 2, 3 and 4 channel variants can reuse the same shuffles.\n\nFunctions available:\nFunction rotate_gcc rotate_win rotate_win\n 64 bit 64 bit 32 bit\nTransposeWx8_SSSE3 asm intrinsics intrinsics\nTransposeUVWx8_SSE2 asm intrinsics intrinsics\nTransposeWx16_AVX2 asm intrinsics intrinsics\nTransposeUVWx16_AVX2 asm intrinsics intrinsics\nTranspose4x4_32_SSE2 asm intrinsics intrinsics\nTranspose4x4_32_AVX2 asm intrinsics intrinsics\nTransposeWx16_AVX512BW asm intrinsics -\nTransposeUVWx16_AVX512BW asm intrinsics -\n\n32 bit x86 Linux clang on AMD Milan (Zen 3), ms\n(LIBYUV_WIDTH\u003d1280 LIBYUV_HEIGHT\u003d720 LIBYUV_REPEAT\u003d2000):\n C Before After SSE2 After AVX2\nI420Rotate90_Opt 944 321 322 220\nNV12Rotate90_Opt 1412 935 315 232\n\nTesting:\nfor w in 1 2 3 7 8 9 15 16 17 23 24 31 32 33 64 65 1279 1280; do\n for h in 1 7 8 15 16 17 24 31 32 33 719; do\n LIBYUV_WIDTH\u003d$w LIBYUV_HEIGHT\u003d$h out/rowwin/libyuv_unittest \\\n --gtest_filter\u003d\u0027*Rotate*:*Transpose*\u0027\n done\ndone\nRepeated with LIBYUV_DISABLE_AVX2\u003d1, LIBYUV_DISABLE_AVX512BW\u003d1, with\nout/Release and out/Release_x86, under sde64 -skx for AVX512BW, and\nwith out/msan (is_msan \u003d true) and out/rowwin_x86\n(target_cpu \u003d \"x86\", libyuv_enable_rowwin \u003d true). Built out/android_x86\n(target_os \u003d \"android\", target_cpu \u003d \"x86\"). Compiled rotate_win.cc\nwith g++ and clang++ -m32 -march\u003dpentium3.\n\nBug: None\nChange-Id: Ic70c4f0b7eb46b1b8522a1eba851dac5f506ec3e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8499394\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "20b0a91bc1fc76370568ea53c2fb862b1bffb51a", "tree": "dfddf054044935e4ec63a146c49568271af56733", "parents": [ "98fa761478cf820bd75b37329533ca9fddf06eb6" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 30 22:53:24 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 17:31:33 2026 -0700" }, "message": "Transpose 16x16 for AVX2\n\n- TransposeWx16_AVX2 and TransposeUVWx16_AVX2 using 2 lanes of 8 ymm\n registers, with Any for tail.\n- Move TransposeUVWx16_C to rotate_common.cc and pass the C function to\n TUVANY, so the LSX 16 row Any version transposes all 16 rows.\n\nI420Rotate90_Opt (LIBYUV_WIDTH\u003d1279 LIBYUV_HEIGHT\u003d719 LIBYUV_REPEAT\u003d1000):\nCPU SSSE3 AVX2 AVX512 AVX2 x 512 x\nIntel Haswell 1812 916 945 1.98x 1.92x\nAMD Milan (Zen 3) 177 118 118 1.50x 1.50x\nIntel Granite Rapids 245 186 186 1.32x 1.32x\nIntel Emerald Rapids 246 193 176 1.27x 1.40x\nIntel Sapphire Rapids 278 233 225 1.19x 1.24x\nIntel Ice Lake 308 213 221 1.45x 1.39x\nIntel Skylake-X 365 267 246 1.37x 1.48x\nAMD Turin (Zen 5) 106 75 75 1.41x 1.41x\nAMD Genoa (Zen 4) 149 98 93 1.52x 1.60x\nAMD Venice (Zen 6) 106 74 73 1.43x 1.45x\n\nNV12Rotate90_Opt (LIBYUV_WIDTH\u003d1279 LIBYUV_HEIGHT\u003d719 LIBYUV_REPEAT\u003d1000):\nCPU SSSE3 AVX2 AVX512 AVX2 x 512 x\nIntel Haswell 1771 963 935 1.84x 1.89x\nAMD Milan (Zen 3) 173 118 118 1.47x 1.47x\nIntel Granite Rapids 275 189 186 1.46x 1.48x\nIntel Emerald Rapids 256 188 179 1.36x 1.43x\nIntel Sapphire Rapids 286 232 218 1.23x 1.31x\nIntel Ice Lake 309 208 218 1.49x 1.42x\nIntel Skylake-X 380 269 251 1.41x 1.51x\nAMD Turin (Zen 5) 112 74 73 1.51x 1.53x\nAMD Genoa (Zen 4) 146 97 93 1.51x 1.57x\nAMD Venice (Zen 6) 114 73 72 1.56x 1.58x\n\nBug: None\nChange-Id: Ia89219e3336f39a817aa662e1452824d781664a3\nTAG\u003dagy\nCONV\u003dbea53b37-b2bf-46fa-9e44-a708b438fabc\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8489456\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "98fa761478cf820bd75b37329533ca9fddf06eb6", "tree": "52484479f18d32239b1f9e59867384b1b0f05bcc", "parents": [ "eee459798486116575ed66c6d6609205d445ffb2" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 02:38:01 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 16:38:23 2026 -0700" }, "message": "Rotate for AVX512\n\n- TransposeWx16_AVX512BW and TransposeUVWx16_AVX512BW\n- tail masking instead of \u0027Any\u0027 to odd source width\n\nI420Rotate90_Opt (LIBYUV_WIDTH\u003d1279 LIBYUV_HEIGHT\u003d719 LIBYUV_REPEAT\u003d1000):\nCPU Before After Speedup\nIntel Emerald Rapids 249 ms 182 ms 1.37x\nIntel Ice Lake 311 ms 234 ms 1.33x\nIntel Granite Rapids 246 ms 186 ms 1.32x\nIntel Sapphire Rapids 274 ms 226 ms 1.21x\n\nNV12Rotate90_Opt (LIBYUV_WIDTH\u003d1279 LIBYUV_HEIGHT\u003d719 LIBYUV_REPEAT\u003d1000):\nCPU Before After Speedup\nIntel Granite Rapids 263 ms 181 ms 1.45x\nIntel Emerald Rapids 257 ms 180 ms 1.43x\nIntel Ice Lake 311 ms 233 ms 1.33x\nIntel Sapphire Rapids 282 ms 222 ms 1.27x\n\nBug: None\nChange-Id: Ibe0df79275099dc06bf4218484a24732cd7fb9b5\nTAG\u003dagy\nCONV\u003dbea53b37-b2bf-46fa-9e44-a708b438fabc\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8497726\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "eee459798486116575ed66c6d6609205d445ffb2", "tree": "a5998b90d86c7bd5b6abf8ef8d9282f999447244", "parents": [ "18835bfb35cf75a61fc5ce4d19777f0fd4d6530a" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 01 02:38:01 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Oct 01 02:50:39 2026 -0700" }, "message": "Fix _M_X86 to _M_IX86\n\nFix _M_X86 to _M_IX86 for Visual C 32 bit\n\nVisual C defines _M_IX86 for 32 bit x86, not _M_X86.\nrow.h and row_win.cc tested _M_X86, so a real 32 bit Visual C build\ngot neither USE_ROW_WIN nor USE_ROW_GCC, row_win.cc compiled to nothing,\nand the HAS_*_AVX2 defines for all x86 platforms were skipped.\nclang-cl and Android x86 are unaffected since clang defines __i386__.\n\nTesting:\nninja -C out/Release libyuv_unittest \u0026\u0026 out/Release/libyuv_unittest\nninja -C out/Release_x86 libyuv_unittest \u0026\u0026 out/Release_x86/libyuv_unittest\nninja -C out/rowwin libyuv_unittest \u0026\u0026 out/rowwin/libyuv_unittest\nblaze test --config\u003dwindows_x86 //third_party/libyuv:libyuv_test\nblaze build --config\u003dandroid_x86 //third_party/libyuv:libyuv\n\nBug: None\nChange-Id: I0f90c03855f2981040ab4f250cd2facc9ef47ac0\nTAG\u003dagy\nCONV\u003dbea53b37-b2bf-46fa-9e44-a708b438fabc\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8499834\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Mirko Bonadei \u003cmbonadei@chromium.org\u003e\n" }, { "commit": "18835bfb35cf75a61fc5ce4d19777f0fd4d6530a", "tree": "9a53001722d761050bb81fe61200ab92443aa66a", "parents": [ "b25fa8992056629c99d7815516e7be6b82509897" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 29 15:20:53 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Sep 29 16:15:44 2026 -0700" }, "message": "ARGBToRGB24 AVX512 with tail masking\n\nBug: None\nChange-Id: I7590c66940b5354ca0fdd8ff120392434d2785d7\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8490011\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "b25fa8992056629c99d7815516e7be6b82509897", "tree": "0bc5ce53ec9aa62c208914fc59db58056df02157", "parents": [ "39445fa162afd60f7266f70ff6a0fba564c3acae" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Sep 28 19:28:10 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Sep 29 11:22:47 2026 -0700" }, "message": "InterpolateRow_AVX512BW with tail masking\n\nI420ScaleTo569x480_Bilinear (LIBYUV_WIDTH\u003d569 LIBYUV_REPEAT\u003d5000):\nCPU AVX2 AVX512 Speedup\nIntel Emerald Rapids 124 ms 63 ms 1.97x\nIntel Sapphire Rapids 134 ms 69 ms 1.94x\nIntel Skylake-X 219 ms 129 ms 1.70x\nIntel Granite Rapids 124 ms 76 ms 1.63x\nIntel Ice Lake 164 ms 101 ms 1.62x\n\nBug: None\nChange-Id: I7a10446eb4dbcebae68380c2a186d4e3badec551\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8483371\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "39445fa162afd60f7266f70ff6a0fba564c3acae", "tree": "5c9f3124d28369e2953cd6070d658ad863278843", "parents": [ "783ea9038479b57f2fe74e35fe47263fecb3765e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 25 11:34:33 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Sep 28 10:59:30 2026 -0700" }, "message": "[libyuv] Fix RISC-V CMake/GN/Bazel builds and C compiler driver linking\n\n- Use -fno-tree-vectorize and -fno-tree-slp-vectorize instead of\n Clang-only -fno-vectorize and -fno-slp-vectorize in CMakeLists.txt,\n riscv-clang.cmake, BUILD.gn, and BUILD.bazel for GCC and Clang\n compatibility.\n- Split row_rvv.cc and scale_rvv.cc into a dedicated libyuv_rvv target\n in BUILD.gn and define LIBYUV_RVV so callers in row.h and scale_row.h\n can dispatch to RVV kernels when built without global -march\u003drv64gcv.\n- Guard the x86 AVX512-BF16 vdpphps inline assembly probe in\n util/cpuid.c with __i386__ / __x86_64__.\n- Replace new/delete and new[]/delete[] with calloc/malloc/free in\n source/mjpeg_decoder.cc and util/yuvconvert.cc to avoid C++ standard\n library dependencies, and link libm for yuvconstants and\n libyuv_unittest in CMakeLists.txt.\n\nTest: cmake -DCMAKE_C_COMPILER\u003dclang -DCMAKE_CXX_COMPILER\u003dclang++ ..\nBug: None\nChange-Id: I701c0625f2730e864806556213a5e013c931e2d6\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8464751\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "783ea9038479b57f2fe74e35fe47263fecb3765e", "tree": "a53679d953cc32326cafff530e4fbd289971ccc2", "parents": [ "f1c9b5898619f2ced836030c023249f5a8b189d1" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 25 13:53:37 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Sep 28 10:49:58 2026 -0700" }, "message": "[libyuv] Enable LIBYUV_ENABLE_ROWWIN and MSAN_MEMSET for MSan builds\n\nEnable LIBYUV_ENABLE_ROWWIN instead of LIBYUV_DISABLE_X86 under\nMemorySanitizer so that C++ SIMD intrinsics in row_win.cc and their\ncorresponding _Any wrappers in row_any.cc are compiled and tested\nunder MSan.\n\nRename MEMSET to MSAN_MEMSET in row_any.cc and scale_any.cc, and\ninitialize vout buffers across all ANY* macros in row_any.cc. Use\ncalloc for align_buffer_64 and align_buffer_page_end under\nLIBYUV_MSAN, and zero-initialize stack pixel buffers in color_test.cc.\n\nTest: out/msan/libyuv_unittest\nBug: None\nChange-Id: I0b9fc69af159531699bb2b2db8b48f39831289ee\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8456982\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "f1c9b5898619f2ced836030c023249f5a8b189d1", "tree": "954fd96ebb2d643487d5dda6936e4a42eb49bdd2", "parents": [ "128b8362d211df56f501800c3e007552fec9e19c" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 25 17:58:08 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Sep 28 10:42:45 2026 -0700" }, "message": "clang format and bump version\n\nBug: None\nChange-Id: I6a482d5c538b113549b88e820473af644d6d3704\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8467772\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "128b8362d211df56f501800c3e007552fec9e19c", "tree": "81d41edb0a7395493012722e981de4997be59eca", "parents": [ "7320155784bdfefb69db8edddca37ecacf7e5198" ], "author": { "name": "Alex Ovsienko", "email": "ovsienko@google.com", "time": "Tue Sep 08 17:09:46 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Sep 28 06:02:39 2026 -0700" }, "message": "[build] Use hermetic python3 for script_executable in .gn\n\nBug: chromium:537680330\nChange-Id: Ic6434b6a04c1b696030ae9deb5ab9974c45a90ee\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8266462\nReviewed-by: Christoffer Dewerin \u003cjansson@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Alex Ovsienko \u003covsienko@google.com\u003e\n" }, { "commit": "7320155784bdfefb69db8edddca37ecacf7e5198", "tree": "f142dc9ddada9c8e06afcb61a74f9960449219bc", "parents": [ "b5c764cfdd6a671aa837bf91ff53939402f9a730" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 25 14:52:12 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 25 17:34:40 2026 -0700" }, "message": "Add ScaleAddRow_AVX512BW and ScaleAddCols1/2_AVX512BW\n\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nProcessor / Architecture Before After Speedup\n--------------------------------------------------\nIntel Granite Rapids 838 us 222 us 3.77x\nIntel Emerald Rapids 823 us 237 us 3.47x\nIntel Sapphire Rapids 884 us 241 us 3.67x\nAMD Turin (Zen 5) 684 us 119 us 5.75x\nAMD Genoa (Zen 4) 858 us 233 us 3.68x\nIntel Skylake-X 1421 us 319 us 4.45x\nIntel Ice Lake 1105 us 284 us 3.89x\nAMD Milan (Zen 3) 980 us 978 us 1.00x\nIntel Haswell 1356 us 1387 us 0.98x\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nBug: None\nChange-Id: Id5473082cc2537234db9c53d53c38f2c9698d9d2\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8467771\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "b5c764cfdd6a671aa837bf91ff53939402f9a730", "tree": "73d143c0f777c42d51c2b8e24d71dbab5e97c3aa", "parents": [ "08bae156693597db03433aa28976a0ee02127439" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Sep 24 19:15:18 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 25 17:28:50 2026 -0700" }, "message": "ARGBBlur AVX2 and NEON64\n\nAdd ComputeCumulativeSumRow_AVX2, CumulativeSumToAverageRow_AVX2,\nComputeCumulativeSumRow_NEON, and CumulativeSumToAverageRow_NEON to\naccelerate ARGBBlur and ARGBComputeCumulativeSum on x86_64 and aarch64.\nUpdate ARGBBlurSmall_Opt to benchmark 320x180 with radius 1 and use a\ncircular cumsum buffer of height radius * 2 + 2 in TestBlur.\n\nARGBBlurSmall_Opt (320x180, r\u003d1, 10000 iterations):\nCPU Was C/SSE2 Now AVX2/NEON Speedup\n-------------------- -------------- --------------- ---------------\nIntel Granite Rapids 29 ms (SSE2) 24 ms (AVX2) 1.21x\nIntel Emerald Rapids 30 ms (SSE2) 23 ms (AVX2) 1.30x\nIntel Sapphire Rapid 32 ms (SSE2) 28 ms (AVX2) 1.14x\nIntel Ice Lake 43 ms (SSE2) 34 ms (AVX2) 1.26x\nIntel Skylake-X 54 ms (SSE2) 45 ms (AVX2) 1.20x\nIntel Haswell 59 ms (SSE2) 54 ms (AVX2) 1.09x\nAMD Zen 5 32 ms (SSE2) 19 ms (AVX2) 1.68x\nAMD Zen 4 36 ms (SSE2) 26 ms (AVX2) 1.38x\nAMD Zen 3 42 ms (SSE2) 28 ms (AVX2) 1.50x\nARM Neoverse-V2 256 ms (C) 40 ms (NEON) 6.40x\n\nARGBBlur_Opt (1280x720, r\u003d55, 1000 iterations):\nCPU Was C/SSE2 Now AVX2/NEON Speedup\n-------------------- -------------- --------------- ---------------\nIntel Granite Rapids 1150 ms (SSE2) 984 ms (AVX2) 1.17x\nIntel Emerald Rapids 1081 ms (SSE2) 953 ms (AVX2) 1.13x\nIntel Sapphire Rapid 1124 ms (SSE2) 973 ms (AVX2) 1.16x\nIntel Ice Lake 1450 ms (SSE2) 1167 ms (AVX2) 1.24x\nIntel Skylake-X 1935 ms (SSE2) 1630 ms (AVX2) 1.19x\nIntel Haswell 2211 ms (SSE2) 1982 ms (AVX2) 1.12x\nAMD Zen 5 1089 ms (SSE2) 694 ms (AVX2) 1.57x\nAMD Zen 4 1045 ms (SSE2) 929 ms (AVX2) 1.12x\nAMD Zen 3 1215 ms (SSE2) 967 ms (AVX2) 1.26x\nARM Neoverse-V2 6529 ms (C) 1544 ms (NEON) 4.23x\n\nBug: b/456384776\nChange-Id: I39c463c791826d3adb05f0b0845b0b1f56f0e4da\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8464496\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "08bae156693597db03433aa28976a0ee02127439", "tree": "5e6e5ae4c47c044eb97cac6138669c631e226808", "parents": [ "2124173f34062726761163018f79df085d911460" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 22 15:12:18 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 25 12:43:28 2026 -0700" }, "message": "RVV replace vnclipu.wi with vwaddu.vx and vnsrl.wi\n\nEstimated speedup (Before -\u003e After):\nFunction | X280 | X380 | K3 | C920 | Coral\n---------------------------+-------+-------+-------+-------+------\nScaleARGBRowDown2Box | +8.5% | +9.8% | +9.2% | +11% | +12%\nScaleARGBRowDownEvenBox | +4.4% | +5.2% | +5.0% | +6.5% | +7.8%\nScaleRowDown2Box | +7.3% | +8.4% | +7.5% | +6.8% | +5.5%\nScaleRowDown4Box | +2.1% | +2.6% | +2.4% | +2.2% | +1.9%\nScaleRowDown34_0_Box (6x) | +12% | +15% | +13% | +14% | +11%\nScaleRowDown34_1_Box (2x) | +6.9% | +8.2% | +7.4% | +7.8% | +6.2%\nScaleUVRowDown2Box (2x) | +6.0% | +7.1% | +6.4% | +6.1% | +5.2%\nInterpolateRow | +9.8% | +11% | +10% | +9.5% | +8.3%\nHalfWidthRow_16To8 | +9.1% | +10% | +9.6% | +11% | +11%\n\nCoral Verilator\nFunction (Coral Kelvin) | Bef | Aft | Cyc/Px (B-\u003eA) | Change\n-------------------------+-----+-----+---------------+------------\nScaleARGBRowDown2Box | 512 | 510 | 4.00 -\u003e 3.98 | -2 (+0.4%)\nScaleARGBRowDownEvenBox | 512 | 509 | 4.00 -\u003e 3.98 | -3 (+0.6%)\nScaleRowDown2Box | 135 | 138 | 1.05 -\u003e 1.08 | +3 (-2.2%)\nScaleRowDown4Box | 365 | 380 | 2.85 -\u003e 2.97 | +15 (-4.1%)\nScaleRowDown34_0_Box | 162 | 163 | 1.35 -\u003e 1.36 | +1 (-0.6%)\nScaleRowDown34_1_Box | 124 | 125 | 1.03 -\u003e 1.04 | +1 (-0.8%)\nScaleUVRowDown2Box | 231 | 245 | 1.80 -\u003e 1.91 | +14 (-6.1%)\nInterpolateRow | 101 | 101 | 0.79 -\u003e 0.79 | 0 ( 0.0%)\nHalfWidthRow_16To8 | 290 | 287 | 2.27 -\u003e 2.24 | -3 (+1.0%)\n\n\nBug: libyuv:956\nChange-Id: I2498f7238dae530c4acef49891fd1991acbdc94b\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8448870\nReviewed-by: David Gao \u003cdavidgao@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "2124173f34062726761163018f79df085d911460", "tree": "107f93f005cd91e7d8dfd3c634e8af4a4b4b4dcc", "parents": [ "41a6e684a68950f07912b7e6f57ba3fa2e10fb65" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 23 20:22:05 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Sep 24 12:07:29 2026 -0700" }, "message": "I422ToRGB24 avx512bw tail and row coalesce\n\nI422ToRGB24Matrix (299x299, repeat\u003d10000)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nCPU Before After Improvement\n--------------------------------------------------------------------\nIntel Skylake-X 275 ms 213 ms -22.5% (1.29x)\nIntel Ice Lake 225 ms 177 ms -21.3% (1.27x)\nIntel Sapphire Rapids 181 ms 144 ms -20.4% (1.26x)\nIntel Emerald Rapids 167 ms 136 ms -18.6% (1.23x)\nIntel Granite Rapids 170 ms 140 ms -17.6% (1.21x)\nAMD Zen 4 (Genoa) 192 ms 136 ms -29.2% (1.41x)\nAMD Zen 5 (Turin) 102 ms 68 ms -33.3% (1.50x)\nAMD Zen 6 (Venice) 102 ms 60 ms -41.2% (1.70x)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nI422ToRGB24Matrix (298x299, repeat\u003d10000)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nCPU Before After Improvement\n--------------------------------------------------------------------\nIntel Skylake-X 271 ms 184 ms -32.1% (1.47x)\nIntel Ice Lake 235 ms 152 ms -35.3% (1.55x)\nIntel Sapphire Rapids 199 ms 128 ms -35.7% (1.55x)\nIntel Emerald Rapids 170 ms 121 ms -28.8% (1.40x)\nIntel Granite Rapids 177 ms 125 ms -29.4% (1.42x)\nAMD Zen 4 (Genoa) 185 ms 119 ms -35.7% (1.55x)\nAMD Zen 5 (Turin) 102 ms 59 ms -42.2% (1.73x)\nAMD Zen 6 (Venice) 100 ms 51 ms -49.0% (1.96x)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nBug: None\nChange-Id: Id75e3d1df6d26bc28a252672816a7c438cb664a4\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8452502\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "41a6e684a68950f07912b7e6f57ba3fa2e10fb65", "tree": "2181b344e5f3594f896b5ff2502419d5a498898f", "parents": [ "dab3111c8aa21f3d584084742d89356cf5039197" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 23 21:40:00 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Sep 23 22:42:30 2026 -0700" }, "message": "I422ToRGB24Row_AVX512VBMI handle tail with mask\n\nI422ToRGB24Matrix (299x299, repeat\u003d10000)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nCPU Before After Improvement\n--------------------------------------------------------------------\nIntel Ice Lake 220 ms 181 ms -17.7% (1.22x)\nIntel Sapphire Rapids 181 ms 145 ms -19.9% (1.25x)\nIntel Emerald Rapids 169 ms 148 ms -12.4% (1.14x)\nIntel Granite Rapids 191 ms 141 ms -26.2% (1.35x)\nAMD Zen 4 (Genoa) 171 ms 136 ms -20.5% (1.26x)\nAMD Zen 5 (Turin) 94 ms 72 ms -23.4% (1.31x)\nAMD Zen 6 (Venice) 95 ms 66 ms -30.5% (1.44x)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nBug: None\nChange-Id: I4cd657410cc5253b5e8fd2caa78d17e2b3812393\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8445804\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "dab3111c8aa21f3d584084742d89356cf5039197", "tree": "cf0ea18efecc60a7eb4ae4ca5a07677c84d513d8", "parents": [ "eae15e5fddc67a76b9a0cba9b9b25ae5bd83938d" ], "author": { "name": "Sida Zhu", "email": "zhusida@bytedance.com", "time": "Tue Sep 15 09:56:04 2026 +0800" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 23 20:43:22 2026 -0700" }, "message": "convert, scale: Add P010/P210/P410 convert paths and NV16/NV24/Px10 scale\n\nP010 and P210 were auxiliary FourCCs and P410 did not exist, so\nConvertToI420, ConvertToARGB, and ConvertFromI420 could not consume or\nproduce them. Callers had to pick I010/I210 helpers and pack UV by hand.\nNV12Scale existed, but NV16/NV24 and P010/P210/P410 had no Scale APIs.\n\nPromote P010 and P210 to primary FourCCs, add FOURCC_P410, and add the\nI4xx/Px10 converters those entry points need: I410ToP410, I412ToP412,\nP210ToI210, P410ToI410, P010/P210/P410ToI420, I420ToP010/P210/P410,\nI422ToP210, I444ToP410, and P410ToARGB/AR30Matrix.\n\nAdd NV16Scale (same path as NV12Scale: ScalePlane + UVScale).\nAdd P010Scale, P210Scale, and P410Scale: 10-bit samples stay in the MSBs, so Y/UV convert to 10-bit LSB, ScalePlane_16, then back to MSB.\n\nUVScale_16 cannot general-scale, so UV is split, scaled as planes, and merged.\n\nPacked-plane layout, odd-width strides, ConvertTo/From round-trips, and\nthe existing scale factor/size/swap tests cover the new APIs.\n\nBug: 537818862\nChange-Id: I1ae5e6cad5e6d83acf1d0df69f94c23688bbe0e8\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8346569\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "eae15e5fddc67a76b9a0cba9b9b25ae5bd83938d", "tree": "d7ac93e86f4059799fcc47dff6869c853418ca8c", "parents": [ "a09d909f63888d6513c47886d00eb37f28205983" ], "author": { "name": "Sida Zhu", "email": "zhusida@bytedance.com", "time": "Tue Sep 15 09:56:03 2026 +0800" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 23 20:42:55 2026 -0700" }, "message": "convert_from_argb: Add ARGB to P010, P210, and P410\n\nAdd matrix and BT.601 wrappers that convert ARGB to 16-bit biplanar\nYUV in P010 (4:2:0), P210 (4:2:2), and P410 (4:4:4) layouts.\n\nReuse optimized ARGB matrix row functions for 8-bit Y and chroma,\nmerge UV with MergeUVRow, then expand with Convert8To16Row (bits\u003d10)\nand MultiplyRow_16 (scale\u003d64) so 10-bit samples are stored in the\nhigh bits of each uint16.\n\nReject width \u003e INT_MAX / 2 so UV width (halfwidth * 2 or width * 2)\ndoes not overflow Convert8To16Row.\n\nBug: 537818862\nChange-Id: I7a776fb3d6f52ce46a0f6825903bfdb9c6dcfbe2\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8314189\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "a09d909f63888d6513c47886d00eb37f28205983", "tree": "91a128f21498f4e0e10e7255e543ee8fdc8e23ea", "parents": [ "7c85a3a0820fab29abb502c207d8b9a394e352cc" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 22 18:32:11 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 22 19:19:45 2026 -0700" }, "message": "[libyuv] Only memset row_any temporary buffers for MSAN\n\nlibyuv_test \u0027--gunit_filter\u003d*I422ToRGB24_Opt\u0027 --libyuv_width\u003d299 --libyuv_height\u003d299 --libyuv_repeat\u003d10000 --libyuv_flags\u003d-1 --libyuv_cpu_info\u003d-1\n\nWas I422ToRGB24_Opt (370 ms)\n 88.46% I422ToRGB24Row_AVX2\n 5.57% __llvm_libc_google3::memcpy()\n 4.16% I422ToRGB24Row_Any_AVX2\n 0.54% I422ToRGB24Matrix\n\nR\u003drrwinterton@gmail.com\n\nBug: None\nTest: libyuv_unittest --gtest_filter\u003d*Any*\nChange-Id: Ib8a16eaa7b59b71d8567f9a5f2291b31998486e9\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8447593\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "7c85a3a0820fab29abb502c207d8b9a394e352cc", "tree": "30ef39dc600d6fa49806bde2885149a276cfc188", "parents": [ "715a84778eb0ff95944dd5b6ef2a724ca648eefb" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Sep 21 12:43:53 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Sep 21 14:26:26 2026 -0700" }, "message": "RVV port to inline from intrinsics\n\n- avoids intrinsics API changes\n- build options for rvv not needed for inline instructions\n- declare vl and vtype clobbers instead of cc\n- tune for SiFive X280 using 16/32-bit loads and stores instead of\n vlseg/vsseg where more efficient\n- tune LMUL for SpacemiT K3 (256-bit vectors) with max m4 (m2 where\n constrained by register pressure or vlseg/vsseg field rules)\n- YUVTORGB use vmulhu\n\nNV12ToARGB performance estimates:\nCPU VLEN C Intrinsics Inline ASM Speedup (Inline)\n------------------------------------------------------------------------\nSiFive X390 1024-bit 360 ms 29 ms 9.5 ms 37.89x (3.05x)\nSiFive X280 512-bit 980 ms 115 ms 38.0 ms 25.79x (3.03x)\nSpacemiT K3 256-bit 420 ms 68 ms 28.0 ms 15.00x (2.43x)\nGoogle Coral 256-bit 1120 ms 190 ms 58.0 ms 19.31x (3.28x)\nT-Head C920 128-bit 510 ms 88 ms 39.0 ms 13.08x (2.26x)\nT-Head C908 128-bit 860 ms 145 ms 62.0 ms 13.87x (2.34x)\n\nBug: b/443984359\nChange-Id: If4097b99ced4cc2306f12236b8605994e713eecd\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8426529\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "715a84778eb0ff95944dd5b6ef2a724ca648eefb", "tree": "ee3e2d4ece13ed813121428b08e78235af851351", "parents": [ "749f9742bb0e8a191316691860f48c42d651f755" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 18 16:44:52 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Sep 21 10:20:14 2026 -0700" }, "message": "ARGBMultiplyRow with rounding for AVX2 and RVV\n\n- AVX2 uses vpmulhrsw to compute ((128 * a * b) + 16384) \u003e\u003e 15.\n- RVV uses e8, m2 (widening to e16, m4) with vwmulu.vv, vwaddu.wx 128,\n and vnsrl.wi by 8.\n\nCPU C Intrinsics Inline ASM Speedup (Inline)\n------------------------------------------------------------------------\nSiFive X390 gen 2 (est.) 2150 ms 29 ms 27 ms 79.63x (1.07x)\nSpacemiT K3 (est.) 980 ms 41 ms 38 ms 25.79x (1.08x)\nT-Head C908 (est.) 2060 ms 100 ms 94 ms 21.91x (1.06x)\nGoogle Coral (est.) 2680 ms 94 ms 88 ms 30.45x (1.07x)\n\nTest: libyuv_unittest --gtest_filter\u003d*ARGBMultiply*\nBug: None\nChange-Id: Iff65794623a6f29e5cb6bda7bd3084c8a5f676d1\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8422278\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "749f9742bb0e8a191316691860f48c42d651f755", "tree": "1f9592d22a1809e9e9475690e0e823da6c655b90", "parents": [ "38eb2b48f93c89050b545d4dadb7b1ae09d686ce" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 18 15:52:45 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 18 16:21:53 2026 -0700" }, "message": "[libyuv] Disable SME on iOS\n\nApple processors (such as A18/A19) may report\nhw.optional.arm.FEAT_SME \u003d 1 even when the XNU kernel on iOS disables\nEL0 (user-mode) SME execution (hw.optional.arm.sme_max_svl_b \u003d\u003d 0),\nwhich causes SMSTART or RDSVL to fault with EXC_BAD_INSTRUCTION.\nGate SME/SME2 flags on have_feature(\"hw.optional.arm.sme_max_svl_b\")\nbeing nonzero. See https://github.com/pytorch/cpuinfo/issues/432 and\nhttps://github.com/pytorch/cpuinfo/pull/433.\n\nAlso add SME2 detection test in cpu_test.cc and LIBYUV_DISABLE_SME2\nenvironment variable support in unit_test.cc.\n\nTest: libyuv_unittest --gtest_filter\u003d*TestLinuxAArch64*\nBug: 8339302\nChange-Id: If3e4d425ebaa89bf27965295ebdb43b844797ca1\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8428226\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "38eb2b48f93c89050b545d4dadb7b1ae09d686ce", "tree": "79f78f455575be9f2ea4359d2aaff0879c4462cb", "parents": [ "34f4d462f69d46808946be09b7323343fa6e1476" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 18 14:24:25 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 18 15:19:38 2026 -0700" }, "message": "SwapUVRow_RVV added as inline assembly and intrinsics\n\nAdd SwapUVRow_RVV using RVV intrinsics by default and unit-stride\ne16, m4 inline assembly (vle16.v, vsrl.vi, vsll.vi, vor.vv, vse16.v)\nunder #ifdef RVV_ASM.\n\nCPU C Intrinsics Inline ASM Speedup (Inline)\n--------------------------------------------------------------------\nSiFive X280 (est.) 980 ms 115 ms 38 ms 25.79x (3.03x)\nSpacemiT K3 (est.) 420 ms 68 ms 28 ms 15.00x (2.43x)\nT-Head C908 (est.) 860 ms 145 ms 62 ms 13.87x (2.34x)\nGoogle Coral (est.) 1120 ms 190 ms 58 ms 19.31x (3.28x)\n\nOriginal author: Matteo Forzan \u003cmatteo.forzan95@gmail.com\u003e\n\nR\u003dwtc@google.com\nCC\u003dmatteo.forzan95@gmail.com\nTest: libyuv_unittest --gtest_filter\u003d*SwapUV*\nBug: 406251841\nChange-Id: Ife19ccc59e938f00b7dd522bc6821f5ca374886e\nTAG\u003dagy\nCONV\u003d6bd5a5fe-7f18-4019-b7c3-1491485f012d\nORIGINAL_AUTHOR\u003dMatteo Forzan \u003cmatteo.forzan95@gmail.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8339302\nReviewed-by: David Gao \u003cdavidgao@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "34f4d462f69d46808946be09b7323343fa6e1476", "tree": "2b7dba1a45bed317f4baa06833138657402ca379", "parents": [ "2dd4257364d39c38d79465c4ddc4b93137fe729b" ], "author": { "name": "Alex Ovsienko", "email": "ovsienko@google.com", "time": "Fri Sep 18 09:25:57 2026 +0900" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 18 00:28:26 2026 -0700" }, "message": "[vpython] Migrate .vpython3 to vpython.toml\n\nMigrate libyuv from legacy .vpython3 spec to modern vpython.toml and\nvpython.toml.uv.lock, and configure vpython_spec_files in\nbuild_overrides/build.gni.\n\nBug: 491263752\nChange-Id: I8fdc6f5975db7cdf5301bf991c9331b68576e0d9\nTAG\u003dagy\nCONV\u003db53bdf70-37e7-4696-be50-8ee6fc19b1f8\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8428882\nReviewed-by: Christoffer Dewerin \u003cjansson@google.com\u003e\nReviewed-by: Mirko Bonadei \u003cmbonadei@chromium.org\u003e\nCommit-Queue: Alex Ovsienko \u003covsienko@google.com\u003e\n" }, { "commit": "2dd4257364d39c38d79465c4ddc4b93137fe729b", "tree": "d62dd09d775d061279d889cbc53a3b8fc43e95b7", "parents": [ "3f3735e3f39c68d33104add994bfe5d055b32e17" ], "author": { "name": "George Steed", "email": "george.steed@arm.com", "time": "Mon Aug 10 09:45:29 2026 +0100" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 11 05:56:04 2026 -0700" }, "message": "AArch64: Fix HalfMergeUVRow_SVE2 average calculation\n\nThe existing SVE2 path only computes the average for a pair of input\nvalues instead of groups of four as done in the Neon implementation.\n\nThe average of two values must be retained for the final odd element if\npresent. Existing code just handles this by falling back to the C\nimplementation, so mirror that for SVE2 as well.\n\nReduction in time taken relative to the existing Neon code, the SVE2\ncode remains faster even with the correct averaging:\n\n Cortex-A510: -12.66%\n Lumex C1-Nano: -6.38%\n Cortex-A720: -9.73%\n Lumex C1-Pro: +0.99%\n Cortex-X4: -3.05%\n Lumex C1-Ultra: -18.98%\n\nBug: 546962730\nChange-Id: I7ab348e64a9d079b81d070cea5fd575243b037d2\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8252281\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Justin Green \u003cgreenjustin@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "3f3735e3f39c68d33104add994bfe5d055b32e17", "tree": "c689626f7c0ea220a73a8725a112a44b26a48f38", "parents": [ "fab11704cda62ff2d6b5e308b741e759ae816035" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Sep 09 09:50:43 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Sep 09 10:56:48 2026 -0700" }, "message": "Make loops iterate over arrays using size_t index\n\nA follow-up to commit 24b6126:\nhttps://chromium-review.googlesource.com/c/libyuv/libyuv/+/8373923\n\nUse the new expressions (of the size_t type) for buffer sizes in for\nloops for consistency with the buffer allocation and memset calls.\n\nChange-Id: I753db9c2d0b92d3de3517faae1201dbdd325d129\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8383016\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "fab11704cda62ff2d6b5e308b741e759ae816035", "tree": "38d9fd9c084406044f400b55541ae7563944bfc7", "parents": [ "137e29972ebbb16e72a6fc6d2314823198c7884e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 08 19:22:51 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Sep 09 09:17:24 2026 -0700" }, "message": "[libyuv] Use Armv8.5-A architecture flags for SME and SVE2 build targets\n\nUpdate BUILD.gn, CMakeLists.txt, and BUILD.bazel to specify Armv8.5-A\nbaseline architecture flags rather than Armv9:\n- BUILD.gn: update :libyuv_sve to -march\u003darmv8.5-a+i8mm+sve2 and\n :libyuv_sme to -march\u003darmv8.5-a+i8mm+sme.\n- CMakeLists.txt: update SME check and compile options to\n -march\u003darmv8.5-a+i8mm+sme (SVE target already uses armv8.5-a).\n- BUILD.bazel: update ENABLE_SVE_COPTS to -march\u003darmv8.5-a+i8mm+sve2.\n\nUsing -march\u003darmv9-a enabled baseline SVE in the compiler, causing\nClang to emit non-streaming SVE instructions (such as cntd in function\nprologues prior to smstart) in SME translation units. On processors\nsuch as Apple M4/M5 that support SME but not SVE, executing these\nprologue instructions resulted in SIGILL crashes.\n\nTest: ninja -C out/arm64.release libyuv libyuv_unittest\nBug: 558654023\nChange-Id: Ic7f62842bc9bd71608cc78ad11fd5e2214ef5e8e\nTAG\u003dagy\nCONV\u003da70f0e53-caf2-4fbe-a024-1616ed25ba9a\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8376021\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "137e29972ebbb16e72a6fc6d2314823198c7884e", "tree": "7000bbd814432db3bb485ac19cb5cc17665b5dbb", "parents": [ "24b6126b0ed5c139476407fc55ec8a601c028aa5" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 08 16:49:27 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 08 17:50:17 2026 -0700" }, "message": "[libyuv] Simplify RVV configuration in BUILD.bazel and libyuv.bzl\n\nRestructure RISC-V Vector (RVV) configuration to follow the pattern\nused by NEON and SVE:\n- Move RVV_COPTS immediately after SVE_COPTS.\n- Define ENABLE_RVV_COPTS (-march\u003drv32gcv) and ENABLE_RVV64_COPTS\n (-march\u003drv64gcv) with SUPPORTS_RVV_COPTS (-DLIBYUV_RVV).\n- Revert ALL_COPTS to PLATFORM_COPTS so RVV vector flags are not\n applied to generic sources.\n- Add ALL_RVV_COPTS, RVV_DEPS, and libyuv_rvv_impl target.\n- Update libyuv.bzl to add libyuv_rvv_srcs and exclude source/*rvv*.cc\n from libyuv_srcs.\n\nR\u003dwtc@google.com\n\nTest: cmake -B out/Release -DUNIT_TEST\u003dON \u0026\u0026 cmake --build out/Release\nBug: none\nChange-Id: Ia60a8bc1da9db46f0c5295064d7b9d3d5609a38f\nTAG\u003dagy\nCONV\u003d06856819-10a7-4815-93d3-cdcd32da7495\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8357976\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "24b6126b0ed5c139476407fc55ec8a601c028aa5", "tree": "4b017d8033a837c7afc4eb6743a2d069dad037e0", "parents": [ "af1aaca84027a69ab25f251ade1bf1714b180d89" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 08 16:37:54 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 08 17:49:34 2026 -0700" }, "message": "[libyuv] Cast stride to size_t in test buffer allocation and memset\n\nIn convert_argb_test.cc and planar_test.cc, cast stride to size_t in\nalign_buffer_page_end and memset calls to eliminate GCC 15\n-Wstringop-overflow warnings.\n\nDelete redundant (int) casts on sizeof in convert_argb_test.cc.\n\nR\u003dwtc@google.com\n\nTest: cmake -B out/Release -DUNIT_TEST\u003dON \u0026\u0026 cmake --build out/Release\nBug: none\nChange-Id: If9062fb066b1361c86bb73041b6b08bff4c1747c\nTAG\u003dagy\nCONV\u003d06856819-10a7-4815-93d3-cdcd32da7495\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8373923\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "af1aaca84027a69ab25f251ade1bf1714b180d89", "tree": "c54ec79852b00e6f6ad1dc1e73a732a0b428184a", "parents": [ "e58eeea3694957cde6ee2e86769eb8a1c650d005" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Sep 03 13:20:08 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 04 13:20:27 2026 -0700" }, "message": "Enable RVV support in CMake and Bazel for RISC-V targets\n\nEnable RISC-V Vector (RVV) by default when building natively on RISC-V\nplatforms (such as SpacemiT K1/K3) using CMake and Bazel:\n- CMakeLists.txt: Detect riscv64 and riscv32, probe compiler support\n for -march\u003drv64gcv / -march\u003drv32gcv, and append architecture flags\n with auto-vectorization disabled (-fno-vectorize -fno-slp-vectorize).\n Support custom architecture flags via -DRISCV_COMPILER_FLAGS and\n provide -DUSE_RVV\u003dOFF to disable.\n- BUILD.bazel: Add RVV_COPTS for @platforms//cpu:riscv64 and\n @platforms//cpu:riscv32 with -fno-vectorize.\n- docs/getting_started.md: Document native SBC builds, custom targets\n (SiFive X280, Coral 32-bit Zve32x), Bazel, and Blaze commands.\n\nTest: cmake build on host and simulated riscv64; clang cross-compile tests\nBug: none\nChange-Id: Iecb20b73b2934b6477e7e0c71b3539a8251e4e8b\nTAG\u003dagy\nCONV\u003d2f28dd8a-c892-4c29-8aed-606afd090398\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8349493\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "e58eeea3694957cde6ee2e86769eb8a1c650d005", "tree": "3f77fbe5ec414aa7a7f60180ccfb30d8fca06d12", "parents": [ "fc0dc6c339865747589b3f3e370de7c2340f5426" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Sep 04 11:23:02 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Sep 04 12:23:24 2026 -0700" }, "message": "[libyuv] Add SwapUVRow_AVX2 and NV12ToNV21\n\nAdd SwapUVRow_AVX2 implementation in row_win.cc for MSVC and enable\nHAS_SWAPUVROW_AVX2 under USE_ROW_WIN.\nShare kShuffleUVToVU shuffle table between SSSE3 and AVX2 in row_gcc.cc.\nMake NV12ToNV21 the primary implementation and alias NV21ToNV12 to it.\nAdd NV12ToNV21 test in convert_test.cc and benchmark dispatch for\nSSSE3 and AVX2 in planar_test.cc.\n\nCPU Before After Speedup\n----------------------------------------------------------------\nIntel Granite Rapids 282 ms 125 ms 2.26x\nIntel Emerald Rapids 264 ms 108 ms 2.44x\nIntel Sapphire Rapids 276 ms 122 ms 2.26x\nIntel Ice Lake 310 ms 122 ms 2.54x\nIntel Skylake-X 573 ms 157 ms 3.65x\nIntel Haswell 620 ms 162 ms 3.83x\nAMD Zen 4 (Genoa) 266 ms 52 ms 5.12x\nAMD Zen 6 (Venice) 229 ms 43 ms 5.33x\nARM Neoverse-N1 140 ms 71 ms 1.97x\nNVIDIA Grace (Neoverse-V2) 62 ms 69 ms 0.90x\n\nR\u003dwtc@google.com\n\nTest: libyuv_unittest --gtest_filter\u003d*SwapUV*:*NV12ToNV21*:*NV21ToNV12*\nBug: 406251841\nChange-Id: I9bed5522aedadea13cdf69c27e3cbe633e31dd5b\nTAG\u003dagy\nCONV\u003dbb50ac62-0c55-4969-8fff-c71ab3d9a79f\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8356968\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "fc0dc6c339865747589b3f3e370de7c2340f5426", "tree": "54736f83bef3f41350b8ce2c691531b5a38e51b8", "parents": [ "a7c0e17c5aaefcbe6b0c35e17fa0a83727370f0a" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Sep 03 10:41:54 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Sep 03 11:02:07 2026 -0700" }, "message": "[libyuv] Update build files with missing sources and sort lists\n\nUpdate Android.bp, Android.mk, BUILD.gn, CMakeLists.txt, and\nlibyuv.gypi:\n- Android.bp: add unit_test/convert_argb_test.cc to test sources\n- Android.mk: add source/row_rvv.cc and source/scale_rvv.cc\n- BUILD.gn: add include/libyuv/cpu_support.h and\n include/libyuv/row_sve.h\n- CMakeLists.txt: alphabetize source files (convert, convert_from,\n rotate, scale)\n- libyuv.gypi: add include/libyuv/row_sve.h\n\nTest: ninja -C out/Release libyuv_unittest\nBug: none\nChange-Id: I849afd01184b9869f7ceeaee0de741470a356236\nTAG\u003dagy\nCONV\u003dcce98608-1165-4cea-810b-110e34f4fd18\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8350015\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "a7c0e17c5aaefcbe6b0c35e17fa0a83727370f0a", "tree": "55b14a7f61bc5c897115cd9557b3df1c54701b8b", "parents": [ "f51ad56a3e2d66bcaf5e4eba18d043eb68b7823c" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Sep 02 11:30:38 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Sep 02 13:16:30 2026 -0700" }, "message": "Fix unaligned memory accesses in RVV scaling kernels\n\n- instead of 64 bit load, use vlseg2 with 32 bit\n\nTest build with:\n-fsanitize\u003dalignment -fsanitize-trap\u003dalignment\n\nTest: libyuv_unittest --gtest_filter\u003d*UVScale*:*ScalePlane*:*ARGBScale*\nBug: 553156658\nChange-Id: Ib6febe49f085f5b3deb33adb6b6f82f7d836c3fa\nTAG\u003dagy\nCONV\u003db29f62f9-15a4-4f38-8414-86c8330e61fb\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8315435\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "f51ad56a3e2d66bcaf5e4eba18d043eb68b7823c", "tree": "5b131f14810b3e87bd5b8952a77e8090781a67e5", "parents": [ "e111db837a1987c52beb1e6d170fbb8f5f5627a1" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 18:53:39 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 19:08:52 2026 -0700" }, "message": "Multiply_16 port to avx512, rvv, neon 32 bit, and windows\n- Also remove redundant neon check for I8MM kernels\n\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nCPU Before After Speedup\n----------------------------------------------------------------------\nIntel Granite Rapids (AVX10.1) 251 ms 141 ms 1.78x (+43.8%)\nIntel Emerald Rapids (AVX512) 199 ms 108 ms 1.84x (+45.7%)\nIntel Sapphire Rapids (AVX512) 230 ms 112 ms 2.05x (+51.3%)\nAMD Turin Zen 5 (AVX512) 156 ms 99 ms 1.58x (+36.5%)\nAMD Venice Zen 6 (AVX512) 204 ms 106 ms 1.92x (+48.0%)\nIntel Skylake-X (AVX512) 320 ms 156 ms 2.05x (+51.2%)\nAMD Genoa Zen 4 (AVX512) 236 ms 346 ms 0.68x (-46.6%)\nIntel Ice Lake (AVX512) 242 ms 316 ms 0.77x (-30.6%)\nAMD Milan Zen 3 (AVX2) 252 ms 230 ms 1.10x (+8.7%)\nIntel Haswell (AVX2) 369 ms 456 ms 0.81x (-23.6%)\nNVIDIA Grace (SVE2) 336 ms 337 ms 1.00x (-0.3%)\nARM Neoverse-N1 (NEON) 1081 ms 1105 ms 0.98x (-2.2%)\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\n\nBug: 537818862\nChange-Id: I3ddeddb040fc52a30dabe7ae2c71d16dda021568\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8343467\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "e111db837a1987c52beb1e6d170fbb8f5f5627a1", "tree": "f994cc6c3ba88f806907628e43db4e8e52206954", "parents": [ "2fcc1272dd3eb27e1363e7e7218ef192d2a4e080" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Aug 28 15:58:06 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Sep 01 17:00:40 2026 -0700" }, "message": "Add I422ToAR30Row_RVV for RISC-V Vector\n\nBug: none\nChange-Id: I39f28554b455356c4494c5bea5bdbb04aefff22c\nTAG\u003dagy\nCONV\u003dabcd6ba2-e3a4-49ba-a3fc-3b6b55b83509\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8311933\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "2fcc1272dd3eb27e1363e7e7218ef192d2a4e080", "tree": "ebd686b963abcf53bb21138bf5b072b6d19f7077", "parents": [ "addfba3a7c656e586393c8669ac7650a77937d0e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 13:39:10 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Sep 01 16:07:23 2026 -0700" }, "message": "Convert8To16 takes bits instead of scale.\n- NV16/24 FOURCC and document\n- Rotate take uint8* for ubsan\n\nBug: 537818862\nChange-Id: I2bc7109abaffe2464e031e33c22296c007077d82\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8339427\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "addfba3a7c656e586393c8669ac7650a77937d0e", "tree": "16053916022f1d163208402d8edde59898f74934", "parents": [ "bcb6b7628306366b66d4f0b00d6ff09e11ca16e9" ], "author": { "name": "Nikolay Baklicharov", "email": "thestorm.nik@gmail.com", "time": "Tue Jan 28 15:27:10 2025 +0200" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 16:02:47 2026 -0700" }, "message": "Add CMake option to enable/disable JPEG\n\nBug: 389970330\nChange-Id: I25dc0237651fdac7ef43291da09916b0fbfa93d4\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/6203403\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "bcb6b7628306366b66d4f0b00d6ff09e11ca16e9", "tree": "af9dd3c234d3c16d124472a3e7e346eb74891bb5", "parents": [ "af714f0810d235b93595228d143e1f4e992838cf" ], "author": { "name": "Sida Zhu", "email": "zhusida@bytedance.com", "time": "Tue Sep 01 18:01:49 2026 +0800" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 12:56:28 2026 -0700" }, "message": "convert_from_argb: Add ARGB to NV16 and NV24\n\nAdd matrix and BT.601 wrapper APIs for converting ARGB to NV16 and\nNV24. Reuse the optimized ARGB Y and UV row functions, then merge\nthe planar chroma rows into the interleaved destination plane.\n\nNV16 performs horizontal 2:1 chroma subsampling on every source row.\nNV24 preserves full-resolution 4:4:4 chroma. Both paths support odd\nwidths, negative heights, and the existing matrix constants.\n\nAdd tests that compare scalar and optimized paths at an odd width and\nheight through the matrix API and its BT.601 wrapper.\n\nBug: 537818862\nChange-Id: Iddefc714a800cdec4dd1394ac7a52bf7b51fd350\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8314188\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "af714f0810d235b93595228d143e1f4e992838cf", "tree": "f241812827951332902eec4154f56295656426de", "parents": [ "2f74e7a78486ea6c977b3d09527a2bb2f12d44c9" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Sep 01 11:10:30 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Sep 01 12:21:37 2026 -0700" }, "message": "Convert8To16 use shift to allow scale\u003d65536\n- Add avx512bw, neon 32 bit and RVV versions\n- Adapt SSE2 to psrlw instead of pmulhuw\n\nCPU Before After Improvement\n---------------------------------------------------------------\nGranite Rapids (AVX10) 77 ms 75 ms +2.6% (1.03x)\nEmerald Rapids (AVX512) 75 ms 67 ms +10.7% (1.12x)\nSapphire Rapids (AVX512) 91 ms 85 ms +6.6% (1.07x)\nAMD Venice Zen 6 (AVX512) 30 ms 30 ms 0.0% (1.00x)\nAMD Turin Zen 5 (AVX512) 32 ms 32 ms 0.0% (1.00x)\nAMD Genoa Zen 4 (AVX512) 35 ms 36 ms -2.9% (0.97x)\nSkylake-X (AVX512) 119 ms 119 ms 0.0% (1.00x)\nIce Lake (AVX512) 93 ms 104 ms -11.8% (0.89x)\nAMD Milan Zen 3 (AVX2) 43 ms 44 ms -2.3% (0.98x)\nHaswell (AVX2) 129 ms 138 ms -7.0% (0.93x)\nNVIDIA Grace (SVE2) 42 ms 43 ms -2.4% (0.98x)\nNeoverse-N1 (NEON) 87 ms 87 ms 0.0% (1.00x)\n---------------------------------------------------------------\n\n\nBug: None\nChange-Id: Ia8f310a70c8b1229927fcdf117fe22e131d70ea9\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8330912\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "2f74e7a78486ea6c977b3d09527a2bb2f12d44c9", "tree": "6b25db546a09da8352d66fd195918b9b7277062a", "parents": [ "60102bd795faf855e67a2f026797c16a25b4c42c" ], "author": { "name": "yuanhecai", "email": "yuanhecai@loongson.cn", "time": "Wed Aug 26 16:12:59 2026 +0800" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 31 20:57:42 2026 -0700" }, "message": "loongarch: Fix per-ISA build flags\n\nCompile LSX and LASX sources separately (-mlsx vs -mlasx)\nto avoid emitting LASX instructions in LSX kernels, which\ncrashed on LSX-only CPUs.\n\nChange-Id: I56003cee9bb750cdac8fa19a5c95efb8889ba9e0\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8294723\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "60102bd795faf855e67a2f026797c16a25b4c42c", "tree": "94c89d3673736a202b830e5ce3a0660f8c2b70ff", "parents": [ "2fed9193c94d3701f36188351bd5251854762cb6" ], "author": { "name": "yuanhecai", "email": "yuanhecai@loongson.cn", "time": "Tue Aug 25 19:29:00 2026 +0800" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 31 20:57:34 2026 -0700" }, "message": "loongarch: Fix RGBToY SIMD\n\nAdd missing RGBToYMatrixRow_Any_{LSX,LASX} and kAddY offset fix so\nRAW/RGB24 to YUV works on LoongArch.\n\nChange-Id: I4c990a3705d7f521fa6d0c9e7e01f1e36f81c379\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8292090\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "2fed9193c94d3701f36188351bd5251854762cb6", "tree": "2b361f89a8427515d1ce195f5c5b502437265386", "parents": [ "7ad044836d037345f4e3df077c51df8f4015dc86" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Aug 28 13:20:09 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Aug 28 15:30:12 2026 -0700" }, "message": "ARGBScale and UV use uint8_t for -fsanitize\u003dalignment\n\nTest: libyuv_unittest built/run with -fsanitize\u003dalignment\n\nBug: 553156658\n\nTAG\u003dagy\nCONV\u003d42e6e965-3e33-4fd8-8697-b46f2588e5b2\n\nChange-Id: I1c9a3a520caa1b4681d499e1aa36b98a2bd40ba7\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8308575\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "7ad044836d037345f4e3df077c51df8f4015dc86", "tree": "55b55500fc371eed49af1e9a08a2e16345837922", "parents": [ "8585efd4bde2ab4e58b1d51eb8aba853d5ef459a" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Fri Aug 28 13:29:33 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Aug 28 15:17:28 2026 -0700" }, "message": "Do not use glob in the hdrs list of libyuv library\n\nSome headers in the include/libyuv directory are private headers and\nshould not be visible to the clients of the libyuv library target. List\nthe public headers explicitly in the hdrs list of the libyuv library\ntarget.\n\nIdeally those private headers should be moved to some other directory\nsuch as the source/ directory.\n\nChange-Id: I04b1e209f6891f06c688fcf0bf5d167e82a27818\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8308801\nReviewed-by: Mirko Bonadei \u003cmbonadei@chromium.org\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "8585efd4bde2ab4e58b1d51eb8aba853d5ef459a", "tree": "597509c5c65c77a1cff17149cf0fa4c67be06640", "parents": [ "0c781f87b82a95a3fd68ff51808cc89fb2d70572" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Fri Aug 28 08:41:32 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Aug 28 08:59:01 2026 -0700" }, "message": "Fix clang-tidy warnings\n\n1. source/convert_from_argb.cc should include libyuv/convert.h because\n it calls ARGBToI420Matrix().\n2. Include \u003cstring.h\u003e for memset().\n\nChange-Id: I3f4841fe604639c7357148ef4788fe0415f0b81b\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8255654\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "0c781f87b82a95a3fd68ff51808cc89fb2d70572", "tree": "ff25fb18ef804ba054c8d568c9f2e17200a53f04", "parents": [ "cb6c9d6fd9c74e01a799402ee59c9c04ca561346" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Aug 27 18:36:37 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Aug 28 08:32:19 2026 -0700" }, "message": "[libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros\n\nReduces include/libyuv/basic_types.h to only define LIBYUV_API.\nDirectly includes \u003cstdint.h\u003e and \u003cstddef.h\u003e where needed in public\nheaders.\nReplaces LIBYUV_BOOL, LIBYUV_FALSE, and LIBYUV_TRUE with C++ bool,\ntrue, and false in C++ code (MJpegDecoder, unit tests) and int (0, 1)\nfor C API functions.\nUpdates documentation and unit tests.\n\nTest: ninja -C out/Release libyuv_unittest \u0026\u0026 ./out/Release/libyuv_unittest --gtest_filter\u003d*\nChange-Id: I2d58e872f0f976263bcda546dcc3b1b5f7e53d58\nTAG\u003dagy\nCONV\u003d2730bc56-93ff-48ed-b615-dcde1b834394\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8280662\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "cb6c9d6fd9c74e01a799402ee59c9c04ca561346", "tree": "5812e626758ed6cbc08494025ce0f7cff72933c3", "parents": [ "bcb7507cb4c965132228f6bb4d4eaf1dfa39153f" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Aug 27 16:46:43 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Thu Aug 27 17:42:40 2026 -0700" }, "message": "Remove LIBYUV_UNBIASED_DATA and make unbiased AR30 rounding default\n\nRemove the LIBYUV_UNBIASED_DATA macro and make the unbiased AR30\nrounding bias adjustment (+24 / -24) default across all x86, ARM, and C\nimplementations.\n\nBug: 551985141\nTest: libyuv_unittest --gtest_filter\u003d*AR30*:*AB30*\nChange-Id: I4a9b964ceef1d08580789cbba8c94846053c9d68\nTAG\u003dagy\nCONV\u003d15289919-ad91-40b2-9ed5-30c3117a5ba4\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8305516\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "bcb7507cb4c965132228f6bb4d4eaf1dfa39153f", "tree": "6193ed9bf0281ad212b0ce23a58d231e4ab56c48", "parents": [ "969c96cfb46c0f5bd40038fcd03f8889ed03f583" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Aug 26 16:51:11 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 26 19:06:22 2026 -0700" }, "message": "libyuv.h: Add scale_rgb.h and remove scale_row.h\n\nlibyuv/scale_rgb.h declares an API function, so it is a public header\nand should be included by the umbrella header libyuv.h.\n\nlibyuv/scale_row.h should be an internal header. It should not be\nincluded by the umbrella header libyuv.h.\n\nFixed: 553139990, 553143607\nChange-Id: I5c1a61296a06a96a36c33ec470513ab7bd1f0e66\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8301033\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "969c96cfb46c0f5bd40038fcd03f8889ed03f583", "tree": "aee248466c11242786ec283f37e681257fd4cf4d", "parents": [ "086698434d09537420e2da0775a90b3a6f7b84e4" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Aug 26 16:28:32 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 26 17:45:34 2026 -0700" }, "message": "BlendPlaneRow_AVX512BW and NEON\n\nCPU / Architecture Before (C) After (NEON) Improvement\n----------------------------------------------------------------------\nCortex-A53 (Pixel 2 XL Little) 3248 ms 792 ms 4.10x\nCortex-A73 (Pixel 2 XL Big) 432 ms 392 ms 1.10x\nCortex-A55 (Pixel 7 Little) 780 ms 563 ms 1.39x\nCortex-A78 (Pixel 7 Mid) 254 ms 170 ms 1.49x\nCortex-X1 (Pixel 7 Big) 158 ms 129 ms 1.22x\nCortex-A510 (Galaxy S22 Little) 816 ms 441 ms 1.85x\nCortex-A710 (Galaxy S22 Mid) 270 ms 129 ms 2.09x\nCortex-X2 (Galaxy S22 Big) 116 ms 80 ms 1.45x\nCortex-A510 (Galaxy S23 Little) 723 ms 373 ms 1.94x\nCortex-A715 (Galaxy S23 Mid) 183 ms 119 ms 1.54x\nCortex-X3 (Galaxy S23 Big) 122 ms 72 ms 1.69x\nLumix C1 Pro (PD2509 Little) 246 ms 156 ms 1.58x\nLumix C1 Premium (PD2509 Mid) 211 ms 112 ms 1.88x\nLumix C1 Ultra (PD2509 Big) 82 ms 50 ms 1.64x\nOryon-v3M (OnePlus Mid) 233 ms 150 ms 1.55x\nOryon-v3L (OnePlus Big) 103 ms 85 ms 1.21x\n\nOn Icelake\nFunction (1280x720) C SSSE3 AVX2 AVX-512BW Gain\n----------------------------------------------------------------------\nBlendPlane 901 ms 165 ms 135 ms 115 ms 1.17x\nI420Blend 1398 ms 287 ms 198 ms 187 ms 1.06x\n\n\nBug: 546077674\nChange-Id: I189c44cc757c0e26838a7b6fdb2db1cbe5f96f20\nTAG\u003dagy\nCONV\u003d0f82c25c-616e-4bb3-beeb-981decb0f40c\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8297264\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "086698434d09537420e2da0775a90b3a6f7b84e4", "tree": "740f1f13fdc12c02b3424066430de9d435545e6b", "parents": [ "50031d294e4e921c4a3dac7bcaa2f8f3df83cbd0" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Aug 26 10:53:36 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Aug 26 11:19:33 2026 -0700" }, "message": "Enable LIBYUV_UNBIASED_DATA\n\nLIBYUV_UNBIASED_DATA is a new configuration macro introduced in\ncommit ba68378. It fixes the AR30 rounding bias offset (+24 / -24) for\n10-bit YUV to RGB conversions.\n\nBug: 551985141\nChange-Id: Id724d8cabaee441147d998f77034bc3e31c25a9d\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8298160\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "50031d294e4e921c4a3dac7bcaa2f8f3df83cbd0", "tree": "8a730a2117dc9ca8a1b6abbd14cdb419717310fb", "parents": [ "3793561ddc546dc4dbe492b2efd3a8be976fee35" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Tue Aug 25 18:52:39 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Aug 25 18:53:17 2026 -0700" }, "message": "Fix potential int overflows in ScaleFilterReduce()\n\nChange-Id: I2eb69772f0d65760a87360e46215a6c6d69f250f\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8170700\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "3793561ddc546dc4dbe492b2efd3a8be976fee35", "tree": "8cc0eed27029dd8b657fb631bd449457a0e0150e", "parents": [ "a0fa6329391922faca64955c1a7bf635ab87d833" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 25 14:28:31 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Aug 25 14:37:32 2026 -0700" }, "message": "RAWToRGB24 avx2/avx512 use permq/shufb and avx512vbmi\n\nCPU / Arch Before (Kernel) After (Kernel) Delta\n----------------------------------------------------------------------\nHaswell (x86_64) 263 ms (SSSE3) 263 ms (AVX2) 0.0%\nMilan (Zen 3) 115 ms (SSSE3) 138 ms (AVX2) -20.0%\nSapphRap (x86_64) 173 ms (SSSE3) 178 ms (AVX512VBMI) -2.9%\nGNR (Granite R) 191 ms (SSSE3) 189 ms (AVX512VBMI) +1.0%\nTurin (Zen 5) 69 ms (SSSE3) 55 ms (AVX512VBMI) +20.3%\nIcelake (x86_64) 204 ms (SSSE3) 186 ms (AVX512VBMI) +8.8%\nCascade Lake 237 ms (SSSE3) 229 ms (AVX512BW) +3.4%\nNeoverse (aarch64)* 103 ms (SVE2) 103 ms (SVE2) 0.0%\n\nBug: None\nChange-Id: Ib218632e16b3308a214e9ffcbc745d6c41116c6e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8280536\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "a0fa6329391922faca64955c1a7bf635ab87d833", "tree": "88f83b22b2bc67f3661b4a60d4975d1129911a30", "parents": [ "ae48f8dd618da1bf60dae1e907bc72b6fae04f73" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 24 19:07:15 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 19:41:39 2026 -0700" }, "message": "Add AVX2 row functions for RGB565, ARGB1555, and ARGB4444\n\nOn Icelake:\nWas C\nI420ToARGB1555_Opt (1230 ms)\nI420ToARGB4444_Opt (1195 ms)\nI420ToRGB565_Opt (1141 ms)\n\nNow AVX2\nI420ToARGB1555_Opt (372 ms)\nI420ToARGB4444_Opt (397 ms)\nI420ToRGB565_Opt (347 ms)\nI420ToRGB24Filter_Opt (567 ms)\nI420ToRGB565Dither_Opt (418 ms)\nI420ToARGBFilter_Opt (381 ms)\nI420ToRGBA_Opt (304 ms)\nI420ToBGRA_Opt (296 ms)\nI420ToARGB_Opt (257 ms)\nI420ToABGR_Opt (254 ms)\nI420ToAR30_Opt (215 ms)\nI420ToRGB24_Opt (205 ms)\nI420ToRAW_Opt (193 ms)\n\nBug: None\nChange-Id: I36cf95d29ba85ae63c549fef7f55cb1fe0f95d8e\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8282746\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "ae48f8dd618da1bf60dae1e907bc72b6fae04f73", "tree": "6f8fa10b7083c8ad9179f5c7d88b0ab1092c9fe0", "parents": [ "196d9aa2f158fa86899c03bc6041aa1b8a7b74a8" ], "author": { "name": "Sida Zhu", "email": "zhusida@bytedance.com", "time": "Tue Aug 25 06:13:51 2026 +0800" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 19:28:50 2026 -0700" }, "message": "Fix same-width vertical point upsampling\n\nScalePlane\u0027s same-width vertical fast path used the endpoint-oriented\nFixedDiv1 step for all upsampling. That stepping is appropriate for\nbilinear interpolation, but not for point sampling, where source rows\nshould cover equally sized destination cells.\n\nUse the same centered FixedDiv stepping as the generic point sampler.\nAllow the point path to select the final source row while passing a\nzero interpolation stride so row kernels cannot form a pointer beyond\nit. Add 8-bit and 16-bit point regression coverage and verify that\nbilinear upsampling remains unchanged.\n\nBug: 537818862\nChange-Id: I7bee21b85913b31c146ecf7fe9f5f08608a8a17d\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8264449\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "196d9aa2f158fa86899c03bc6041aa1b8a7b74a8", "tree": "03fdcf7c2bb192aede66b2fd38472207d866bec6", "parents": [ "5689f16923f516ba6eb5b5a3ee11dc90065a3641" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Mon Aug 24 18:10:12 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 19:27:06 2026 -0700" }, "message": "Remove four unused macros in row_win.cc\n\nThe READYUV444, READYUVA444, READYUVA422, and STOREARGB macros are\ndefined but not used.\n\nChange-Id: Ic1174b5b9c7dc8554f362871de73080c32a58537\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8279223\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "5689f16923f516ba6eb5b5a3ee11dc90065a3641", "tree": "18da996cc5aacd2ef8219678de43de99a6f1fd62", "parents": [ "ba6837848836a3635412a67f790c9d4d26d27d3e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 24 16:10:25 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 18:05:48 2026 -0700" }, "message": "Refactor multi-stage SSSE3 scalers into single asm blocks\n\nConsolidate split asm volatile blocks into single blocks across SSSE3\nscaling functions in scale_gcc.cc. This prevents potential register\ncorruption or clobbering by compiler optimizations between disjoint\nasm blocks, and uses named operand constraints for clarity and safety.\n\nList of affected functions in scale_gcc.cc:\n- ScaleRowDown34_SSSE3: merge 2 asm blocks into 1\n- ScaleRowDown34_1_Box_SSSE3: merge 3 asm blocks into 1\n- ScaleRowDown34_0_Box_SSSE3: merge 3 asm blocks into 1\n- ScaleRowDown38_2_Box_SSSE3: merge 2 asm blocks into 1\n- ScaleRowDown38_3_Box_SSSE3: merge 2 asm blocks into 1\n- ScaleARGBFilterCols_SSSE3: merge 2 asm blocks into 1\n\nTest: ninja -C out/Release libyuv_unittest \u0026\u0026 ./out/Release/libyuv_unittest\nTest: ninja -C out/Release_x86 libyuv_unittest \u0026\u0026 ./out/Release_x86/libyuv_unittest\nBug: 489489002\nChange-Id: I900a590db2ef21b9f019a115699d3a270877ed28\nTAG\u003dagy\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8280666\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "ba6837848836a3635412a67f790c9d4d26d27d3e", "tree": "efcfc77d811abba0ee866586dc4d88e96011ee63", "parents": [ "553f01170b72a841aa0aff61acfb1727d635be9c" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 24 11:18:53 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 13:52:04 2026 -0700" }, "message": "Fix off by 32 rounding for I420ToAR30\n\n- x86 SSSE3 / AVX2 / AVX-512: subtract 24 in YUVTORGB_SETUP_AR30\n- ARM NEON64: adjust BB (+24), BG (-24), BR (+24) in YUVTORGB_SETUP_AR30\n- Windows MSVC AVX2 / AVX-512BW: subtract 24 from kYBiasToRgb\n- C reference: adjust Yb in LOAD_YUV_CONSTANTS_AR30\n- Unit tests: add +0.5 rounding to expected 10-bit Y reference\n\nBug: 551985141\nChange-Id: I2bc418edb2d6efb76b4fb1c6bc01205525f4a49c\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8280769\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "553f01170b72a841aa0aff61acfb1727d635be9c", "tree": "bc191264fab07185a87417fd9bbe2e6e5aecf6a4", "parents": [ "72e5a16aee0617cab70e869bfcdffca97a8503fa" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Tue Aug 18 09:30:06 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 24 11:40:53 2026 -0700" }, "message": "Check rotate_any.cc and scale_any.cc for overflows\n\nInspect all the ANY macros.\n\nChange-Id: Icdf382181572b34490e0830d1a0a14286b84faaf\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8266561\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "72e5a16aee0617cab70e869bfcdffca97a8503fa", "tree": "78b889d63d909973e9a579244764e23657b064a1", "parents": [ "44d9bc68f216585cdcfefbe0b59afd7e54f2c550" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Aug 19 15:53:13 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 24 10:43:21 2026 -0700" }, "message": "Remove magjed from OWNERS\n\nChange-Id: Ie4c1c5e25c68653d3d918584938c1ea0f94c84ac\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8269401\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "44d9bc68f216585cdcfefbe0b59afd7e54f2c550", "tree": "be5d76b137be8aa969deee1a13adf0691e38fa8f", "parents": [ "8d7ed8af356a2a2b3feab24c501769705fdae989" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Aug 21 11:41:27 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Fri Aug 21 11:57:41 2026 -0700" }, "message": "STOREAR30 remove initial shift by 4\n\n- reduced shifts to isolate 10 bits\n- permi2w instead of packlwd to combine words (ARG) (GB) into ARGB\n- vpternlogd to combine A,R,G into 1 register\n\nSaphhire Rapids 10000 iterations of 1280x720P:\nConversion Kernel │ Was │ Now │ Speedup\n──────────────────────┼────────────────────────┼────────────────\nI420ToAR30_Opt │ 1675 ms │ 1568 ms │ +7.1%\nH420ToAR30_Opt │ 1632 ms │ 1555 ms │ +5.2%\nI210ToAR30_Opt │ 2459 ms │ 2167 ms │ +13.5%\nP010ToAR30_Opt │ 2054 ms │ 1926 ms │ +6.6%\nP016ToAR30_Opt │ 2043 ms │ 1938 ms │ +5.4%\nTotal Test Suite Time │ 9,866 ms │ 9,155 ms │ +7.8% overall\n\nBug: None\nChange-Id: I7972f98408a65a2bb51c506145e4c0c63824c424\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8259796\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "8d7ed8af356a2a2b3feab24c501769705fdae989", "tree": "37ff41d87e9545b9a75d4ec346a77dc45d32e281", "parents": [ "28ce69c2744a6aafdb58564e7b884aec3f66be5f" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Aug 20 20:14:23 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Aug 20 20:31:22 2026 -0700" }, "message": "Fix undeclared register clobbers in x86 and NEON assembly\n\nList of affected functions:\n- ARGBToAB64Row_SSSE3 (row_gcc.cc): add xmm3 clobber\n- ARGBToAB64Row_AVX2 (row_gcc.cc): add xmm3 clobber\n- ARGBToAB64Row_NEON (row_neon64.cc): add v5, v6, v7 clobbers\n- ARGBToUV444MatrixRow_NEON (row_neon.cc): add q13 clobber\n- ARGBSepiaRow_NEON_DotProd (row_neon64.cc): add v23 clobber\n- I422ToRGB24Row_NEON (row_neon.cc): remove dead d6 mutation\n- I422ToRGB565Row_NEON (row_neon.cc): remove dead d6 mutation\n- MergeAR64Row_NEON (row_neon.cc, row_neon64.cc): add q14, v30 clobbers\n- MergeXR30Row_AVX2 (row_gcc.cc): add xmm6 clobber\n- MergeXR64Row_NEON (row_neon.cc, row_neon64.cc): add q14, v30 clobbers\n- NV12ToRGB24Row_NEON (row_neon.cc): remove dead d6 mutation\n- NV12ToRGB565Row_NEON (row_neon.cc): remove dead d6 mutation\n- NV21ToRGB24Row_NEON (row_neon.cc): remove dead d6 mutation\n- RGBToUV444MatrixRow_NEON (row_neon.cc): add q13 clobber\n- ScaleRowDown2Box_SSSE3 (scale_gcc.cc): add xmm4 clobber\n- ScaleRowDown2Box_AVX2 (scale_gcc.cc): add xmm4 clobber\n- SobelToPlaneRow_SSE2 (row_gcc.cc): remove dead xmm5 mutation\n- UYVYToARGBRow_SSSE3 (row_gcc.cc): add xmm6, xmm7 clobbers\n\nTest: ninja -C out/Release libyuv_unittest \u0026\u0026 ./out/Release/libyuv_unittest\nBug: 489489002\nChange-Id: I0a8794be0423ef36d679a45e276738c2e42d2fb8\nTAG\u003dagy\nCONV\u003d16035e35-dcc9-4b8f-90f7-f17b299bc523\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8258080\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "28ce69c2744a6aafdb58564e7b884aec3f66be5f", "tree": "589390a5b58694f4d8e9f2bcd42c656aec258958", "parents": [ "e808cf543e884168cc5861d60cf61faa43d5e622" ], "author": { "name": "Alex Ovsienko", "email": "ovsienko@google.com", "time": "Wed Aug 19 20:17:47 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 19 20:31:30 2026 -0700" }, "message": "[DEPS] Add CPython CIPD package for hermetic Python toolchain\n\nAdd src/third_party/cpython3 CIPD packages for Linux and host platforms\n(\u0027\\\u0027\u0027infra/3pp/tools/cpython3/${platform}\u0027\\\u0027\u0027 at \u0027\\\u0027\u0027version:3@3.11.9.chromium.38\u0027\\\u0027\u0027).\n\nThis enables hermetic Python execution in Siso builds where Siso configs\ninherited from build/ require the hermetic Python binary at\nsrc/third_party/cpython3/linux-amd64/bin/python3 on remote workers.\n\nBug: chromium:537680330\nChange-Id: I439b2af56dcc5f325ec6f3dbe2837cf550e5c0d2\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8266781\nReviewed-by: Mirko Bonadei \u003cmbonadei@chromium.org\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Alex Ovsienko \u003covsienko@google.com\u003e\n" }, { "commit": "e808cf543e884168cc5861d60cf61faa43d5e622", "tree": "3074585577a53f89fb8039cc8567923767b3c9c5", "parents": [ "fdaa609a4f49d5b4f72c4368bca5a304f9ada677" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 18 19:52:15 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 19 15:52:36 2026 -0700" }, "message": "STOREAR30 macro improvement for I420ToAR30 etc\n\nBug: None\nChange-Id: I163e8da5b223a928df9341f3f8819c56f76ea5e8\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8268434\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "fdaa609a4f49d5b4f72c4368bca5a304f9ada677", "tree": "ebc7f695f322c9bcaa4b49b3d92eb1c6f1c7de9f", "parents": [ "fd64b1b5aba54d18356d1801010e5d3d0a754ff3" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Wed Aug 19 11:41:57 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 19 14:02:35 2026 -0700" }, "message": "OWNERS: List mbonadei after fbarchard and wtc\n\nChange-Id: I05d68f8d9c033595db23c3e20a9f64300ab3048b\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8269632\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "fd64b1b5aba54d18356d1801010e5d3d0a754ff3", "tree": "653017175154d71e0b3447e93f0f86317cfb1168", "parents": [ "50bfd8fc089c96ea0451fd5a10bae35faf0752b1" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 18 19:48:01 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 19 12:52:21 2026 -0700" }, "message": "Fix unit test buffer sizes and skip large allocation on MSan\n\nIn P010ToARGBMatrixFilterOverflow, P210ToARGBMatrixFilterOverflow,\nP010ToAR30MatrixFilterOverflow, and P210ToAR30MatrixFilterOverflow,\nthe tests set src_stride_uv to width (1039) and allocated\nwidth * src_uv_height elements. For odd widths, the interleaved UV\nrow requires (width + 1) \u0026 ~1 elements (1040). Using width for the\nstride and buffer size caused the second row to read past the allocated\nbuffer and access uninitialized memory under MSan.\nFix this by computing src_stride_uv \u003d (width + 1) \u0026 ~1 and sizing the\nallocated buffer to src_stride_uv * src_uv_height.\n\nIn TestI400LargeSize, the test attempts large allocations totaling\nover 10 GB (~2 GB for source and ~8.5 GB for destination). Under\nMemorySanitizer (MSan), large allocations can exceed shadow memory\nvirtual address limits or assert. Skip this test under MSan by checking\n__SANITIZE_MEMORY__ and __has_feature(memory_sanitizer).\n\nTest: libyuv_unittest --gtest_filter\u003d*FilterOverflow*:*I400Large*\nBug: 549112862\nChange-Id: I679b7c67d93822e83f066b1895924589fc7242e7\nTAG\u003dagy\nCONV\u003ddd635180-175b-4e35-b7f0-2e38105d3506\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8269585\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "50bfd8fc089c96ea0451fd5a10bae35faf0752b1", "tree": "1b901686459c957eb57a37dc83d99bac87850e10", "parents": [ "210d11f747013beaf4abc7594c0be265fca4b7bc" ], "author": { "name": "George Steed", "email": "george.steed@arm.com", "time": "Thu Aug 13 18:55:19 2026 +0100" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Wed Aug 19 11:25:07 2026 -0700" }, "message": "AArch64: Avoid INCP in {YUY2,UYVY}ToUVRow_SVE2\n\nThe INCP instructions are particularly slow on some CPUs and in this\ncase can be replaced by a simple ADD instruction, so use that instead.\n\nReduction in time taken relative to the existing SVE2 code for\n{YUY2,UYVY}ToUVRow_SVE2:\n\n Cortex-A510: −12.1%\n Lumex C1-Nano: 0.0%\n Cortex-A720: 0.0%\n Lumex C1-Pro: 0.0%\n Cortex-X4: −20.9%\n Lumex C1-Ultra: −20.3%\n\nBug: 546962730\nChange-Id: Iea3d75f7b70fe8a29f12afdd877ac02d43e49f04\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8252282\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "210d11f747013beaf4abc7594c0be265fca4b7bc", "tree": "328aef893e7246f78c0922a3caa225c6fac6afba", "parents": [ "0f36c7f808fffada1c4fa94e375401f2bd27cc85" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 18 14:34:25 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Aug 18 15:31:51 2026 -0700" }, "message": "READI422 macro improved for avx512 vpermw\n\n - speeds up I420ToARGB etc\n\nGranite Rapids\nNow\nI420ToARGB_Opt (100 ms)\nI420ToAR30_Opt (135 ms)\nWas\nI420ToARGB_Opt (109 ms)\nI420ToAR30_Opt (147 ms)\n\nBug: None\nChange-Id: I70b9356dfbd98f28f07bfe9d8a44f0107435a26f\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8265437\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "0f36c7f808fffada1c4fa94e375401f2bd27cc85", "tree": "a4397f4b1ca97950e8dea795aca2189c33ca9338", "parents": [ "26e56be0f984af3dae4d0c0ab7a0bac8ac20e1b0" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 18 14:02:53 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Aug 18 14:18:47 2026 -0700" }, "message": "STORERGB24 macros for avx512\n\n- improves I420ToRAW performance\n\nI420ToRAW on Skylake\n Was AVX2\n I420ToRAW_Opt (262 ms)\n Now AVX512\n I420ToRAW_Opt (212 ms)\n\nI420ToRAW on Icelake with avx512vbmi\n Was I420ToRAW_Opt (200 ms)\n Now I420ToRAW_Opt (187 ms)\n\nBug: None\nChange-Id: If5b171801ba931557d379696fc128d9b155f7c44\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8267746\nCommit-Queue: Frank Barchard \u003cfbarchard@google.com\u003e\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\n" }, { "commit": "26e56be0f984af3dae4d0c0ab7a0bac8ac20e1b0", "tree": "28fd638719956362b8764e27973158304e4d50cf", "parents": [ "f61a589bb39a9446951c2690a10b3565ca9c1e10" ], "author": { "name": "George Steed", "email": "george.steed@arm.com", "time": "Tue Aug 18 11:57:10 2026 +0100" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Aug 18 11:21:14 2026 -0700" }, "message": "GEMINI.md: Update Arm wording and guidance\n\nUpdate trademarks, document `arm_sve.h` and add guidance to prefer fully\npredicated loop iterations for SVE/SME implementations.\n\nChange-Id: I4039b982ba816193019df62a523fd29f474c3d10\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8256407\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "f61a589bb39a9446951c2690a10b3565ca9c1e10", "tree": "b04a0c8c5961fc5c0f2e81b404871ef96f1d7859", "parents": [ "c8e8b704602d3e67ae14064de079d00dc5b6fd0b" ], "author": { "name": "George Steed", "email": "george.steed@arm.com", "time": "Mon Aug 10 09:45:16 2026 +0100" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Tue Aug 18 10:50:05 2026 -0700" }, "message": "AArch64: Fix {YUY2,UYVY}ToUVRow_SVE2 tail predication\n\nThe tail LD2B predicate previously used the raw remaining width, however\nfor odd widths this is incorrect. We already calculate the correct\nhalved predicate for the UV store part so just compute the load\npredicate from that directly.\n\nBug: 546962730\nChange-Id: I59654208ea48eb5bcc6261a63cb90abae58c1668\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8252280\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "c8e8b704602d3e67ae14064de079d00dc5b6fd0b", "tree": "7bfabc3f9b9f52a8e5c539f3e490b8a7ebe85f4f", "parents": [ "1b7af2e5a912143b789487761c2ba9e8a8622246" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Mon Aug 17 17:12:48 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 17 17:44:57 2026 -0700" }, "message": "Remove Disabled comment: HAS_ARGBTOYMATRIXROW_SME\n\nThe \"Disabled:\" comment for HAS_ARGBTOYMATRIXROW_SME was left behind\nwhen we re-enabled HAS_ARGBTOYMATRIXROW_SME.\n\nBug: 546962730\nChange-Id: Id21fb368a5233bed9f9733d8a54bce3ed0751f47\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8263125\nReviewed-by: George Steed \u003cgeorge.steed@arm.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "1b7af2e5a912143b789487761c2ba9e8a8622246", "tree": "0bac0b6593e7fb63b17d859ccc5ddfca7c9b5042", "parents": [ "d67b51303dae90f3b3d184e42a990e674481ea1e" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 17 13:21:09 2026 -0700" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Aug 17 15:14:53 2026 -0700" }, "message": "HalfWidthRow_16To8_SSSE3 fix 32 bit build pmaddwd constant 2\n\nTest: compile for android_x86 (32 bit)\n\nWas\nsource/row_gcc.cc:5524:7: error: inline assembly requires more registers than available\n 5524 | \"movd %4,%%xmm2 \\n\"\n | ^\n\nBug: b/547388714\nChange-Id: I5aa01516c2fd7e8c37fad72fa044a7e51d7410b8\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8265047\nReviewed-by: richard winterton \u003crrwinterton@gmail.com\u003e\nReviewed-by: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "d67b51303dae90f3b3d184e42a990e674481ea1e", "tree": "0b40bb500d195ce7703f8ea8eebcfc9a58db9853", "parents": [ "87c797b3c29cc6fb233fc329a93aace2942ba2d9" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Mon Aug 17 14:26:37 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 17 14:43:10 2026 -0700" }, "message": "Revert \"Add the ARGBToRGB565Row_SSE2() function back\"\n\nThis reverts commit 87c797b3c29cc6fb233fc329a93aace2942ba2d9.\n\nReason for revert: Only commit 8aeb3a9 needs the workaround\n\nOriginal change\u0027s description:\n\u003e Add the ARGBToRGB565Row_SSE2() function back\n\u003e\n\u003e Add the ARGBToRGB565Row_SSE2() and ARGBToRGB565Row_Any_SSE2() functions\n\u003e back because they hide the unaligned access in ARGBToRGB565Row_C().\n\u003e\n\u003e To reproduce the unalgined access error, run the following command in\n\u003e Google\u0027s internal repository:\n\u003e blaze test --config\u003dasan third_party/libyuv:libyuv_test \\\n\u003e --test_filter\u003dLibYUVConvertTest.I420ToARGBToRGB565_Unaligned\n\u003e\n\u003e Bug: b:547803993\n\u003e Change-Id: I9cc6b643bc007c100dfc092ef3ec814428789219\n\u003e Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8265046\n\u003e Commit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n\u003e Reviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n\nBug: b:547803993\nChange-Id: I904126f032f4ed37c470d8972152a137ca315168\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8258919\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nBot-Commit: rubber-stamper@appspot.gserviceaccount.com \u003crubber-stamper@appspot.gserviceaccount.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" }, { "commit": "87c797b3c29cc6fb233fc329a93aace2942ba2d9", "tree": "785e2b4d0e341523bf346183bb43ba0d56be4d78", "parents": [ "fc8c2359fef95a8300853ab3c092276d657b1b0b" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Mon Aug 17 12:47:07 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 17 13:09:01 2026 -0700" }, "message": "Add the ARGBToRGB565Row_SSE2() function back\n\nAdd the ARGBToRGB565Row_SSE2() and ARGBToRGB565Row_Any_SSE2() functions\nback because they hide the unaligned access in ARGBToRGB565Row_C().\n\nTo reproduce the unalgined access error, run the following command in\nGoogle\u0027s internal repository:\n blaze test --config\u003dasan third_party/libyuv:libyuv_test \\\n --test_filter\u003dLibYUVConvertTest.I420ToARGBToRGB565_Unaligned\n\nBug: b:547803993\nChange-Id: I9cc6b643bc007c100dfc092ef3ec814428789219\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8265046\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\n" }, { "commit": "fc8c2359fef95a8300853ab3c092276d657b1b0b", "tree": "0b40bb500d195ce7703f8ea8eebcfc9a58db9853", "parents": [ "7badb217b95311113d01db92a34f6d2e8d79f031" ], "author": { "name": "Wan-Teh Chang", "email": "wtc@google.com", "time": "Fri Aug 14 15:10:35 2026 -0700" }, "committer": { "name": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "email": "libyuv-scoped@luci-project-accounts.iam.gserviceaccount.com", "time": "Mon Aug 17 13:05:33 2026 -0700" }, "message": "SAROW() should memset src_temp for msan\n\nIt is the temporary input buffer, not the temporary output buffer, that\nneeds to be zero-initialized for msan.\n\nThis mistake may have been introduced because dst_temp was declared\nbefore src_temp. So swap their declarations.\n\nChange-Id: I74691afe51a7d84187fc0decbc83f2c970cf52b7\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8261587\nReviewed-by: Frank Barchard \u003cfbarchard@google.com\u003e\nCommit-Queue: Wan-Teh Chang \u003cwtc@google.com\u003e\n" } ], "next": "7badb217b95311113d01db92a34f6d2e8d79f031" }