)]}'
{
  "commit": "fa16ddbb9fbee36d67d8496fc9389ea95930b238",
  "tree": "6124fb32d4222bc4d75bb4e4019ba6774643138d",
  "parents": [
    "616bee5420b62a7be09fda0252034e8be85f91b0"
  ],
  "author": {
    "name": "Frank Barchard",
    "email": "fbarchard@google.com",
    "time": "Tue Jul 02 10:39:04 2024 -0700"
  },
  "committer": {
    "name": "Frank Barchard",
    "email": "fbarchard@google.com",
    "time": "Tue Jul 02 18:10:56 2024 +0000"
  },
  "message": "cpuid show vector length on ARM and RISCV\n\n- additional asm volatile changes from github\n- rotate mips remove C function - moved to common\n\nRun on Samsung S22\n[ RUN      ] LibYUVBaseTest.TestCpuHas\nKernel Version 5.10\nHas Arm 0x2\nHas Neon 0x4\nHas Neon DotProd 0x10\nHas Neon I8MM 0x20\nHas SVE 0x40\nHas SVE2 0x80\nHas SME 0x0\nSVE vector length: 16 bytes\n[       OK ] LibYUVBaseTest.TestCpuHas (0 ms)\n[ RUN      ] LibYUVBaseTest.TestCompilerMacros\n__ATOMIC_RELAXED 0\n__cplusplus 201703\n__clang_major__ 17\n__clang_minor__ 0\n__GNUC__ 4\n__GNUC_MINOR__ 2\n__aarch64__ 1\n__clang__ 1\n__llvm__ 1\n__pic__ 2\nINT_TYPES_DEFINED\n__has_feature\n\nRun on RISCV qemu emulating SiFive X280:\n[ RUN      ] LibYUVBaseTest.TestCpuHas\nKernel Version 6.6\nHas RISCV 0x10000000\nHas RVV 0x20000000\nRVV vector length: 64 bytes\n[       OK ] LibYUVBaseTest.TestCpuHas (4 ms)\n[ RUN      ] LibYUVBaseTest.TestCompilerMacros\n__ATOMIC_RELAXED 0\n__cplusplus 202002\n__clang_major__ 9999\n__clang_minor__ 0\n__GNUC__ 4\n__GNUC_MINOR__ 2\n__riscv 1\n__riscv_vector 1\n__riscv_v_intrinsic 12000\n__riscv_zve64x 1000000\n__clang__ 1\n__llvm__ 1\n__pic__ 2\nINT_TYPES_DEFINED\n__has_feature\n\nBug: b/42280943\nChange-Id: I53cf0450be4965a28942e113e4c77295ace70999\nReviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5672088\nReviewed-by: David Gao \u003cdavidgao@google.com\u003e\n",
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