| // Code generated from _gen/*Ops.go; DO NOT EDIT. |
| |
| package ssa |
| |
| import ( |
| "cmd/internal/obj" |
| "cmd/internal/obj/arm" |
| "cmd/internal/obj/arm64" |
| "cmd/internal/obj/loong64" |
| "cmd/internal/obj/mips" |
| "cmd/internal/obj/ppc64" |
| "cmd/internal/obj/riscv" |
| "cmd/internal/obj/s390x" |
| "cmd/internal/obj/wasm" |
| "cmd/internal/obj/x86" |
| ) |
| |
| const ( |
| BlockInvalid BlockKind = iota |
| |
| Block386EQ |
| Block386NE |
| Block386LT |
| Block386LE |
| Block386GT |
| Block386GE |
| Block386OS |
| Block386OC |
| Block386ULT |
| Block386ULE |
| Block386UGT |
| Block386UGE |
| Block386EQF |
| Block386NEF |
| Block386ORD |
| Block386NAN |
| |
| BlockAMD64EQ |
| BlockAMD64NE |
| BlockAMD64LT |
| BlockAMD64LE |
| BlockAMD64GT |
| BlockAMD64GE |
| BlockAMD64OS |
| BlockAMD64OC |
| BlockAMD64ULT |
| BlockAMD64ULE |
| BlockAMD64UGT |
| BlockAMD64UGE |
| BlockAMD64EQF |
| BlockAMD64NEF |
| BlockAMD64ORD |
| BlockAMD64NAN |
| BlockAMD64JUMPTABLE |
| |
| BlockARMEQ |
| BlockARMNE |
| BlockARMLT |
| BlockARMLE |
| BlockARMGT |
| BlockARMGE |
| BlockARMULT |
| BlockARMULE |
| BlockARMUGT |
| BlockARMUGE |
| BlockARMLTnoov |
| BlockARMLEnoov |
| BlockARMGTnoov |
| BlockARMGEnoov |
| |
| BlockARM64EQ |
| BlockARM64NE |
| BlockARM64LT |
| BlockARM64LE |
| BlockARM64GT |
| BlockARM64GE |
| BlockARM64ULT |
| BlockARM64ULE |
| BlockARM64UGT |
| BlockARM64UGE |
| BlockARM64Z |
| BlockARM64NZ |
| BlockARM64ZW |
| BlockARM64NZW |
| BlockARM64TBZ |
| BlockARM64TBNZ |
| BlockARM64FLT |
| BlockARM64FLE |
| BlockARM64FGT |
| BlockARM64FGE |
| BlockARM64LTnoov |
| BlockARM64LEnoov |
| BlockARM64GTnoov |
| BlockARM64GEnoov |
| BlockARM64JUMPTABLE |
| |
| BlockLOONG64EQ |
| BlockLOONG64NE |
| BlockLOONG64LTZ |
| BlockLOONG64LEZ |
| BlockLOONG64GTZ |
| BlockLOONG64GEZ |
| BlockLOONG64FPT |
| BlockLOONG64FPF |
| |
| BlockMIPSEQ |
| BlockMIPSNE |
| BlockMIPSLTZ |
| BlockMIPSLEZ |
| BlockMIPSGTZ |
| BlockMIPSGEZ |
| BlockMIPSFPT |
| BlockMIPSFPF |
| |
| BlockMIPS64EQ |
| BlockMIPS64NE |
| BlockMIPS64LTZ |
| BlockMIPS64LEZ |
| BlockMIPS64GTZ |
| BlockMIPS64GEZ |
| BlockMIPS64FPT |
| BlockMIPS64FPF |
| |
| BlockPPC64EQ |
| BlockPPC64NE |
| BlockPPC64LT |
| BlockPPC64LE |
| BlockPPC64GT |
| BlockPPC64GE |
| BlockPPC64FLT |
| BlockPPC64FLE |
| BlockPPC64FGT |
| BlockPPC64FGE |
| |
| BlockRISCV64BEQ |
| BlockRISCV64BNE |
| BlockRISCV64BLT |
| BlockRISCV64BGE |
| BlockRISCV64BLTU |
| BlockRISCV64BGEU |
| BlockRISCV64BEQZ |
| BlockRISCV64BNEZ |
| BlockRISCV64BLEZ |
| BlockRISCV64BGEZ |
| BlockRISCV64BLTZ |
| BlockRISCV64BGTZ |
| |
| BlockS390XBRC |
| BlockS390XCRJ |
| BlockS390XCGRJ |
| BlockS390XCLRJ |
| BlockS390XCLGRJ |
| BlockS390XCIJ |
| BlockS390XCGIJ |
| BlockS390XCLIJ |
| BlockS390XCLGIJ |
| |
| BlockPlain |
| BlockIf |
| BlockDefer |
| BlockRet |
| BlockRetJmp |
| BlockExit |
| BlockJumpTable |
| BlockFirst |
| ) |
| |
| var blockString = [...]string{ |
| BlockInvalid: "BlockInvalid", |
| |
| Block386EQ: "EQ", |
| Block386NE: "NE", |
| Block386LT: "LT", |
| Block386LE: "LE", |
| Block386GT: "GT", |
| Block386GE: "GE", |
| Block386OS: "OS", |
| Block386OC: "OC", |
| Block386ULT: "ULT", |
| Block386ULE: "ULE", |
| Block386UGT: "UGT", |
| Block386UGE: "UGE", |
| Block386EQF: "EQF", |
| Block386NEF: "NEF", |
| Block386ORD: "ORD", |
| Block386NAN: "NAN", |
| |
| BlockAMD64EQ: "EQ", |
| BlockAMD64NE: "NE", |
| BlockAMD64LT: "LT", |
| BlockAMD64LE: "LE", |
| BlockAMD64GT: "GT", |
| BlockAMD64GE: "GE", |
| BlockAMD64OS: "OS", |
| BlockAMD64OC: "OC", |
| BlockAMD64ULT: "ULT", |
| BlockAMD64ULE: "ULE", |
| BlockAMD64UGT: "UGT", |
| BlockAMD64UGE: "UGE", |
| BlockAMD64EQF: "EQF", |
| BlockAMD64NEF: "NEF", |
| BlockAMD64ORD: "ORD", |
| BlockAMD64NAN: "NAN", |
| BlockAMD64JUMPTABLE: "JUMPTABLE", |
| |
| BlockARMEQ: "EQ", |
| BlockARMNE: "NE", |
| BlockARMLT: "LT", |
| BlockARMLE: "LE", |
| BlockARMGT: "GT", |
| BlockARMGE: "GE", |
| BlockARMULT: "ULT", |
| BlockARMULE: "ULE", |
| BlockARMUGT: "UGT", |
| BlockARMUGE: "UGE", |
| BlockARMLTnoov: "LTnoov", |
| BlockARMLEnoov: "LEnoov", |
| BlockARMGTnoov: "GTnoov", |
| BlockARMGEnoov: "GEnoov", |
| |
| BlockARM64EQ: "EQ", |
| BlockARM64NE: "NE", |
| BlockARM64LT: "LT", |
| BlockARM64LE: "LE", |
| BlockARM64GT: "GT", |
| BlockARM64GE: "GE", |
| BlockARM64ULT: "ULT", |
| BlockARM64ULE: "ULE", |
| BlockARM64UGT: "UGT", |
| BlockARM64UGE: "UGE", |
| BlockARM64Z: "Z", |
| BlockARM64NZ: "NZ", |
| BlockARM64ZW: "ZW", |
| BlockARM64NZW: "NZW", |
| BlockARM64TBZ: "TBZ", |
| BlockARM64TBNZ: "TBNZ", |
| BlockARM64FLT: "FLT", |
| BlockARM64FLE: "FLE", |
| BlockARM64FGT: "FGT", |
| BlockARM64FGE: "FGE", |
| BlockARM64LTnoov: "LTnoov", |
| BlockARM64LEnoov: "LEnoov", |
| BlockARM64GTnoov: "GTnoov", |
| BlockARM64GEnoov: "GEnoov", |
| BlockARM64JUMPTABLE: "JUMPTABLE", |
| |
| BlockLOONG64EQ: "EQ", |
| BlockLOONG64NE: "NE", |
| BlockLOONG64LTZ: "LTZ", |
| BlockLOONG64LEZ: "LEZ", |
| BlockLOONG64GTZ: "GTZ", |
| BlockLOONG64GEZ: "GEZ", |
| BlockLOONG64FPT: "FPT", |
| BlockLOONG64FPF: "FPF", |
| |
| BlockMIPSEQ: "EQ", |
| BlockMIPSNE: "NE", |
| BlockMIPSLTZ: "LTZ", |
| BlockMIPSLEZ: "LEZ", |
| BlockMIPSGTZ: "GTZ", |
| BlockMIPSGEZ: "GEZ", |
| BlockMIPSFPT: "FPT", |
| BlockMIPSFPF: "FPF", |
| |
| BlockMIPS64EQ: "EQ", |
| BlockMIPS64NE: "NE", |
| BlockMIPS64LTZ: "LTZ", |
| BlockMIPS64LEZ: "LEZ", |
| BlockMIPS64GTZ: "GTZ", |
| BlockMIPS64GEZ: "GEZ", |
| BlockMIPS64FPT: "FPT", |
| BlockMIPS64FPF: "FPF", |
| |
| BlockPPC64EQ: "EQ", |
| BlockPPC64NE: "NE", |
| BlockPPC64LT: "LT", |
| BlockPPC64LE: "LE", |
| BlockPPC64GT: "GT", |
| BlockPPC64GE: "GE", |
| BlockPPC64FLT: "FLT", |
| BlockPPC64FLE: "FLE", |
| BlockPPC64FGT: "FGT", |
| BlockPPC64FGE: "FGE", |
| |
| BlockRISCV64BEQ: "BEQ", |
| BlockRISCV64BNE: "BNE", |
| BlockRISCV64BLT: "BLT", |
| BlockRISCV64BGE: "BGE", |
| BlockRISCV64BLTU: "BLTU", |
| BlockRISCV64BGEU: "BGEU", |
| BlockRISCV64BEQZ: "BEQZ", |
| BlockRISCV64BNEZ: "BNEZ", |
| BlockRISCV64BLEZ: "BLEZ", |
| BlockRISCV64BGEZ: "BGEZ", |
| BlockRISCV64BLTZ: "BLTZ", |
| BlockRISCV64BGTZ: "BGTZ", |
| |
| BlockS390XBRC: "BRC", |
| BlockS390XCRJ: "CRJ", |
| BlockS390XCGRJ: "CGRJ", |
| BlockS390XCLRJ: "CLRJ", |
| BlockS390XCLGRJ: "CLGRJ", |
| BlockS390XCIJ: "CIJ", |
| BlockS390XCGIJ: "CGIJ", |
| BlockS390XCLIJ: "CLIJ", |
| BlockS390XCLGIJ: "CLGIJ", |
| |
| BlockPlain: "Plain", |
| BlockIf: "If", |
| BlockDefer: "Defer", |
| BlockRet: "Ret", |
| BlockRetJmp: "RetJmp", |
| BlockExit: "Exit", |
| BlockJumpTable: "JumpTable", |
| BlockFirst: "First", |
| } |
| |
| func (k BlockKind) String() string { return blockString[k] } |
| func (k BlockKind) AuxIntType() string { |
| switch k { |
| case BlockARM64TBZ: |
| return "int64" |
| case BlockARM64TBNZ: |
| return "int64" |
| case BlockS390XCIJ: |
| return "int8" |
| case BlockS390XCGIJ: |
| return "int8" |
| case BlockS390XCLIJ: |
| return "uint8" |
| case BlockS390XCLGIJ: |
| return "uint8" |
| } |
| return "" |
| } |
| |
| const ( |
| OpInvalid Op = iota |
| |
| Op386ADDSS |
| Op386ADDSD |
| Op386SUBSS |
| Op386SUBSD |
| Op386MULSS |
| Op386MULSD |
| Op386DIVSS |
| Op386DIVSD |
| Op386MOVSSload |
| Op386MOVSDload |
| Op386MOVSSconst |
| Op386MOVSDconst |
| Op386MOVSSloadidx1 |
| Op386MOVSSloadidx4 |
| Op386MOVSDloadidx1 |
| Op386MOVSDloadidx8 |
| Op386MOVSSstore |
| Op386MOVSDstore |
| Op386MOVSSstoreidx1 |
| Op386MOVSSstoreidx4 |
| Op386MOVSDstoreidx1 |
| Op386MOVSDstoreidx8 |
| Op386ADDSSload |
| Op386ADDSDload |
| Op386SUBSSload |
| Op386SUBSDload |
| Op386MULSSload |
| Op386MULSDload |
| Op386DIVSSload |
| Op386DIVSDload |
| Op386ADDL |
| Op386ADDLconst |
| Op386ADDLcarry |
| Op386ADDLconstcarry |
| Op386ADCL |
| Op386ADCLconst |
| Op386SUBL |
| Op386SUBLconst |
| Op386SUBLcarry |
| Op386SUBLconstcarry |
| Op386SBBL |
| Op386SBBLconst |
| Op386MULL |
| Op386MULLconst |
| Op386MULLU |
| Op386HMULL |
| Op386HMULLU |
| Op386MULLQU |
| Op386AVGLU |
| Op386DIVL |
| Op386DIVW |
| Op386DIVLU |
| Op386DIVWU |
| Op386MODL |
| Op386MODW |
| Op386MODLU |
| Op386MODWU |
| Op386ANDL |
| Op386ANDLconst |
| Op386ORL |
| Op386ORLconst |
| Op386XORL |
| Op386XORLconst |
| Op386CMPL |
| Op386CMPW |
| Op386CMPB |
| Op386CMPLconst |
| Op386CMPWconst |
| Op386CMPBconst |
| Op386CMPLload |
| Op386CMPWload |
| Op386CMPBload |
| Op386CMPLconstload |
| Op386CMPWconstload |
| Op386CMPBconstload |
| Op386UCOMISS |
| Op386UCOMISD |
| Op386TESTL |
| Op386TESTW |
| Op386TESTB |
| Op386TESTLconst |
| Op386TESTWconst |
| Op386TESTBconst |
| Op386SHLL |
| Op386SHLLconst |
| Op386SHRL |
| Op386SHRW |
| Op386SHRB |
| Op386SHRLconst |
| Op386SHRWconst |
| Op386SHRBconst |
| Op386SARL |
| Op386SARW |
| Op386SARB |
| Op386SARLconst |
| Op386SARWconst |
| Op386SARBconst |
| Op386ROLL |
| Op386ROLW |
| Op386ROLB |
| Op386ROLLconst |
| Op386ROLWconst |
| Op386ROLBconst |
| Op386ADDLload |
| Op386SUBLload |
| Op386MULLload |
| Op386ANDLload |
| Op386ORLload |
| Op386XORLload |
| Op386ADDLloadidx4 |
| Op386SUBLloadidx4 |
| Op386MULLloadidx4 |
| Op386ANDLloadidx4 |
| Op386ORLloadidx4 |
| Op386XORLloadidx4 |
| Op386NEGL |
| Op386NOTL |
| Op386BSFL |
| Op386BSFW |
| Op386BSRL |
| Op386BSRW |
| Op386BSWAPL |
| Op386SQRTSD |
| Op386SQRTSS |
| Op386SBBLcarrymask |
| Op386SETEQ |
| Op386SETNE |
| Op386SETL |
| Op386SETLE |
| Op386SETG |
| Op386SETGE |
| Op386SETB |
| Op386SETBE |
| Op386SETA |
| Op386SETAE |
| Op386SETO |
| Op386SETEQF |
| Op386SETNEF |
| Op386SETORD |
| Op386SETNAN |
| Op386SETGF |
| Op386SETGEF |
| Op386MOVBLSX |
| Op386MOVBLZX |
| Op386MOVWLSX |
| Op386MOVWLZX |
| Op386MOVLconst |
| Op386CVTTSD2SL |
| Op386CVTTSS2SL |
| Op386CVTSL2SS |
| Op386CVTSL2SD |
| Op386CVTSD2SS |
| Op386CVTSS2SD |
| Op386PXOR |
| Op386LEAL |
| Op386LEAL1 |
| Op386LEAL2 |
| Op386LEAL4 |
| Op386LEAL8 |
| Op386MOVBload |
| Op386MOVBLSXload |
| Op386MOVWload |
| Op386MOVWLSXload |
| Op386MOVLload |
| Op386MOVBstore |
| Op386MOVWstore |
| Op386MOVLstore |
| Op386ADDLmodify |
| Op386SUBLmodify |
| Op386ANDLmodify |
| Op386ORLmodify |
| Op386XORLmodify |
| Op386ADDLmodifyidx4 |
| Op386SUBLmodifyidx4 |
| Op386ANDLmodifyidx4 |
| Op386ORLmodifyidx4 |
| Op386XORLmodifyidx4 |
| Op386ADDLconstmodify |
| Op386ANDLconstmodify |
| Op386ORLconstmodify |
| Op386XORLconstmodify |
| Op386ADDLconstmodifyidx4 |
| Op386ANDLconstmodifyidx4 |
| Op386ORLconstmodifyidx4 |
| Op386XORLconstmodifyidx4 |
| Op386MOVBloadidx1 |
| Op386MOVWloadidx1 |
| Op386MOVWloadidx2 |
| Op386MOVLloadidx1 |
| Op386MOVLloadidx4 |
| Op386MOVBstoreidx1 |
| Op386MOVWstoreidx1 |
| Op386MOVWstoreidx2 |
| Op386MOVLstoreidx1 |
| Op386MOVLstoreidx4 |
| Op386MOVBstoreconst |
| Op386MOVWstoreconst |
| Op386MOVLstoreconst |
| Op386MOVBstoreconstidx1 |
| Op386MOVWstoreconstidx1 |
| Op386MOVWstoreconstidx2 |
| Op386MOVLstoreconstidx1 |
| Op386MOVLstoreconstidx4 |
| Op386DUFFZERO |
| Op386REPSTOSL |
| Op386CALLstatic |
| Op386CALLtail |
| Op386CALLclosure |
| Op386CALLinter |
| Op386DUFFCOPY |
| Op386REPMOVSL |
| Op386InvertFlags |
| Op386LoweredGetG |
| Op386LoweredGetClosurePtr |
| Op386LoweredGetCallerPC |
| Op386LoweredGetCallerSP |
| Op386LoweredNilCheck |
| Op386LoweredWB |
| Op386LoweredPanicBoundsA |
| Op386LoweredPanicBoundsB |
| Op386LoweredPanicBoundsC |
| Op386LoweredPanicExtendA |
| Op386LoweredPanicExtendB |
| Op386LoweredPanicExtendC |
| Op386FlagEQ |
| Op386FlagLT_ULT |
| Op386FlagLT_UGT |
| Op386FlagGT_UGT |
| Op386FlagGT_ULT |
| Op386MOVSSconst1 |
| Op386MOVSDconst1 |
| Op386MOVSSconst2 |
| Op386MOVSDconst2 |
| |
| OpAMD64ADDSS |
| OpAMD64ADDSD |
| OpAMD64SUBSS |
| OpAMD64SUBSD |
| OpAMD64MULSS |
| OpAMD64MULSD |
| OpAMD64DIVSS |
| OpAMD64DIVSD |
| OpAMD64MOVSSload |
| OpAMD64MOVSDload |
| OpAMD64MOVSSconst |
| OpAMD64MOVSDconst |
| OpAMD64MOVSSloadidx1 |
| OpAMD64MOVSSloadidx4 |
| OpAMD64MOVSDloadidx1 |
| OpAMD64MOVSDloadidx8 |
| OpAMD64MOVSSstore |
| OpAMD64MOVSDstore |
| OpAMD64MOVSSstoreidx1 |
| OpAMD64MOVSSstoreidx4 |
| OpAMD64MOVSDstoreidx1 |
| OpAMD64MOVSDstoreidx8 |
| OpAMD64ADDSSload |
| OpAMD64ADDSDload |
| OpAMD64SUBSSload |
| OpAMD64SUBSDload |
| OpAMD64MULSSload |
| OpAMD64MULSDload |
| OpAMD64DIVSSload |
| OpAMD64DIVSDload |
| OpAMD64ADDSSloadidx1 |
| OpAMD64ADDSSloadidx4 |
| OpAMD64ADDSDloadidx1 |
| OpAMD64ADDSDloadidx8 |
| OpAMD64SUBSSloadidx1 |
| OpAMD64SUBSSloadidx4 |
| OpAMD64SUBSDloadidx1 |
| OpAMD64SUBSDloadidx8 |
| OpAMD64MULSSloadidx1 |
| OpAMD64MULSSloadidx4 |
| OpAMD64MULSDloadidx1 |
| OpAMD64MULSDloadidx8 |
| OpAMD64DIVSSloadidx1 |
| OpAMD64DIVSSloadidx4 |
| OpAMD64DIVSDloadidx1 |
| OpAMD64DIVSDloadidx8 |
| OpAMD64ADDQ |
| OpAMD64ADDL |
| OpAMD64ADDQconst |
| OpAMD64ADDLconst |
| OpAMD64ADDQconstmodify |
| OpAMD64ADDLconstmodify |
| OpAMD64SUBQ |
| OpAMD64SUBL |
| OpAMD64SUBQconst |
| OpAMD64SUBLconst |
| OpAMD64MULQ |
| OpAMD64MULL |
| OpAMD64MULQconst |
| OpAMD64MULLconst |
| OpAMD64MULLU |
| OpAMD64MULQU |
| OpAMD64HMULQ |
| OpAMD64HMULL |
| OpAMD64HMULQU |
| OpAMD64HMULLU |
| OpAMD64AVGQU |
| OpAMD64DIVQ |
| OpAMD64DIVL |
| OpAMD64DIVW |
| OpAMD64DIVQU |
| OpAMD64DIVLU |
| OpAMD64DIVWU |
| OpAMD64NEGLflags |
| OpAMD64ADDQcarry |
| OpAMD64ADCQ |
| OpAMD64ADDQconstcarry |
| OpAMD64ADCQconst |
| OpAMD64SUBQborrow |
| OpAMD64SBBQ |
| OpAMD64SUBQconstborrow |
| OpAMD64SBBQconst |
| OpAMD64MULQU2 |
| OpAMD64DIVQU2 |
| OpAMD64ANDQ |
| OpAMD64ANDL |
| OpAMD64ANDQconst |
| OpAMD64ANDLconst |
| OpAMD64ANDQconstmodify |
| OpAMD64ANDLconstmodify |
| OpAMD64ORQ |
| OpAMD64ORL |
| OpAMD64ORQconst |
| OpAMD64ORLconst |
| OpAMD64ORQconstmodify |
| OpAMD64ORLconstmodify |
| OpAMD64XORQ |
| OpAMD64XORL |
| OpAMD64XORQconst |
| OpAMD64XORLconst |
| OpAMD64XORQconstmodify |
| OpAMD64XORLconstmodify |
| OpAMD64CMPQ |
| OpAMD64CMPL |
| OpAMD64CMPW |
| OpAMD64CMPB |
| OpAMD64CMPQconst |
| OpAMD64CMPLconst |
| OpAMD64CMPWconst |
| OpAMD64CMPBconst |
| OpAMD64CMPQload |
| OpAMD64CMPLload |
| OpAMD64CMPWload |
| OpAMD64CMPBload |
| OpAMD64CMPQconstload |
| OpAMD64CMPLconstload |
| OpAMD64CMPWconstload |
| OpAMD64CMPBconstload |
| OpAMD64CMPQloadidx8 |
| OpAMD64CMPQloadidx1 |
| OpAMD64CMPLloadidx4 |
| OpAMD64CMPLloadidx1 |
| OpAMD64CMPWloadidx2 |
| OpAMD64CMPWloadidx1 |
| OpAMD64CMPBloadidx1 |
| OpAMD64CMPQconstloadidx8 |
| OpAMD64CMPQconstloadidx1 |
| OpAMD64CMPLconstloadidx4 |
| OpAMD64CMPLconstloadidx1 |
| OpAMD64CMPWconstloadidx2 |
| OpAMD64CMPWconstloadidx1 |
| OpAMD64CMPBconstloadidx1 |
| OpAMD64UCOMISS |
| OpAMD64UCOMISD |
| OpAMD64BTL |
| OpAMD64BTQ |
| OpAMD64BTCL |
| OpAMD64BTCQ |
| OpAMD64BTRL |
| OpAMD64BTRQ |
| OpAMD64BTSL |
| OpAMD64BTSQ |
| OpAMD64BTLconst |
| OpAMD64BTQconst |
| OpAMD64BTCLconst |
| OpAMD64BTCQconst |
| OpAMD64BTRLconst |
| OpAMD64BTRQconst |
| OpAMD64BTSLconst |
| OpAMD64BTSQconst |
| OpAMD64TESTQ |
| OpAMD64TESTL |
| OpAMD64TESTW |
| OpAMD64TESTB |
| OpAMD64TESTQconst |
| OpAMD64TESTLconst |
| OpAMD64TESTWconst |
| OpAMD64TESTBconst |
| OpAMD64SHLQ |
| OpAMD64SHLL |
| OpAMD64SHLQconst |
| OpAMD64SHLLconst |
| OpAMD64SHRQ |
| OpAMD64SHRL |
| OpAMD64SHRW |
| OpAMD64SHRB |
| OpAMD64SHRQconst |
| OpAMD64SHRLconst |
| OpAMD64SHRWconst |
| OpAMD64SHRBconst |
| OpAMD64SARQ |
| OpAMD64SARL |
| OpAMD64SARW |
| OpAMD64SARB |
| OpAMD64SARQconst |
| OpAMD64SARLconst |
| OpAMD64SARWconst |
| OpAMD64SARBconst |
| OpAMD64SHRDQ |
| OpAMD64SHLDQ |
| OpAMD64ROLQ |
| OpAMD64ROLL |
| OpAMD64ROLW |
| OpAMD64ROLB |
| OpAMD64RORQ |
| OpAMD64RORL |
| OpAMD64RORW |
| OpAMD64RORB |
| OpAMD64ROLQconst |
| OpAMD64ROLLconst |
| OpAMD64ROLWconst |
| OpAMD64ROLBconst |
| OpAMD64ADDLload |
| OpAMD64ADDQload |
| OpAMD64SUBQload |
| OpAMD64SUBLload |
| OpAMD64ANDLload |
| OpAMD64ANDQload |
| OpAMD64ORQload |
| OpAMD64ORLload |
| OpAMD64XORQload |
| OpAMD64XORLload |
| OpAMD64ADDLloadidx1 |
| OpAMD64ADDLloadidx4 |
| OpAMD64ADDLloadidx8 |
| OpAMD64ADDQloadidx1 |
| OpAMD64ADDQloadidx8 |
| OpAMD64SUBLloadidx1 |
| OpAMD64SUBLloadidx4 |
| OpAMD64SUBLloadidx8 |
| OpAMD64SUBQloadidx1 |
| OpAMD64SUBQloadidx8 |
| OpAMD64ANDLloadidx1 |
| OpAMD64ANDLloadidx4 |
| OpAMD64ANDLloadidx8 |
| OpAMD64ANDQloadidx1 |
| OpAMD64ANDQloadidx8 |
| OpAMD64ORLloadidx1 |
| OpAMD64ORLloadidx4 |
| OpAMD64ORLloadidx8 |
| OpAMD64ORQloadidx1 |
| OpAMD64ORQloadidx8 |
| OpAMD64XORLloadidx1 |
| OpAMD64XORLloadidx4 |
| OpAMD64XORLloadidx8 |
| OpAMD64XORQloadidx1 |
| OpAMD64XORQloadidx8 |
| OpAMD64ADDQmodify |
| OpAMD64SUBQmodify |
| OpAMD64ANDQmodify |
| OpAMD64ORQmodify |
| OpAMD64XORQmodify |
| OpAMD64ADDLmodify |
| OpAMD64SUBLmodify |
| OpAMD64ANDLmodify |
| OpAMD64ORLmodify |
| OpAMD64XORLmodify |
| OpAMD64ADDQmodifyidx1 |
| OpAMD64ADDQmodifyidx8 |
| OpAMD64SUBQmodifyidx1 |
| OpAMD64SUBQmodifyidx8 |
| OpAMD64ANDQmodifyidx1 |
| OpAMD64ANDQmodifyidx8 |
| OpAMD64ORQmodifyidx1 |
| OpAMD64ORQmodifyidx8 |
| OpAMD64XORQmodifyidx1 |
| OpAMD64XORQmodifyidx8 |
| OpAMD64ADDLmodifyidx1 |
| OpAMD64ADDLmodifyidx4 |
| OpAMD64ADDLmodifyidx8 |
| OpAMD64SUBLmodifyidx1 |
| OpAMD64SUBLmodifyidx4 |
| OpAMD64SUBLmodifyidx8 |
| OpAMD64ANDLmodifyidx1 |
| OpAMD64ANDLmodifyidx4 |
| OpAMD64ANDLmodifyidx8 |
| OpAMD64ORLmodifyidx1 |
| OpAMD64ORLmodifyidx4 |
| OpAMD64ORLmodifyidx8 |
| OpAMD64XORLmodifyidx1 |
| OpAMD64XORLmodifyidx4 |
| OpAMD64XORLmodifyidx8 |
| OpAMD64ADDQconstmodifyidx1 |
| OpAMD64ADDQconstmodifyidx8 |
| OpAMD64ANDQconstmodifyidx1 |
| OpAMD64ANDQconstmodifyidx8 |
| OpAMD64ORQconstmodifyidx1 |
| OpAMD64ORQconstmodifyidx8 |
| OpAMD64XORQconstmodifyidx1 |
| OpAMD64XORQconstmodifyidx8 |
| OpAMD64ADDLconstmodifyidx1 |
| OpAMD64ADDLconstmodifyidx4 |
| OpAMD64ADDLconstmodifyidx8 |
| OpAMD64ANDLconstmodifyidx1 |
| OpAMD64ANDLconstmodifyidx4 |
| OpAMD64ANDLconstmodifyidx8 |
| OpAMD64ORLconstmodifyidx1 |
| OpAMD64ORLconstmodifyidx4 |
| OpAMD64ORLconstmodifyidx8 |
| OpAMD64XORLconstmodifyidx1 |
| OpAMD64XORLconstmodifyidx4 |
| OpAMD64XORLconstmodifyidx8 |
| OpAMD64NEGQ |
| OpAMD64NEGL |
| OpAMD64NOTQ |
| OpAMD64NOTL |
| OpAMD64BSFQ |
| OpAMD64BSFL |
| OpAMD64BSRQ |
| OpAMD64BSRL |
| OpAMD64CMOVQEQ |
| OpAMD64CMOVQNE |
| OpAMD64CMOVQLT |
| OpAMD64CMOVQGT |
| OpAMD64CMOVQLE |
| OpAMD64CMOVQGE |
| OpAMD64CMOVQLS |
| OpAMD64CMOVQHI |
| OpAMD64CMOVQCC |
| OpAMD64CMOVQCS |
| OpAMD64CMOVLEQ |
| OpAMD64CMOVLNE |
| OpAMD64CMOVLLT |
| OpAMD64CMOVLGT |
| OpAMD64CMOVLLE |
| OpAMD64CMOVLGE |
| OpAMD64CMOVLLS |
| OpAMD64CMOVLHI |
| OpAMD64CMOVLCC |
| OpAMD64CMOVLCS |
| OpAMD64CMOVWEQ |
| OpAMD64CMOVWNE |
| OpAMD64CMOVWLT |
| OpAMD64CMOVWGT |
| OpAMD64CMOVWLE |
| OpAMD64CMOVWGE |
| OpAMD64CMOVWLS |
| OpAMD64CMOVWHI |
| OpAMD64CMOVWCC |
| OpAMD64CMOVWCS |
| OpAMD64CMOVQEQF |
| OpAMD64CMOVQNEF |
| OpAMD64CMOVQGTF |
| OpAMD64CMOVQGEF |
| OpAMD64CMOVLEQF |
| OpAMD64CMOVLNEF |
| OpAMD64CMOVLGTF |
| OpAMD64CMOVLGEF |
| OpAMD64CMOVWEQF |
| OpAMD64CMOVWNEF |
| OpAMD64CMOVWGTF |
| OpAMD64CMOVWGEF |
| OpAMD64BSWAPQ |
| OpAMD64BSWAPL |
| OpAMD64POPCNTQ |
| OpAMD64POPCNTL |
| OpAMD64SQRTSD |
| OpAMD64SQRTSS |
| OpAMD64ROUNDSD |
| OpAMD64VFMADD231SD |
| OpAMD64SBBQcarrymask |
| OpAMD64SBBLcarrymask |
| OpAMD64SETEQ |
| OpAMD64SETNE |
| OpAMD64SETL |
| OpAMD64SETLE |
| OpAMD64SETG |
| OpAMD64SETGE |
| OpAMD64SETB |
| OpAMD64SETBE |
| OpAMD64SETA |
| OpAMD64SETAE |
| OpAMD64SETO |
| OpAMD64SETEQstore |
| OpAMD64SETNEstore |
| OpAMD64SETLstore |
| OpAMD64SETLEstore |
| OpAMD64SETGstore |
| OpAMD64SETGEstore |
| OpAMD64SETBstore |
| OpAMD64SETBEstore |
| OpAMD64SETAstore |
| OpAMD64SETAEstore |
| OpAMD64SETEQF |
| OpAMD64SETNEF |
| OpAMD64SETORD |
| OpAMD64SETNAN |
| OpAMD64SETGF |
| OpAMD64SETGEF |
| OpAMD64MOVBQSX |
| OpAMD64MOVBQZX |
| OpAMD64MOVWQSX |
| OpAMD64MOVWQZX |
| OpAMD64MOVLQSX |
| OpAMD64MOVLQZX |
| OpAMD64MOVLconst |
| OpAMD64MOVQconst |
| OpAMD64CVTTSD2SL |
| OpAMD64CVTTSD2SQ |
| OpAMD64CVTTSS2SL |
| OpAMD64CVTTSS2SQ |
| OpAMD64CVTSL2SS |
| OpAMD64CVTSL2SD |
| OpAMD64CVTSQ2SS |
| OpAMD64CVTSQ2SD |
| OpAMD64CVTSD2SS |
| OpAMD64CVTSS2SD |
| OpAMD64MOVQi2f |
| OpAMD64MOVQf2i |
| OpAMD64MOVLi2f |
| OpAMD64MOVLf2i |
| OpAMD64PXOR |
| OpAMD64LEAQ |
| OpAMD64LEAL |
| OpAMD64LEAW |
| OpAMD64LEAQ1 |
| OpAMD64LEAL1 |
| OpAMD64LEAW1 |
| OpAMD64LEAQ2 |
| OpAMD64LEAL2 |
| OpAMD64LEAW2 |
| OpAMD64LEAQ4 |
| OpAMD64LEAL4 |
| OpAMD64LEAW4 |
| OpAMD64LEAQ8 |
| OpAMD64LEAL8 |
| OpAMD64LEAW8 |
| OpAMD64MOVBload |
| OpAMD64MOVBQSXload |
| OpAMD64MOVWload |
| OpAMD64MOVWQSXload |
| OpAMD64MOVLload |
| OpAMD64MOVLQSXload |
| OpAMD64MOVQload |
| OpAMD64MOVBstore |
| OpAMD64MOVWstore |
| OpAMD64MOVLstore |
| OpAMD64MOVQstore |
| OpAMD64MOVOload |
| OpAMD64MOVOstore |
| OpAMD64MOVBloadidx1 |
| OpAMD64MOVWloadidx1 |
| OpAMD64MOVWloadidx2 |
| OpAMD64MOVLloadidx1 |
| OpAMD64MOVLloadidx4 |
| OpAMD64MOVLloadidx8 |
| OpAMD64MOVQloadidx1 |
| OpAMD64MOVQloadidx8 |
| OpAMD64MOVBstoreidx1 |
| OpAMD64MOVWstoreidx1 |
| OpAMD64MOVWstoreidx2 |
| OpAMD64MOVLstoreidx1 |
| OpAMD64MOVLstoreidx4 |
| OpAMD64MOVLstoreidx8 |
| OpAMD64MOVQstoreidx1 |
| OpAMD64MOVQstoreidx8 |
| OpAMD64MOVBstoreconst |
| OpAMD64MOVWstoreconst |
| OpAMD64MOVLstoreconst |
| OpAMD64MOVQstoreconst |
| OpAMD64MOVOstoreconst |
| OpAMD64MOVBstoreconstidx1 |
| OpAMD64MOVWstoreconstidx1 |
| OpAMD64MOVWstoreconstidx2 |
| OpAMD64MOVLstoreconstidx1 |
| OpAMD64MOVLstoreconstidx4 |
| OpAMD64MOVQstoreconstidx1 |
| OpAMD64MOVQstoreconstidx8 |
| OpAMD64DUFFZERO |
| OpAMD64REPSTOSQ |
| OpAMD64CALLstatic |
| OpAMD64CALLtail |
| OpAMD64CALLclosure |
| OpAMD64CALLinter |
| OpAMD64DUFFCOPY |
| OpAMD64REPMOVSQ |
| OpAMD64InvertFlags |
| OpAMD64LoweredGetG |
| OpAMD64LoweredGetClosurePtr |
| OpAMD64LoweredGetCallerPC |
| OpAMD64LoweredGetCallerSP |
| OpAMD64LoweredNilCheck |
| OpAMD64LoweredWB |
| OpAMD64LoweredHasCPUFeature |
| OpAMD64LoweredPanicBoundsA |
| OpAMD64LoweredPanicBoundsB |
| OpAMD64LoweredPanicBoundsC |
| OpAMD64FlagEQ |
| OpAMD64FlagLT_ULT |
| OpAMD64FlagLT_UGT |
| OpAMD64FlagGT_UGT |
| OpAMD64FlagGT_ULT |
| OpAMD64MOVBatomicload |
| OpAMD64MOVLatomicload |
| OpAMD64MOVQatomicload |
| OpAMD64XCHGB |
| OpAMD64XCHGL |
| OpAMD64XCHGQ |
| OpAMD64XADDLlock |
| OpAMD64XADDQlock |
| OpAMD64AddTupleFirst32 |
| OpAMD64AddTupleFirst64 |
| OpAMD64CMPXCHGLlock |
| OpAMD64CMPXCHGQlock |
| OpAMD64ANDBlock |
| OpAMD64ANDLlock |
| OpAMD64ORBlock |
| OpAMD64ORLlock |
| OpAMD64PrefetchT0 |
| OpAMD64PrefetchNTA |
| OpAMD64ANDNQ |
| OpAMD64ANDNL |
| OpAMD64BLSIQ |
| OpAMD64BLSIL |
| OpAMD64BLSMSKQ |
| OpAMD64BLSMSKL |
| OpAMD64BLSRQ |
| OpAMD64BLSRL |
| OpAMD64TZCNTQ |
| OpAMD64TZCNTL |
| OpAMD64LZCNTQ |
| OpAMD64LZCNTL |
| OpAMD64MOVBEWstore |
| OpAMD64MOVBELload |
| OpAMD64MOVBELstore |
| OpAMD64MOVBEQload |
| OpAMD64MOVBEQstore |
| OpAMD64MOVBELloadidx1 |
| OpAMD64MOVBELloadidx4 |
| OpAMD64MOVBELloadidx8 |
| OpAMD64MOVBEQloadidx1 |
| OpAMD64MOVBEQloadidx8 |
| OpAMD64MOVBEWstoreidx1 |
| OpAMD64MOVBEWstoreidx2 |
| OpAMD64MOVBELstoreidx1 |
| OpAMD64MOVBELstoreidx4 |
| OpAMD64MOVBELstoreidx8 |
| OpAMD64MOVBEQstoreidx1 |
| OpAMD64MOVBEQstoreidx8 |
| OpAMD64SARXQ |
| OpAMD64SARXL |
| OpAMD64SHLXQ |
| OpAMD64SHLXL |
| OpAMD64SHRXQ |
| OpAMD64SHRXL |
| OpAMD64SARXLload |
| OpAMD64SARXQload |
| OpAMD64SHLXLload |
| OpAMD64SHLXQload |
| OpAMD64SHRXLload |
| OpAMD64SHRXQload |
| OpAMD64SARXLloadidx1 |
| OpAMD64SARXLloadidx4 |
| OpAMD64SARXLloadidx8 |
| OpAMD64SARXQloadidx1 |
| OpAMD64SARXQloadidx8 |
| OpAMD64SHLXLloadidx1 |
| OpAMD64SHLXLloadidx4 |
| OpAMD64SHLXLloadidx8 |
| OpAMD64SHLXQloadidx1 |
| OpAMD64SHLXQloadidx8 |
| OpAMD64SHRXLloadidx1 |
| OpAMD64SHRXLloadidx4 |
| OpAMD64SHRXLloadidx8 |
| OpAMD64SHRXQloadidx1 |
| OpAMD64SHRXQloadidx8 |
| |
| OpARMADD |
| OpARMADDconst |
| OpARMSUB |
| OpARMSUBconst |
| OpARMRSB |
| OpARMRSBconst |
| OpARMMUL |
| OpARMHMUL |
| OpARMHMULU |
| OpARMCALLudiv |
| OpARMADDS |
| OpARMADDSconst |
| OpARMADC |
| OpARMADCconst |
| OpARMSUBS |
| OpARMSUBSconst |
| OpARMRSBSconst |
| OpARMSBC |
| OpARMSBCconst |
| OpARMRSCconst |
| OpARMMULLU |
| OpARMMULA |
| OpARMMULS |
| OpARMADDF |
| OpARMADDD |
| OpARMSUBF |
| OpARMSUBD |
| OpARMMULF |
| OpARMMULD |
| OpARMNMULF |
| OpARMNMULD |
| OpARMDIVF |
| OpARMDIVD |
| OpARMMULAF |
| OpARMMULAD |
| OpARMMULSF |
| OpARMMULSD |
| OpARMFMULAD |
| OpARMAND |
| OpARMANDconst |
| OpARMOR |
| OpARMORconst |
| OpARMXOR |
| OpARMXORconst |
| OpARMBIC |
| OpARMBICconst |
| OpARMBFX |
| OpARMBFXU |
| OpARMMVN |
| OpARMNEGF |
| OpARMNEGD |
| OpARMSQRTD |
| OpARMSQRTF |
| OpARMABSD |
| OpARMCLZ |
| OpARMREV |
| OpARMREV16 |
| OpARMRBIT |
| OpARMSLL |
| OpARMSLLconst |
| OpARMSRL |
| OpARMSRLconst |
| OpARMSRA |
| OpARMSRAconst |
| OpARMSRR |
| OpARMSRRconst |
| OpARMADDshiftLL |
| OpARMADDshiftRL |
| OpARMADDshiftRA |
| OpARMSUBshiftLL |
| OpARMSUBshiftRL |
| OpARMSUBshiftRA |
| OpARMRSBshiftLL |
| OpARMRSBshiftRL |
| OpARMRSBshiftRA |
| OpARMANDshiftLL |
| OpARMANDshiftRL |
| OpARMANDshiftRA |
| OpARMORshiftLL |
| OpARMORshiftRL |
| OpARMORshiftRA |
| OpARMXORshiftLL |
| OpARMXORshiftRL |
| OpARMXORshiftRA |
| OpARMXORshiftRR |
| OpARMBICshiftLL |
| OpARMBICshiftRL |
| OpARMBICshiftRA |
| OpARMMVNshiftLL |
| OpARMMVNshiftRL |
| OpARMMVNshiftRA |
| OpARMADCshiftLL |
| OpARMADCshiftRL |
| OpARMADCshiftRA |
| OpARMSBCshiftLL |
| OpARMSBCshiftRL |
| OpARMSBCshiftRA |
| OpARMRSCshiftLL |
| OpARMRSCshiftRL |
| OpARMRSCshiftRA |
| OpARMADDSshiftLL |
| OpARMADDSshiftRL |
| OpARMADDSshiftRA |
| OpARMSUBSshiftLL |
| OpARMSUBSshiftRL |
| OpARMSUBSshiftRA |
| OpARMRSBSshiftLL |
| OpARMRSBSshiftRL |
| OpARMRSBSshiftRA |
| OpARMADDshiftLLreg |
| OpARMADDshiftRLreg |
| OpARMADDshiftRAreg |
| OpARMSUBshiftLLreg |
| OpARMSUBshiftRLreg |
| OpARMSUBshiftRAreg |
| OpARMRSBshiftLLreg |
| OpARMRSBshiftRLreg |
| OpARMRSBshiftRAreg |
| OpARMANDshiftLLreg |
| OpARMANDshiftRLreg |
| OpARMANDshiftRAreg |
| OpARMORshiftLLreg |
| OpARMORshiftRLreg |
| OpARMORshiftRAreg |
| OpARMXORshiftLLreg |
| OpARMXORshiftRLreg |
| OpARMXORshiftRAreg |
| OpARMBICshiftLLreg |
| OpARMBICshiftRLreg |
| OpARMBICshiftRAreg |
| OpARMMVNshiftLLreg |
| OpARMMVNshiftRLreg |
| OpARMMVNshiftRAreg |
| OpARMADCshiftLLreg |
| OpARMADCshiftRLreg |
| OpARMADCshiftRAreg |
| OpARMSBCshiftLLreg |
| OpARMSBCshiftRLreg |
| OpARMSBCshiftRAreg |
| OpARMRSCshiftLLreg |
| OpARMRSCshiftRLreg |
| OpARMRSCshiftRAreg |
| OpARMADDSshiftLLreg |
| OpARMADDSshiftRLreg |
| OpARMADDSshiftRAreg |
| OpARMSUBSshiftLLreg |
| OpARMSUBSshiftRLreg |
| OpARMSUBSshiftRAreg |
| OpARMRSBSshiftLLreg |
| OpARMRSBSshiftRLreg |
| OpARMRSBSshiftRAreg |
| OpARMCMP |
| OpARMCMPconst |
| OpARMCMN |
| OpARMCMNconst |
| OpARMTST |
| OpARMTSTconst |
| OpARMTEQ |
| OpARMTEQconst |
| OpARMCMPF |
| OpARMCMPD |
| OpARMCMPshiftLL |
| OpARMCMPshiftRL |
| OpARMCMPshiftRA |
| OpARMCMNshiftLL |
| OpARMCMNshiftRL |
| OpARMCMNshiftRA |
| OpARMTSTshiftLL |
| OpARMTSTshiftRL |
| OpARMTSTshiftRA |
| OpARMTEQshiftLL |
| OpARMTEQshiftRL |
| OpARMTEQshiftRA |
| OpARMCMPshiftLLreg |
| OpARMCMPshiftRLreg |
| OpARMCMPshiftRAreg |
| OpARMCMNshiftLLreg |
| OpARMCMNshiftRLreg |
| OpARMCMNshiftRAreg |
| OpARMTSTshiftLLreg |
| OpARMTSTshiftRLreg |
| OpARMTSTshiftRAreg |
| OpARMTEQshiftLLreg |
| OpARMTEQshiftRLreg |
| OpARMTEQshiftRAreg |
| OpARMCMPF0 |
| OpARMCMPD0 |
| OpARMMOVWconst |
| OpARMMOVFconst |
| OpARMMOVDconst |
| OpARMMOVWaddr |
| OpARMMOVBload |
| OpARMMOVBUload |
| OpARMMOVHload |
| OpARMMOVHUload |
| OpARMMOVWload |
| OpARMMOVFload |
| OpARMMOVDload |
| OpARMMOVBstore |
| OpARMMOVHstore |
| OpARMMOVWstore |
| OpARMMOVFstore |
| OpARMMOVDstore |
| OpARMMOVWloadidx |
| OpARMMOVWloadshiftLL |
| OpARMMOVWloadshiftRL |
| OpARMMOVWloadshiftRA |
| OpARMMOVBUloadidx |
| OpARMMOVBloadidx |
| OpARMMOVHUloadidx |
| OpARMMOVHloadidx |
| OpARMMOVWstoreidx |
| OpARMMOVWstoreshiftLL |
| OpARMMOVWstoreshiftRL |
| OpARMMOVWstoreshiftRA |
| OpARMMOVBstoreidx |
| OpARMMOVHstoreidx |
| OpARMMOVBreg |
| OpARMMOVBUreg |
| OpARMMOVHreg |
| OpARMMOVHUreg |
| OpARMMOVWreg |
| OpARMMOVWnop |
| OpARMMOVWF |
| OpARMMOVWD |
| OpARMMOVWUF |
| OpARMMOVWUD |
| OpARMMOVFW |
| OpARMMOVDW |
| OpARMMOVFWU |
| OpARMMOVDWU |
| OpARMMOVFD |
| OpARMMOVDF |
| OpARMCMOVWHSconst |
| OpARMCMOVWLSconst |
| OpARMSRAcond |
| OpARMCALLstatic |
| OpARMCALLtail |
| OpARMCALLclosure |
| OpARMCALLinter |
| OpARMLoweredNilCheck |
| OpARMEqual |
| OpARMNotEqual |
| OpARMLessThan |
| OpARMLessEqual |
| OpARMGreaterThan |
| OpARMGreaterEqual |
| OpARMLessThanU |
| OpARMLessEqualU |
| OpARMGreaterThanU |
| OpARMGreaterEqualU |
| OpARMDUFFZERO |
| OpARMDUFFCOPY |
| OpARMLoweredZero |
| OpARMLoweredMove |
| OpARMLoweredGetClosurePtr |
| OpARMLoweredGetCallerSP |
| OpARMLoweredGetCallerPC |
| OpARMLoweredPanicBoundsA |
| OpARMLoweredPanicBoundsB |
| OpARMLoweredPanicBoundsC |
| OpARMLoweredPanicExtendA |
| OpARMLoweredPanicExtendB |
| OpARMLoweredPanicExtendC |
| OpARMFlagConstant |
| OpARMInvertFlags |
| OpARMLoweredWB |
| |
| OpARM64ADCSflags |
| OpARM64ADCzerocarry |
| OpARM64ADD |
| OpARM64ADDconst |
| OpARM64ADDSconstflags |
| OpARM64ADDSflags |
| OpARM64SUB |
| OpARM64SUBconst |
| OpARM64SBCSflags |
| OpARM64SUBSflags |
| OpARM64MUL |
| OpARM64MULW |
| OpARM64MNEG |
| OpARM64MNEGW |
| OpARM64MULH |
| OpARM64UMULH |
| OpARM64MULL |
| OpARM64UMULL |
| OpARM64DIV |
| OpARM64UDIV |
| OpARM64DIVW |
| OpARM64UDIVW |
| OpARM64MOD |
| OpARM64UMOD |
| OpARM64MODW |
| OpARM64UMODW |
| OpARM64FADDS |
| OpARM64FADDD |
| OpARM64FSUBS |
| OpARM64FSUBD |
| OpARM64FMULS |
| OpARM64FMULD |
| OpARM64FNMULS |
| OpARM64FNMULD |
| OpARM64FDIVS |
| OpARM64FDIVD |
| OpARM64AND |
| OpARM64ANDconst |
| OpARM64OR |
| OpARM64ORconst |
| OpARM64XOR |
| OpARM64XORconst |
| OpARM64BIC |
| OpARM64EON |
| OpARM64ORN |
| OpARM64MVN |
| OpARM64NEG |
| OpARM64NEGSflags |
| OpARM64NGCzerocarry |
| OpARM64FABSD |
| OpARM64FNEGS |
| OpARM64FNEGD |
| OpARM64FSQRTD |
| OpARM64FSQRTS |
| OpARM64REV |
| OpARM64REVW |
| OpARM64REV16 |
| OpARM64REV16W |
| OpARM64RBIT |
| OpARM64RBITW |
| OpARM64CLZ |
| OpARM64CLZW |
| OpARM64VCNT |
| OpARM64VUADDLV |
| OpARM64LoweredRound32F |
| OpARM64LoweredRound64F |
| OpARM64FMADDS |
| OpARM64FMADDD |
| OpARM64FNMADDS |
| OpARM64FNMADDD |
| OpARM64FMSUBS |
| OpARM64FMSUBD |
| OpARM64FNMSUBS |
| OpARM64FNMSUBD |
| OpARM64MADD |
| OpARM64MADDW |
| OpARM64MSUB |
| OpARM64MSUBW |
| OpARM64SLL |
| OpARM64SLLconst |
| OpARM64SRL |
| OpARM64SRLconst |
| OpARM64SRA |
| OpARM64SRAconst |
| OpARM64ROR |
| OpARM64RORW |
| OpARM64RORconst |
| OpARM64RORWconst |
| OpARM64EXTRconst |
| OpARM64EXTRWconst |
| OpARM64CMP |
| OpARM64CMPconst |
| OpARM64CMPW |
| OpARM64CMPWconst |
| OpARM64CMN |
| OpARM64CMNconst |
| OpARM64CMNW |
| OpARM64CMNWconst |
| OpARM64TST |
| OpARM64TSTconst |
| OpARM64TSTW |
| OpARM64TSTWconst |
| OpARM64FCMPS |
| OpARM64FCMPD |
| OpARM64FCMPS0 |
| OpARM64FCMPD0 |
| OpARM64MVNshiftLL |
| OpARM64MVNshiftRL |
| OpARM64MVNshiftRA |
| OpARM64MVNshiftRO |
| OpARM64NEGshiftLL |
| OpARM64NEGshiftRL |
| OpARM64NEGshiftRA |
| OpARM64ADDshiftLL |
| OpARM64ADDshiftRL |
| OpARM64ADDshiftRA |
| OpARM64SUBshiftLL |
| OpARM64SUBshiftRL |
| OpARM64SUBshiftRA |
| OpARM64ANDshiftLL |
| OpARM64ANDshiftRL |
| OpARM64ANDshiftRA |
| OpARM64ANDshiftRO |
| OpARM64ORshiftLL |
| OpARM64ORshiftRL |
| OpARM64ORshiftRA |
| OpARM64ORshiftRO |
| OpARM64XORshiftLL |
| OpARM64XORshiftRL |
| OpARM64XORshiftRA |
| OpARM64XORshiftRO |
| OpARM64BICshiftLL |
| OpARM64BICshiftRL |
| OpARM64BICshiftRA |
| OpARM64BICshiftRO |
| OpARM64EONshiftLL |
| OpARM64EONshiftRL |
| OpARM64EONshiftRA |
| OpARM64EONshiftRO |
| OpARM64ORNshiftLL |
| OpARM64ORNshiftRL |
| OpARM64ORNshiftRA |
| OpARM64ORNshiftRO |
| OpARM64CMPshiftLL |
| OpARM64CMPshiftRL |
| OpARM64CMPshiftRA |
| OpARM64CMNshiftLL |
| OpARM64CMNshiftRL |
| OpARM64CMNshiftRA |
| OpARM64TSTshiftLL |
| OpARM64TSTshiftRL |
| OpARM64TSTshiftRA |
| OpARM64TSTshiftRO |
| OpARM64BFI |
| OpARM64BFXIL |
| OpARM64SBFIZ |
| OpARM64SBFX |
| OpARM64UBFIZ |
| OpARM64UBFX |
| OpARM64MOVDconst |
| OpARM64FMOVSconst |
| OpARM64FMOVDconst |
| OpARM64MOVDaddr |
| OpARM64MOVBload |
| OpARM64MOVBUload |
| OpARM64MOVHload |
| OpARM64MOVHUload |
| OpARM64MOVWload |
| OpARM64MOVWUload |
| OpARM64MOVDload |
| OpARM64LDP |
| OpARM64FMOVSload |
| OpARM64FMOVDload |
| OpARM64MOVDloadidx |
| OpARM64MOVWloadidx |
| OpARM64MOVWUloadidx |
| OpARM64MOVHloadidx |
| OpARM64MOVHUloadidx |
| OpARM64MOVBloadidx |
| OpARM64MOVBUloadidx |
| OpARM64FMOVSloadidx |
| OpARM64FMOVDloadidx |
| OpARM64MOVHloadidx2 |
| OpARM64MOVHUloadidx2 |
| OpARM64MOVWloadidx4 |
| OpARM64MOVWUloadidx4 |
| OpARM64MOVDloadidx8 |
| OpARM64FMOVSloadidx4 |
| OpARM64FMOVDloadidx8 |
| OpARM64MOVBstore |
| OpARM64MOVHstore |
| OpARM64MOVWstore |
| OpARM64MOVDstore |
| OpARM64STP |
| OpARM64FMOVSstore |
| OpARM64FMOVDstore |
| OpARM64MOVBstoreidx |
| OpARM64MOVHstoreidx |
| OpARM64MOVWstoreidx |
| OpARM64MOVDstoreidx |
| OpARM64FMOVSstoreidx |
| OpARM64FMOVDstoreidx |
| OpARM64MOVHstoreidx2 |
| OpARM64MOVWstoreidx4 |
| OpARM64MOVDstoreidx8 |
| OpARM64FMOVSstoreidx4 |
| OpARM64FMOVDstoreidx8 |
| OpARM64MOVBstorezero |
| OpARM64MOVHstorezero |
| OpARM64MOVWstorezero |
| OpARM64MOVDstorezero |
| OpARM64MOVQstorezero |
| OpARM64MOVBstorezeroidx |
| OpARM64MOVHstorezeroidx |
| OpARM64MOVWstorezeroidx |
| OpARM64MOVDstorezeroidx |
| OpARM64MOVHstorezeroidx2 |
| OpARM64MOVWstorezeroidx4 |
| OpARM64MOVDstorezeroidx8 |
| OpARM64FMOVDgpfp |
| OpARM64FMOVDfpgp |
| OpARM64FMOVSgpfp |
| OpARM64FMOVSfpgp |
| OpARM64MOVBreg |
| OpARM64MOVBUreg |
| OpARM64MOVHreg |
| OpARM64MOVHUreg |
| OpARM64MOVWreg |
| OpARM64MOVWUreg |
| OpARM64MOVDreg |
| OpARM64MOVDnop |
| OpARM64SCVTFWS |
| OpARM64SCVTFWD |
| OpARM64UCVTFWS |
| OpARM64UCVTFWD |
| OpARM64SCVTFS |
| OpARM64SCVTFD |
| OpARM64UCVTFS |
| OpARM64UCVTFD |
| OpARM64FCVTZSSW |
| OpARM64FCVTZSDW |
| OpARM64FCVTZUSW |
| OpARM64FCVTZUDW |
| OpARM64FCVTZSS |
| OpARM64FCVTZSD |
| OpARM64FCVTZUS |
| OpARM64FCVTZUD |
| OpARM64FCVTSD |
| OpARM64FCVTDS |
| OpARM64FRINTAD |
| OpARM64FRINTMD |
| OpARM64FRINTND |
| OpARM64FRINTPD |
| OpARM64FRINTZD |
| OpARM64CSEL |
| OpARM64CSEL0 |
| OpARM64CSINC |
| OpARM64CSINV |
| OpARM64CSNEG |
| OpARM64CSETM |
| OpARM64CALLstatic |
| OpARM64CALLtail |
| OpARM64CALLclosure |
| OpARM64CALLinter |
| OpARM64LoweredNilCheck |
| OpARM64Equal |
| OpARM64NotEqual |
| OpARM64LessThan |
| OpARM64LessEqual |
| OpARM64GreaterThan |
| OpARM64GreaterEqual |
| OpARM64LessThanU |
| OpARM64LessEqualU |
| OpARM64GreaterThanU |
| OpARM64GreaterEqualU |
| OpARM64LessThanF |
| OpARM64LessEqualF |
| OpARM64GreaterThanF |
| OpARM64GreaterEqualF |
| OpARM64NotLessThanF |
| OpARM64NotLessEqualF |
| OpARM64NotGreaterThanF |
| OpARM64NotGreaterEqualF |
| OpARM64DUFFZERO |
| OpARM64LoweredZero |
| OpARM64DUFFCOPY |
| OpARM64LoweredMove |
| OpARM64LoweredGetClosurePtr |
| OpARM64LoweredGetCallerSP |
| OpARM64LoweredGetCallerPC |
| OpARM64FlagConstant |
| OpARM64InvertFlags |
| OpARM64LDAR |
| OpARM64LDARB |
| OpARM64LDARW |
| OpARM64STLRB |
| OpARM64STLR |
| OpARM64STLRW |
| OpARM64LoweredAtomicExchange64 |
| OpARM64LoweredAtomicExchange32 |
| OpARM64LoweredAtomicExchange64Variant |
| OpARM64LoweredAtomicExchange32Variant |
| OpARM64LoweredAtomicAdd64 |
| OpARM64LoweredAtomicAdd32 |
| OpARM64LoweredAtomicAdd64Variant |
| OpARM64LoweredAtomicAdd32Variant |
| OpARM64LoweredAtomicCas64 |
| OpARM64LoweredAtomicCas32 |
| OpARM64LoweredAtomicCas64Variant |
| OpARM64LoweredAtomicCas32Variant |
| OpARM64LoweredAtomicAnd8 |
| OpARM64LoweredAtomicAnd32 |
| OpARM64LoweredAtomicOr8 |
| OpARM64LoweredAtomicOr32 |
| OpARM64LoweredAtomicAnd8Variant |
| OpARM64LoweredAtomicAnd32Variant |
| OpARM64LoweredAtomicOr8Variant |
| OpARM64LoweredAtomicOr32Variant |
| OpARM64LoweredWB |
| OpARM64LoweredPanicBoundsA |
| OpARM64LoweredPanicBoundsB |
| OpARM64LoweredPanicBoundsC |
| OpARM64PRFM |
| OpARM64DMB |
| |
| OpLOONG64ADDV |
| OpLOONG64ADDVconst |
| OpLOONG64SUBV |
| OpLOONG64SUBVconst |
| OpLOONG64MULV |
| OpLOONG64MULVU |
| OpLOONG64DIVV |
| OpLOONG64DIVVU |
| OpLOONG64ADDF |
| OpLOONG64ADDD |
| OpLOONG64SUBF |
| OpLOONG64SUBD |
| OpLOONG64MULF |
| OpLOONG64MULD |
| OpLOONG64DIVF |
| OpLOONG64DIVD |
| OpLOONG64AND |
| OpLOONG64ANDconst |
| OpLOONG64OR |
| OpLOONG64ORconst |
| OpLOONG64XOR |
| OpLOONG64XORconst |
| OpLOONG64NOR |
| OpLOONG64NORconst |
| OpLOONG64NEGV |
| OpLOONG64NEGF |
| OpLOONG64NEGD |
| OpLOONG64SQRTD |
| OpLOONG64SQRTF |
| OpLOONG64MASKEQZ |
| OpLOONG64MASKNEZ |
| OpLOONG64SLLV |
| OpLOONG64SLLVconst |
| OpLOONG64SRLV |
| OpLOONG64SRLVconst |
| OpLOONG64SRAV |
| OpLOONG64SRAVconst |
| OpLOONG64ROTR |
| OpLOONG64ROTRV |
| OpLOONG64ROTRconst |
| OpLOONG64ROTRVconst |
| OpLOONG64SGT |
| OpLOONG64SGTconst |
| OpLOONG64SGTU |
| OpLOONG64SGTUconst |
| OpLOONG64CMPEQF |
| OpLOONG64CMPEQD |
| OpLOONG64CMPGEF |
| OpLOONG64CMPGED |
| OpLOONG64CMPGTF |
| OpLOONG64CMPGTD |
| OpLOONG64MOVVconst |
| OpLOONG64MOVFconst |
| OpLOONG64MOVDconst |
| OpLOONG64MOVVaddr |
| OpLOONG64MOVBload |
| OpLOONG64MOVBUload |
| OpLOONG64MOVHload |
| OpLOONG64MOVHUload |
| OpLOONG64MOVWload |
| OpLOONG64MOVWUload |
| OpLOONG64MOVVload |
| OpLOONG64MOVFload |
| OpLOONG64MOVDload |
| OpLOONG64MOVBstore |
| OpLOONG64MOVHstore |
| OpLOONG64MOVWstore |
| OpLOONG64MOVVstore |
| OpLOONG64MOVFstore |
| OpLOONG64MOVDstore |
| OpLOONG64MOVBstorezero |
| OpLOONG64MOVHstorezero |
| OpLOONG64MOVWstorezero |
| OpLOONG64MOVVstorezero |
| OpLOONG64MOVBreg |
| OpLOONG64MOVBUreg |
| OpLOONG64MOVHreg |
| OpLOONG64MOVHUreg |
| OpLOONG64MOVWreg |
| OpLOONG64MOVWUreg |
| OpLOONG64MOVVreg |
| OpLOONG64MOVVnop |
| OpLOONG64MOVWF |
| OpLOONG64MOVWD |
| OpLOONG64MOVVF |
| OpLOONG64MOVVD |
| OpLOONG64TRUNCFW |
| OpLOONG64TRUNCDW |
| OpLOONG64TRUNCFV |
| OpLOONG64TRUNCDV |
| OpLOONG64MOVFD |
| OpLOONG64MOVDF |
| OpLOONG64CALLstatic |
| OpLOONG64CALLtail |
| OpLOONG64CALLclosure |
| OpLOONG64CALLinter |
| OpLOONG64DUFFZERO |
| OpLOONG64DUFFCOPY |
| OpLOONG64LoweredZero |
| OpLOONG64LoweredMove |
| OpLOONG64LoweredAtomicLoad8 |
| OpLOONG64LoweredAtomicLoad32 |
| OpLOONG64LoweredAtomicLoad64 |
| OpLOONG64LoweredAtomicStore8 |
| OpLOONG64LoweredAtomicStore32 |
| OpLOONG64LoweredAtomicStore64 |
| OpLOONG64LoweredAtomicStorezero32 |
| OpLOONG64LoweredAtomicStorezero64 |
| OpLOONG64LoweredAtomicExchange32 |
| OpLOONG64LoweredAtomicExchange64 |
| OpLOONG64LoweredAtomicAdd32 |
| OpLOONG64LoweredAtomicAdd64 |
| OpLOONG64LoweredAtomicAddconst32 |
| OpLOONG64LoweredAtomicAddconst64 |
| OpLOONG64LoweredAtomicCas32 |
| OpLOONG64LoweredAtomicCas64 |
| OpLOONG64LoweredNilCheck |
| OpLOONG64FPFlagTrue |
| OpLOONG64FPFlagFalse |
| OpLOONG64LoweredGetClosurePtr |
| OpLOONG64LoweredGetCallerSP |
| OpLOONG64LoweredGetCallerPC |
| OpLOONG64LoweredWB |
| OpLOONG64LoweredPanicBoundsA |
| OpLOONG64LoweredPanicBoundsB |
| OpLOONG64LoweredPanicBoundsC |
| |
| OpMIPSADD |
| OpMIPSADDconst |
| OpMIPSSUB |
| OpMIPSSUBconst |
| OpMIPSMUL |
| OpMIPSMULT |
| OpMIPSMULTU |
| OpMIPSDIV |
| OpMIPSDIVU |
| OpMIPSADDF |
| OpMIPSADDD |
| OpMIPSSUBF |
| OpMIPSSUBD |
| OpMIPSMULF |
| OpMIPSMULD |
| OpMIPSDIVF |
| OpMIPSDIVD |
| OpMIPSAND |
| OpMIPSANDconst |
| OpMIPSOR |
| OpMIPSORconst |
| OpMIPSXOR |
| OpMIPSXORconst |
| OpMIPSNOR |
| OpMIPSNORconst |
| OpMIPSNEG |
| OpMIPSNEGF |
| OpMIPSNEGD |
| OpMIPSSQRTD |
| OpMIPSSQRTF |
| OpMIPSSLL |
| OpMIPSSLLconst |
| OpMIPSSRL |
| OpMIPSSRLconst |
| OpMIPSSRA |
| OpMIPSSRAconst |
| OpMIPSCLZ |
| OpMIPSSGT |
| OpMIPSSGTconst |
| OpMIPSSGTzero |
| OpMIPSSGTU |
| OpMIPSSGTUconst |
| OpMIPSSGTUzero |
| OpMIPSCMPEQF |
| OpMIPSCMPEQD |
| OpMIPSCMPGEF |
| OpMIPSCMPGED |
| OpMIPSCMPGTF |
| OpMIPSCMPGTD |
| OpMIPSMOVWconst |
| OpMIPSMOVFconst |
| OpMIPSMOVDconst |
| OpMIPSMOVWaddr |
| OpMIPSMOVBload |
| OpMIPSMOVBUload |
| OpMIPSMOVHload |
| OpMIPSMOVHUload |
| OpMIPSMOVWload |
| OpMIPSMOVFload |
| OpMIPSMOVDload |
| OpMIPSMOVBstore |
| OpMIPSMOVHstore |
| OpMIPSMOVWstore |
| OpMIPSMOVFstore |
| OpMIPSMOVDstore |
| OpMIPSMOVBstorezero |
| OpMIPSMOVHstorezero |
| OpMIPSMOVWstorezero |
| OpMIPSMOVBreg |
| OpMIPSMOVBUreg |
| OpMIPSMOVHreg |
| OpMIPSMOVHUreg |
| OpMIPSMOVWreg |
| OpMIPSMOVWnop |
| OpMIPSCMOVZ |
| OpMIPSCMOVZzero |
| OpMIPSMOVWF |
| OpMIPSMOVWD |
| OpMIPSTRUNCFW |
| OpMIPSTRUNCDW |
| OpMIPSMOVFD |
| OpMIPSMOVDF |
| OpMIPSCALLstatic |
| OpMIPSCALLtail |
| OpMIPSCALLclosure |
| OpMIPSCALLinter |
| OpMIPSLoweredAtomicLoad8 |
| OpMIPSLoweredAtomicLoad32 |
| OpMIPSLoweredAtomicStore8 |
| OpMIPSLoweredAtomicStore32 |
| OpMIPSLoweredAtomicStorezero |
| OpMIPSLoweredAtomicExchange |
| OpMIPSLoweredAtomicAdd |
| OpMIPSLoweredAtomicAddconst |
| OpMIPSLoweredAtomicCas |
| OpMIPSLoweredAtomicAnd |
| OpMIPSLoweredAtomicOr |
| OpMIPSLoweredZero |
| OpMIPSLoweredMove |
| OpMIPSLoweredNilCheck |
| OpMIPSFPFlagTrue |
| OpMIPSFPFlagFalse |
| OpMIPSLoweredGetClosurePtr |
| OpMIPSLoweredGetCallerSP |
| OpMIPSLoweredGetCallerPC |
| OpMIPSLoweredWB |
| OpMIPSLoweredPanicBoundsA |
| OpMIPSLoweredPanicBoundsB |
| OpMIPSLoweredPanicBoundsC |
| OpMIPSLoweredPanicExtendA |
| OpMIPSLoweredPanicExtendB |
| OpMIPSLoweredPanicExtendC |
| |
| OpMIPS64ADDV |
| OpMIPS64ADDVconst |
| OpMIPS64SUBV |
| OpMIPS64SUBVconst |
| OpMIPS64MULV |
| OpMIPS64MULVU |
| OpMIPS64DIVV |
| OpMIPS64DIVVU |
| OpMIPS64ADDF |
| OpMIPS64ADDD |
| OpMIPS64SUBF |
| OpMIPS64SUBD |
| OpMIPS64MULF |
| OpMIPS64MULD |
| OpMIPS64DIVF |
| OpMIPS64DIVD |
| OpMIPS64AND |
| OpMIPS64ANDconst |
| OpMIPS64OR |
| OpMIPS64ORconst |
| OpMIPS64XOR |
| OpMIPS64XORconst |
| OpMIPS64NOR |
| OpMIPS64NORconst |
| OpMIPS64NEGV |
| OpMIPS64NEGF |
| OpMIPS64NEGD |
| OpMIPS64SQRTD |
| OpMIPS64SQRTF |
| OpMIPS64SLLV |
| OpMIPS64SLLVconst |
| OpMIPS64SRLV |
| OpMIPS64SRLVconst |
| OpMIPS64SRAV |
| OpMIPS64SRAVconst |
| OpMIPS64SGT |
| OpMIPS64SGTconst |
| OpMIPS64SGTU |
| OpMIPS64SGTUconst |
| OpMIPS64CMPEQF |
| OpMIPS64CMPEQD |
| OpMIPS64CMPGEF |
| OpMIPS64CMPGED |
| OpMIPS64CMPGTF |
| OpMIPS64CMPGTD |
| OpMIPS64MOVVconst |
| OpMIPS64MOVFconst |
| OpMIPS64MOVDconst |
| OpMIPS64MOVVaddr |
| OpMIPS64MOVBload |
| OpMIPS64MOVBUload |
| OpMIPS64MOVHload |
| OpMIPS64MOVHUload |
| OpMIPS64MOVWload |
| OpMIPS64MOVWUload |
| OpMIPS64MOVVload |
| OpMIPS64MOVFload |
| OpMIPS64MOVDload |
| OpMIPS64MOVBstore |
| OpMIPS64MOVHstore |
| OpMIPS64MOVWstore |
| OpMIPS64MOVVstore |
| OpMIPS64MOVFstore |
| OpMIPS64MOVDstore |
| OpMIPS64MOVBstorezero |
| OpMIPS64MOVHstorezero |
| OpMIPS64MOVWstorezero |
| OpMIPS64MOVVstorezero |
| OpMIPS64MOVBreg |
| OpMIPS64MOVBUreg |
| OpMIPS64MOVHreg |
| OpMIPS64MOVHUreg |
| OpMIPS64MOVWreg |
| OpMIPS64MOVWUreg |
| OpMIPS64MOVVreg |
| OpMIPS64MOVVnop |
| OpMIPS64MOVWF |
| OpMIPS64MOVWD |
| OpMIPS64MOVVF |
| OpMIPS64MOVVD |
| OpMIPS64TRUNCFW |
| OpMIPS64TRUNCDW |
| OpMIPS64TRUNCFV |
| OpMIPS64TRUNCDV |
| OpMIPS64MOVFD |
| OpMIPS64MOVDF |
| OpMIPS64CALLstatic |
| OpMIPS64CALLtail |
| OpMIPS64CALLclosure |
| OpMIPS64CALLinter |
| OpMIPS64DUFFZERO |
| OpMIPS64DUFFCOPY |
| OpMIPS64LoweredZero |
| OpMIPS64LoweredMove |
| OpMIPS64LoweredAtomicLoad8 |
| OpMIPS64LoweredAtomicLoad32 |
| OpMIPS64LoweredAtomicLoad64 |
| OpMIPS64LoweredAtomicStore8 |
| OpMIPS64LoweredAtomicStore32 |
| OpMIPS64LoweredAtomicStore64 |
| OpMIPS64LoweredAtomicStorezero32 |
| OpMIPS64LoweredAtomicStorezero64 |
| OpMIPS64LoweredAtomicExchange32 |
| OpMIPS64LoweredAtomicExchange64 |
| OpMIPS64LoweredAtomicAdd32 |
| OpMIPS64LoweredAtomicAdd64 |
| OpMIPS64LoweredAtomicAddconst32 |
| OpMIPS64LoweredAtomicAddconst64 |
| OpMIPS64LoweredAtomicCas32 |
| OpMIPS64LoweredAtomicCas64 |
| OpMIPS64LoweredNilCheck |
| OpMIPS64FPFlagTrue |
| OpMIPS64FPFlagFalse |
| OpMIPS64LoweredGetClosurePtr |
| OpMIPS64LoweredGetCallerSP |
| OpMIPS64LoweredGetCallerPC |
| OpMIPS64LoweredWB |
| OpMIPS64LoweredPanicBoundsA |
| OpMIPS64LoweredPanicBoundsB |
| OpMIPS64LoweredPanicBoundsC |
| |
| OpPPC64ADD |
| OpPPC64ADDconst |
| OpPPC64FADD |
| OpPPC64FADDS |
| OpPPC64SUB |
| OpPPC64SUBFCconst |
| OpPPC64FSUB |
| OpPPC64FSUBS |
| OpPPC64MULLD |
| OpPPC64MULLW |
| OpPPC64MULLDconst |
| OpPPC64MULLWconst |
| OpPPC64MADDLD |
| OpPPC64MULHD |
| OpPPC64MULHW |
| OpPPC64MULHDU |
| OpPPC64MULHWU |
| OpPPC64FMUL |
| OpPPC64FMULS |
| OpPPC64FMADD |
| OpPPC64FMADDS |
| OpPPC64FMSUB |
| OpPPC64FMSUBS |
| OpPPC64SRAD |
| OpPPC64SRAW |
| OpPPC64SRD |
| OpPPC64SRW |
| OpPPC64SLD |
| OpPPC64SLW |
| OpPPC64ROTL |
| OpPPC64ROTLW |
| OpPPC64RLDICL |
| OpPPC64CLRLSLWI |
| OpPPC64CLRLSLDI |
| OpPPC64ADDC |
| OpPPC64SUBC |
| OpPPC64ADDCconst |
| OpPPC64SUBCconst |
| OpPPC64ADDE |
| OpPPC64SUBE |
| OpPPC64ADDZEzero |
| OpPPC64SUBZEzero |
| OpPPC64SRADconst |
| OpPPC64SRAWconst |
| OpPPC64SRDconst |
| OpPPC64SRWconst |
| OpPPC64SLDconst |
| OpPPC64SLWconst |
| OpPPC64ROTLconst |
| OpPPC64ROTLWconst |
| OpPPC64EXTSWSLconst |
| OpPPC64RLWINM |
| OpPPC64RLWNM |
| OpPPC64RLWMI |
| OpPPC64CNTLZD |
| OpPPC64CNTLZW |
| OpPPC64CNTTZD |
| OpPPC64CNTTZW |
| OpPPC64POPCNTD |
| OpPPC64POPCNTW |
| OpPPC64POPCNTB |
| OpPPC64FDIV |
| OpPPC64FDIVS |
| OpPPC64DIVD |
| OpPPC64DIVW |
| OpPPC64DIVDU |
| OpPPC64DIVWU |
| OpPPC64MODUD |
| OpPPC64MODSD |
| OpPPC64MODUW |
| OpPPC64MODSW |
| OpPPC64FCTIDZ |
| OpPPC64FCTIWZ |
| OpPPC64FCFID |
| OpPPC64FCFIDS |
| OpPPC64FRSP |
| OpPPC64MFVSRD |
| OpPPC64MTVSRD |
| OpPPC64AND |
| OpPPC64ANDN |
| OpPPC64ANDCC |
| OpPPC64OR |
| OpPPC64ORN |
| OpPPC64ORCC |
| OpPPC64NOR |
| OpPPC64XOR |
| OpPPC64XORCC |
| OpPPC64EQV |
| OpPPC64NEG |
| OpPPC64FNEG |
| OpPPC64FSQRT |
| OpPPC64FSQRTS |
| OpPPC64FFLOOR |
| OpPPC64FCEIL |
| OpPPC64FTRUNC |
| OpPPC64FROUND |
| OpPPC64FABS |
| OpPPC64FNABS |
| OpPPC64FCPSGN |
| OpPPC64ORconst |
| OpPPC64XORconst |
| OpPPC64ANDCCconst |
| OpPPC64MOVBreg |
| OpPPC64MOVBZreg |
| OpPPC64MOVHreg |
| OpPPC64MOVHZreg |
| OpPPC64MOVWreg |
| OpPPC64MOVWZreg |
| OpPPC64MOVBZload |
| OpPPC64MOVHload |
| OpPPC64MOVHZload |
| OpPPC64MOVWload |
| OpPPC64MOVWZload |
| OpPPC64MOVDload |
| OpPPC64MOVDBRload |
| OpPPC64MOVWBRload |
| OpPPC64MOVHBRload |
| OpPPC64MOVBZloadidx |
| OpPPC64MOVHloadidx |
| OpPPC64MOVHZloadidx |
| OpPPC64MOVWloadidx |
| OpPPC64MOVWZloadidx |
| OpPPC64MOVDloadidx |
| OpPPC64MOVHBRloadidx |
| OpPPC64MOVWBRloadidx |
| OpPPC64MOVDBRloadidx |
| OpPPC64FMOVDloadidx |
| OpPPC64FMOVSloadidx |
| OpPPC64DCBT |
| OpPPC64MOVDBRstore |
| OpPPC64MOVWBRstore |
| OpPPC64MOVHBRstore |
| OpPPC64FMOVDload |
| OpPPC64FMOVSload |
| OpPPC64MOVBstore |
| OpPPC64MOVHstore |
| OpPPC64MOVWstore |
| OpPPC64MOVDstore |
| OpPPC64FMOVDstore |
| OpPPC64FMOVSstore |
| OpPPC64MOVBstoreidx |
| OpPPC64MOVHstoreidx |
| OpPPC64MOVWstoreidx |
| OpPPC64MOVDstoreidx |
| OpPPC64FMOVDstoreidx |
| OpPPC64FMOVSstoreidx |
| OpPPC64MOVHBRstoreidx |
| OpPPC64MOVWBRstoreidx |
| OpPPC64MOVDBRstoreidx |
| OpPPC64MOVBstorezero |
| OpPPC64MOVHstorezero |
| OpPPC64MOVWstorezero |
| OpPPC64MOVDstorezero |
| OpPPC64MOVDaddr |
| OpPPC64MOVDconst |
| OpPPC64FMOVDconst |
| OpPPC64FMOVSconst |
| OpPPC64FCMPU |
| OpPPC64CMP |
| OpPPC64CMPU |
| OpPPC64CMPW |
| OpPPC64CMPWU |
| OpPPC64CMPconst |
| OpPPC64CMPUconst |
| OpPPC64CMPWconst |
| OpPPC64CMPWUconst |
| OpPPC64ISEL |
| OpPPC64ISELB |
| OpPPC64ISELZ |
| OpPPC64Equal |
| OpPPC64NotEqual |
| OpPPC64LessThan |
| OpPPC64FLessThan |
| OpPPC64LessEqual |
| OpPPC64FLessEqual |
| OpPPC64GreaterThan |
| OpPPC64FGreaterThan |
| OpPPC64GreaterEqual |
| OpPPC64FGreaterEqual |
| OpPPC64LoweredGetClosurePtr |
| OpPPC64LoweredGetCallerSP |
| OpPPC64LoweredGetCallerPC |
| OpPPC64LoweredNilCheck |
| OpPPC64LoweredRound32F |
| OpPPC64LoweredRound64F |
| OpPPC64CALLstatic |
| OpPPC64CALLtail |
| OpPPC64CALLclosure |
| OpPPC64CALLinter |
| OpPPC64LoweredZero |
| OpPPC64LoweredZeroShort |
| OpPPC64LoweredQuadZeroShort |
| OpPPC64LoweredQuadZero |
| OpPPC64LoweredMove |
| OpPPC64LoweredMoveShort |
| OpPPC64LoweredQuadMove |
| OpPPC64LoweredQuadMoveShort |
| OpPPC64LoweredAtomicStore8 |
| OpPPC64LoweredAtomicStore32 |
| OpPPC64LoweredAtomicStore64 |
| OpPPC64LoweredAtomicLoad8 |
| OpPPC64LoweredAtomicLoad32 |
| OpPPC64LoweredAtomicLoad64 |
| OpPPC64LoweredAtomicLoadPtr |
| OpPPC64LoweredAtomicAdd32 |
| OpPPC64LoweredAtomicAdd64 |
| OpPPC64LoweredAtomicExchange32 |
| OpPPC64LoweredAtomicExchange64 |
| OpPPC64LoweredAtomicCas64 |
| OpPPC64LoweredAtomicCas32 |
| OpPPC64LoweredAtomicAnd8 |
| OpPPC64LoweredAtomicAnd32 |
| OpPPC64LoweredAtomicOr8 |
| OpPPC64LoweredAtomicOr32 |
| OpPPC64LoweredWB |
| OpPPC64LoweredPubBarrier |
| OpPPC64LoweredPanicBoundsA |
| OpPPC64LoweredPanicBoundsB |
| OpPPC64LoweredPanicBoundsC |
| OpPPC64InvertFlags |
| OpPPC64FlagEQ |
| OpPPC64FlagLT |
| OpPPC64FlagGT |
| |
| OpRISCV64ADD |
| OpRISCV64ADDI |
| OpRISCV64ADDIW |
| OpRISCV64NEG |
| OpRISCV64NEGW |
| OpRISCV64SUB |
| OpRISCV64SUBW |
| OpRISCV64MUL |
| OpRISCV64MULW |
| OpRISCV64MULH |
| OpRISCV64MULHU |
| OpRISCV64LoweredMuluhilo |
| OpRISCV64LoweredMuluover |
| OpRISCV64DIV |
| OpRISCV64DIVU |
| OpRISCV64DIVW |
| OpRISCV64DIVUW |
| OpRISCV64REM |
| OpRISCV64REMU |
| OpRISCV64REMW |
| OpRISCV64REMUW |
| OpRISCV64MOVaddr |
| OpRISCV64MOVDconst |
| OpRISCV64MOVBload |
| OpRISCV64MOVHload |
| OpRISCV64MOVWload |
| OpRISCV64MOVDload |
| OpRISCV64MOVBUload |
| OpRISCV64MOVHUload |
| OpRISCV64MOVWUload |
| OpRISCV64MOVBstore |
| OpRISCV64MOVHstore |
| OpRISCV64MOVWstore |
| OpRISCV64MOVDstore |
| OpRISCV64MOVBstorezero |
| OpRISCV64MOVHstorezero |
| OpRISCV64MOVWstorezero |
| OpRISCV64MOVDstorezero |
| OpRISCV64MOVBreg |
| OpRISCV64MOVHreg |
| OpRISCV64MOVWreg |
| OpRISCV64MOVDreg |
| OpRISCV64MOVBUreg |
| OpRISCV64MOVHUreg |
| OpRISCV64MOVWUreg |
| OpRISCV64MOVDnop |
| OpRISCV64SLL |
| OpRISCV64SRA |
| OpRISCV64SRL |
| OpRISCV64SLLI |
| OpRISCV64SRAI |
| OpRISCV64SRLI |
| OpRISCV64XOR |
| OpRISCV64XORI |
| OpRISCV64OR |
| OpRISCV64ORI |
| OpRISCV64AND |
| OpRISCV64ANDI |
| OpRISCV64NOT |
| OpRISCV64SEQZ |
| OpRISCV64SNEZ |
| OpRISCV64SLT |
| OpRISCV64SLTI |
| OpRISCV64SLTU |
| OpRISCV64SLTIU |
| OpRISCV64MOVconvert |
| OpRISCV64CALLstatic |
| OpRISCV64CALLtail |
| OpRISCV64CALLclosure |
| OpRISCV64CALLinter |
| OpRISCV64DUFFZERO |
| OpRISCV64DUFFCOPY |
| OpRISCV64LoweredZero |
| OpRISCV64LoweredMove |
| OpRISCV64LoweredAtomicLoad8 |
| OpRISCV64LoweredAtomicLoad32 |
| OpRISCV64LoweredAtomicLoad64 |
| OpRISCV64LoweredAtomicStore8 |
| OpRISCV64LoweredAtomicStore32 |
| OpRISCV64LoweredAtomicStore64 |
| OpRISCV64LoweredAtomicExchange32 |
| OpRISCV64LoweredAtomicExchange64 |
| OpRISCV64LoweredAtomicAdd32 |
| OpRISCV64LoweredAtomicAdd64 |
| OpRISCV64LoweredAtomicCas32 |
| OpRISCV64LoweredAtomicCas64 |
| OpRISCV64LoweredAtomicAnd32 |
| OpRISCV64LoweredAtomicOr32 |
| OpRISCV64LoweredNilCheck |
| OpRISCV64LoweredGetClosurePtr |
| OpRISCV64LoweredGetCallerSP |
| OpRISCV64LoweredGetCallerPC |
| OpRISCV64LoweredWB |
| OpRISCV64LoweredPanicBoundsA |
| OpRISCV64LoweredPanicBoundsB |
| OpRISCV64LoweredPanicBoundsC |
| OpRISCV64FADDS |
| OpRISCV64FSUBS |
| OpRISCV64FMULS |
| OpRISCV64FDIVS |
| OpRISCV64FSQRTS |
| OpRISCV64FNEGS |
| OpRISCV64FMVSX |
| OpRISCV64FCVTSW |
| OpRISCV64FCVTSL |
| OpRISCV64FCVTWS |
| OpRISCV64FCVTLS |
| OpRISCV64FMOVWload |
| OpRISCV64FMOVWstore |
| OpRISCV64FEQS |
| OpRISCV64FNES |
| OpRISCV64FLTS |
| OpRISCV64FLES |
| OpRISCV64FADDD |
| OpRISCV64FSUBD |
| OpRISCV64FMULD |
| OpRISCV64FDIVD |
| OpRISCV64FMADDD |
| OpRISCV64FMSUBD |
| OpRISCV64FNMADDD |
| OpRISCV64FNMSUBD |
| OpRISCV64FSQRTD |
| OpRISCV64FNEGD |
| OpRISCV64FABSD |
| OpRISCV64FSGNJD |
| OpRISCV64FMVDX |
| OpRISCV64FCVTDW |
| OpRISCV64FCVTDL |
| OpRISCV64FCVTWD |
| OpRISCV64FCVTLD |
| OpRISCV64FCVTDS |
| OpRISCV64FCVTSD |
| OpRISCV64FMOVDload |
| OpRISCV64FMOVDstore |
| OpRISCV64FEQD |
| OpRISCV64FNED |
| OpRISCV64FLTD |
| OpRISCV64FLED |
| |
| OpS390XFADDS |
| OpS390XFADD |
| OpS390XFSUBS |
| OpS390XFSUB |
| OpS390XFMULS |
| OpS390XFMUL |
| OpS390XFDIVS |
| OpS390XFDIV |
| OpS390XFNEGS |
| OpS390XFNEG |
| OpS390XFMADDS |
| OpS390XFMADD |
| OpS390XFMSUBS |
| OpS390XFMSUB |
| OpS390XLPDFR |
| OpS390XLNDFR |
| OpS390XCPSDR |
| OpS390XFIDBR |
| OpS390XFMOVSload |
| OpS390XFMOVDload |
| OpS390XFMOVSconst |
| OpS390XFMOVDconst |
| OpS390XFMOVSloadidx |
| OpS390XFMOVDloadidx |
| OpS390XFMOVSstore |
| OpS390XFMOVDstore |
| OpS390XFMOVSstoreidx |
| OpS390XFMOVDstoreidx |
| OpS390XADD |
| OpS390XADDW |
| OpS390XADDconst |
| OpS390XADDWconst |
| OpS390XADDload |
| OpS390XADDWload |
| OpS390XSUB |
| OpS390XSUBW |
| OpS390XSUBconst |
| OpS390XSUBWconst |
| OpS390XSUBload |
| OpS390XSUBWload |
| OpS390XMULLD |
| OpS390XMULLW |
| OpS390XMULLDconst |
| OpS390XMULLWconst |
| OpS390XMULLDload |
| OpS390XMULLWload |
| OpS390XMULHD |
| OpS390XMULHDU |
| OpS390XDIVD |
| OpS390XDIVW |
| OpS390XDIVDU |
| OpS390XDIVWU |
| OpS390XMODD |
| OpS390XMODW |
| OpS390XMODDU |
| OpS390XMODWU |
| OpS390XAND |
| OpS390XANDW |
| OpS390XANDconst |
| OpS390XANDWconst |
| OpS390XANDload |
| OpS390XANDWload |
| OpS390XOR |
| OpS390XORW |
| OpS390XORconst |
| OpS390XORWconst |
| OpS390XORload |
| OpS390XORWload |
| OpS390XXOR |
| OpS390XXORW |
| OpS390XXORconst |
| OpS390XXORWconst |
| OpS390XXORload |
| OpS390XXORWload |
| OpS390XADDC |
| OpS390XADDCconst |
| OpS390XADDE |
| OpS390XSUBC |
| OpS390XSUBE |
| OpS390XCMP |
| OpS390XCMPW |
| OpS390XCMPU |
| OpS390XCMPWU |
| OpS390XCMPconst |
| OpS390XCMPWconst |
| OpS390XCMPUconst |
| OpS390XCMPWUconst |
| OpS390XFCMPS |
| OpS390XFCMP |
| OpS390XLTDBR |
| OpS390XLTEBR |
| OpS390XSLD |
| OpS390XSLW |
| OpS390XSLDconst |
| OpS390XSLWconst |
| OpS390XSRD |
| OpS390XSRW |
| OpS390XSRDconst |
| OpS390XSRWconst |
| OpS390XSRAD |
| OpS390XSRAW |
| OpS390XSRADconst |
| OpS390XSRAWconst |
| OpS390XRLLG |
| OpS390XRLL |
| OpS390XRLLconst |
| OpS390XRXSBG |
| OpS390XRISBGZ |
| OpS390XNEG |
| OpS390XNEGW |
| OpS390XNOT |
| OpS390XNOTW |
| OpS390XFSQRT |
| OpS390XFSQRTS |
| OpS390XLOCGR |
| OpS390XMOVBreg |
| OpS390XMOVBZreg |
| OpS390XMOVHreg |
| OpS390XMOVHZreg |
| OpS390XMOVWreg |
| OpS390XMOVWZreg |
| OpS390XMOVDconst |
| OpS390XLDGR |
| OpS390XLGDR |
| OpS390XCFDBRA |
| OpS390XCGDBRA |
| OpS390XCFEBRA |
| OpS390XCGEBRA |
| OpS390XCEFBRA |
| OpS390XCDFBRA |
| OpS390XCEGBRA |
| OpS390XCDGBRA |
| OpS390XCLFEBR |
| OpS390XCLFDBR |
| OpS390XCLGEBR |
| OpS390XCLGDBR |
| OpS390XCELFBR |
| OpS390XCDLFBR |
| OpS390XCELGBR |
| OpS390XCDLGBR |
| OpS390XLEDBR |
| OpS390XLDEBR |
| OpS390XMOVDaddr |
| OpS390XMOVDaddridx |
| OpS390XMOVBZload |
| OpS390XMOVBload |
| OpS390XMOVHZload |
| OpS390XMOVHload |
| OpS390XMOVWZload |
| OpS390XMOVWload |
| OpS390XMOVDload |
| OpS390XMOVWBR |
| OpS390XMOVDBR |
| OpS390XMOVHBRload |
| OpS390XMOVWBRload |
| OpS390XMOVDBRload |
| OpS390XMOVBstore |
| OpS390XMOVHstore |
| OpS390XMOVWstore |
| OpS390XMOVDstore |
| OpS390XMOVHBRstore |
| OpS390XMOVWBRstore |
| OpS390XMOVDBRstore |
| OpS390XMVC |
| OpS390XMOVBZloadidx |
| OpS390XMOVBloadidx |
| OpS390XMOVHZloadidx |
| OpS390XMOVHloadidx |
| OpS390XMOVWZloadidx |
| OpS390XMOVWloadidx |
| OpS390XMOVDloadidx |
| OpS390XMOVHBRloadidx |
| OpS390XMOVWBRloadidx |
| OpS390XMOVDBRloadidx |
| OpS390XMOVBstoreidx |
| OpS390XMOVHstoreidx |
| OpS390XMOVWstoreidx |
| OpS390XMOVDstoreidx |
| OpS390XMOVHBRstoreidx |
| OpS390XMOVWBRstoreidx |
| OpS390XMOVDBRstoreidx |
| OpS390XMOVBstoreconst |
| OpS390XMOVHstoreconst |
| OpS390XMOVWstoreconst |
| OpS390XMOVDstoreconst |
| OpS390XCLEAR |
| OpS390XCALLstatic |
| OpS390XCALLtail |
| OpS390XCALLclosure |
| OpS390XCALLinter |
| OpS390XInvertFlags |
| OpS390XLoweredGetG |
| OpS390XLoweredGetClosurePtr |
| OpS390XLoweredGetCallerSP |
| OpS390XLoweredGetCallerPC |
| OpS390XLoweredNilCheck |
| OpS390XLoweredRound32F |
| OpS390XLoweredRound64F |
| OpS390XLoweredWB |
| OpS390XLoweredPanicBoundsA |
| OpS390XLoweredPanicBoundsB |
| OpS390XLoweredPanicBoundsC |
| OpS390XFlagEQ |
| OpS390XFlagLT |
| OpS390XFlagGT |
| OpS390XFlagOV |
| OpS390XSYNC |
| OpS390XMOVBZatomicload |
| OpS390XMOVWZatomicload |
| OpS390XMOVDatomicload |
| OpS390XMOVBatomicstore |
| OpS390XMOVWatomicstore |
| OpS390XMOVDatomicstore |
| OpS390XLAA |
| OpS390XLAAG |
| OpS390XAddTupleFirst32 |
| OpS390XAddTupleFirst64 |
| OpS390XLAN |
| OpS390XLANfloor |
| OpS390XLAO |
| OpS390XLAOfloor |
| OpS390XLoweredAtomicCas32 |
| OpS390XLoweredAtomicCas64 |
| OpS390XLoweredAtomicExchange32 |
| OpS390XLoweredAtomicExchange64 |
| OpS390XFLOGR |
| OpS390XPOPCNT |
| OpS390XMLGR |
| OpS390XSumBytes2 |
| OpS390XSumBytes4 |
| OpS390XSumBytes8 |
| OpS390XSTMG2 |
| OpS390XSTMG3 |
| OpS390XSTMG4 |
| OpS390XSTM2 |
| OpS390XSTM3 |
| OpS390XSTM4 |
| OpS390XLoweredMove |
| OpS390XLoweredZero |
| |
| OpWasmLoweredStaticCall |
| OpWasmLoweredTailCall |
| OpWasmLoweredClosureCall |
| OpWasmLoweredInterCall |
| OpWasmLoweredAddr |
| OpWasmLoweredMove |
| OpWasmLoweredZero |
| OpWasmLoweredGetClosurePtr |
| OpWasmLoweredGetCallerPC |
| OpWasmLoweredGetCallerSP |
| OpWasmLoweredNilCheck |
| OpWasmLoweredWB |
| OpWasmLoweredConvert |
| OpWasmSelect |
| OpWasmI64Load8U |
| OpWasmI64Load8S |
| OpWasmI64Load16U |
| OpWasmI64Load16S |
| OpWasmI64Load32U |
| OpWasmI64Load32S |
| OpWasmI64Load |
| OpWasmI64Store8 |
| OpWasmI64Store16 |
| OpWasmI64Store32 |
| OpWasmI64Store |
| OpWasmF32Load |
| OpWasmF64Load |
| OpWasmF32Store |
| OpWasmF64Store |
| OpWasmI64Const |
| OpWasmF32Const |
| OpWasmF64Const |
| OpWasmI64Eqz |
| OpWasmI64Eq |
| OpWasmI64Ne |
| OpWasmI64LtS |
| OpWasmI64LtU |
| OpWasmI64GtS |
| OpWasmI64GtU |
| OpWasmI64LeS |
| OpWasmI64LeU |
| OpWasmI64GeS |
| OpWasmI64GeU |
| OpWasmF32Eq |
| OpWasmF32Ne |
| OpWasmF32Lt |
| OpWasmF32Gt |
| OpWasmF32Le |
| OpWasmF32Ge |
| OpWasmF64Eq |
| OpWasmF64Ne |
| OpWasmF64Lt |
| OpWasmF64Gt |
| OpWasmF64Le |
| OpWasmF64Ge |
| OpWasmI64Add |
| OpWasmI64AddConst |
| OpWasmI64Sub |
| OpWasmI64Mul |
| OpWasmI64DivS |
| OpWasmI64DivU |
| OpWasmI64RemS |
| OpWasmI64RemU |
| OpWasmI64And |
| OpWasmI64Or |
| OpWasmI64Xor |
| OpWasmI64Shl |
| OpWasmI64ShrS |
| OpWasmI64ShrU |
| OpWasmF32Neg |
| OpWasmF32Add |
| OpWasmF32Sub |
| OpWasmF32Mul |
| OpWasmF32Div |
| OpWasmF64Neg |
| OpWasmF64Add |
| OpWasmF64Sub |
| OpWasmF64Mul |
| OpWasmF64Div |
| OpWasmI64TruncSatF64S |
| OpWasmI64TruncSatF64U |
| OpWasmI64TruncSatF32S |
| OpWasmI64TruncSatF32U |
| OpWasmF32ConvertI64S |
| OpWasmF32ConvertI64U |
| OpWasmF64ConvertI64S |
| OpWasmF64ConvertI64U |
| OpWasmF32DemoteF64 |
| OpWasmF64PromoteF32 |
| OpWasmI64Extend8S |
| OpWasmI64Extend16S |
| OpWasmI64Extend32S |
| OpWasmF32Sqrt |
| OpWasmF32Trunc |
| OpWasmF32Ceil |
| OpWasmF32Floor |
| OpWasmF32Nearest |
| OpWasmF32Abs |
| OpWasmF32Copysign |
| OpWasmF64Sqrt |
| OpWasmF64Trunc |
| OpWasmF64Ceil |
| OpWasmF64Floor |
| OpWasmF64Nearest |
| OpWasmF64Abs |
| OpWasmF64Copysign |
| OpWasmI64Ctz |
| OpWasmI64Clz |
| OpWasmI32Rotl |
| OpWasmI64Rotl |
| OpWasmI64Popcnt |
| |
| OpAdd8 |
| OpAdd16 |
| OpAdd32 |
| OpAdd64 |
| OpAddPtr |
| OpAdd32F |
| OpAdd64F |
| OpSub8 |
| OpSub16 |
| OpSub32 |
| OpSub64 |
| OpSubPtr |
| OpSub32F |
| OpSub64F |
| OpMul8 |
| OpMul16 |
| OpMul32 |
| OpMul64 |
| OpMul32F |
| OpMul64F |
| OpDiv32F |
| OpDiv64F |
| OpHmul32 |
| OpHmul32u |
| OpHmul64 |
| OpHmul64u |
| OpMul32uhilo |
| OpMul64uhilo |
| OpMul32uover |
| OpMul64uover |
| OpAvg32u |
| OpAvg64u |
| OpDiv8 |
| OpDiv8u |
| OpDiv16 |
| OpDiv16u |
| OpDiv32 |
| OpDiv32u |
| OpDiv64 |
| OpDiv64u |
| OpDiv128u |
| OpMod8 |
| OpMod8u |
| OpMod16 |
| OpMod16u |
| OpMod32 |
| OpMod32u |
| OpMod64 |
| OpMod64u |
| OpAnd8 |
| OpAnd16 |
| OpAnd32 |
| OpAnd64 |
| OpOr8 |
| OpOr16 |
| OpOr32 |
| OpOr64 |
| OpXor8 |
| OpXor16 |
| OpXor32 |
| OpXor64 |
| OpLsh8x8 |
| OpLsh8x16 |
| OpLsh8x32 |
| OpLsh8x64 |
| OpLsh16x8 |
| OpLsh16x16 |
| OpLsh16x32 |
| OpLsh16x64 |
| OpLsh32x8 |
| OpLsh32x16 |
| OpLsh32x32 |
| OpLsh32x64 |
| OpLsh64x8 |
| OpLsh64x16 |
| OpLsh64x32 |
| OpLsh64x64 |
| OpRsh8x8 |
| OpRsh8x16 |
| OpRsh8x32 |
| OpRsh8x64 |
| OpRsh16x8 |
| OpRsh16x16 |
| OpRsh16x32 |
| OpRsh16x64 |
| OpRsh32x8 |
| OpRsh32x16 |
| OpRsh32x32 |
| OpRsh32x64 |
| OpRsh64x8 |
| OpRsh64x16 |
| OpRsh64x32 |
| OpRsh64x64 |
| OpRsh8Ux8 |
| OpRsh8Ux16 |
| OpRsh8Ux32 |
| OpRsh8Ux64 |
| OpRsh16Ux8 |
| OpRsh16Ux16 |
| OpRsh16Ux32 |
| OpRsh16Ux64 |
| OpRsh32Ux8 |
| OpRsh32Ux16 |
| OpRsh32Ux32 |
| OpRsh32Ux64 |
| OpRsh64Ux8 |
| OpRsh64Ux16 |
| OpRsh64Ux32 |
| OpRsh64Ux64 |
| OpEq8 |
| OpEq16 |
| OpEq32 |
| OpEq64 |
| OpEqPtr |
| OpEqInter |
| OpEqSlice |
| OpEq32F |
| OpEq64F |
| OpNeq8 |
| OpNeq16 |
| OpNeq32 |
| OpNeq64 |
| OpNeqPtr |
| OpNeqInter |
| OpNeqSlice |
| OpNeq32F |
| OpNeq64F |
| OpLess8 |
| OpLess8U |
| OpLess16 |
| OpLess16U |
| OpLess32 |
| OpLess32U |
| OpLess64 |
| OpLess64U |
| OpLess32F |
| OpLess64F |
| OpLeq8 |
| OpLeq8U |
| OpLeq16 |
| OpLeq16U |
| OpLeq32 |
| OpLeq32U |
| OpLeq64 |
| OpLeq64U |
| OpLeq32F |
| OpLeq64F |
| OpCondSelect |
| OpAndB |
| OpOrB |
| OpEqB |
| OpNeqB |
| OpNot |
| OpNeg8 |
| OpNeg16 |
| OpNeg32 |
| OpNeg64 |
| OpNeg32F |
| OpNeg64F |
| OpCom8 |
| OpCom16 |
| OpCom32 |
| OpCom64 |
| OpCtz8 |
| OpCtz16 |
| OpCtz32 |
| OpCtz64 |
| OpCtz8NonZero |
| OpCtz16NonZero |
| OpCtz32NonZero |
| OpCtz64NonZero |
| OpBitLen8 |
| OpBitLen16 |
| OpBitLen32 |
| OpBitLen64 |
| OpBswap32 |
| OpBswap64 |
| OpBitRev8 |
| OpBitRev16 |
| OpBitRev32 |
| OpBitRev64 |
| OpPopCount8 |
| OpPopCount16 |
| OpPopCount32 |
| OpPopCount64 |
| OpRotateLeft64 |
| OpRotateLeft32 |
| OpRotateLeft16 |
| OpRotateLeft8 |
| OpSqrt |
| OpSqrt32 |
| OpFloor |
| OpCeil |
| OpTrunc |
| OpRound |
| OpRoundToEven |
| OpAbs |
| OpCopysign |
| OpFMA |
| OpPhi |
| OpCopy |
| OpConvert |
| OpConstBool |
| OpConstString |
| OpConstNil |
| OpConst8 |
| OpConst16 |
| OpConst32 |
| OpConst64 |
| OpConst32F |
| OpConst64F |
| OpConstInterface |
| OpConstSlice |
| OpInitMem |
| OpArg |
| OpArgIntReg |
| OpArgFloatReg |
| OpAddr |
| OpLocalAddr |
| OpSP |
| OpSB |
| OpLoad |
| OpDereference |
| OpStore |
| OpMove |
| OpZero |
| OpStoreWB |
| OpMoveWB |
| OpZeroWB |
| OpWB |
| OpHasCPUFeature |
| OpPanicBounds |
| OpPanicExtend |
| OpClosureCall |
| OpStaticCall |
| OpInterCall |
| OpTailCall |
| OpClosureLECall |
| OpStaticLECall |
| OpInterLECall |
| OpTailLECall |
| OpSignExt8to16 |
| OpSignExt8to32 |
| OpSignExt8to64 |
| OpSignExt16to32 |
| OpSignExt16to64 |
| OpSignExt32to64 |
| OpZeroExt8to16 |
| OpZeroExt8to32 |
| OpZeroExt8to64 |
| OpZeroExt16to32 |
| OpZeroExt16to64 |
| OpZeroExt32to64 |
| OpTrunc16to8 |
| OpTrunc32to8 |
| OpTrunc32to16 |
| OpTrunc64to8 |
| OpTrunc64to16 |
| OpTrunc64to32 |
| OpCvt32to32F |
| OpCvt32to64F |
| OpCvt64to32F |
| OpCvt64to64F |
| OpCvt32Fto32 |
| OpCvt32Fto64 |
| OpCvt64Fto32 |
| OpCvt64Fto64 |
| OpCvt32Fto64F |
| OpCvt64Fto32F |
| OpCvtBoolToUint8 |
| OpRound32F |
| OpRound64F |
| OpIsNonNil |
| OpIsInBounds |
| OpIsSliceInBounds |
| OpNilCheck |
| OpGetG |
| OpGetClosurePtr |
| OpGetCallerPC |
| OpGetCallerSP |
| OpPtrIndex |
| OpOffPtr |
| OpSliceMake |
| OpSlicePtr |
| OpSliceLen |
| OpSliceCap |
| OpSlicePtrUnchecked |
| OpComplexMake |
| OpComplexReal |
| OpComplexImag |
| OpStringMake |
| OpStringPtr |
| OpStringLen |
| OpIMake |
| OpITab |
| OpIData |
| OpStructMake0 |
| OpStructMake1 |
| OpStructMake2 |
| OpStructMake3 |
| OpStructMake4 |
| OpStructSelect |
| OpArrayMake0 |
| OpArrayMake1 |
| OpArraySelect |
| OpStoreReg |
| OpLoadReg |
| OpFwdRef |
| OpUnknown |
| OpVarDef |
| OpVarLive |
| OpKeepAlive |
| OpInlMark |
| OpInt64Make |
| OpInt64Hi |
| OpInt64Lo |
| OpAdd32carry |
| OpAdd32withcarry |
| OpSub32carry |
| OpSub32withcarry |
| OpAdd64carry |
| OpSub64borrow |
| OpSignmask |
| OpZeromask |
| OpSlicemask |
| OpSpectreIndex |
| OpSpectreSliceIndex |
| OpCvt32Uto32F |
| OpCvt32Uto64F |
| OpCvt32Fto32U |
| OpCvt64Fto32U |
| OpCvt64Uto32F |
| OpCvt64Uto64F |
| OpCvt32Fto64U |
| OpCvt64Fto64U |
| OpSelect0 |
| OpSelect1 |
| OpSelectN |
| OpSelectNAddr |
| OpMakeResult |
| OpAtomicLoad8 |
| OpAtomicLoad32 |
| OpAtomicLoad64 |
| OpAtomicLoadPtr |
| OpAtomicLoadAcq32 |
| OpAtomicLoadAcq64 |
| OpAtomicStore8 |
| OpAtomicStore32 |
| OpAtomicStore64 |
| OpAtomicStorePtrNoWB |
| OpAtomicStoreRel32 |
| OpAtomicStoreRel64 |
| OpAtomicExchange32 |
| OpAtomicExchange64 |
| OpAtomicAdd32 |
| OpAtomicAdd64 |
| OpAtomicCompareAndSwap32 |
| OpAtomicCompareAndSwap64 |
| OpAtomicCompareAndSwapRel32 |
| OpAtomicAnd8 |
| OpAtomicAnd32 |
| OpAtomicOr8 |
| OpAtomicOr32 |
| OpAtomicAdd32Variant |
| OpAtomicAdd64Variant |
| OpAtomicExchange32Variant |
| OpAtomicExchange64Variant |
| OpAtomicCompareAndSwap32Variant |
| OpAtomicCompareAndSwap64Variant |
| OpAtomicAnd8Variant |
| OpAtomicAnd32Variant |
| OpAtomicOr8Variant |
| OpAtomicOr32Variant |
| OpPubBarrier |
| OpClobber |
| OpClobberReg |
| OpPrefetchCache |
| OpPrefetchCacheStreamed |
| ) |
| |
| var opcodeTable = [...]opInfo{ |
| {name: "OpInvalid"}, |
| |
| { |
| name: "ADDSS", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSD", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSS", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSD", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MULSS", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AMULSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MULSD", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AMULSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSS", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ADIVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSD", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ADIVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSconst", |
| auxType: auxFloat32, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstoreidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MULSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AMULSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MULSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AMULSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "ADDL", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 239}, // AX CX DX BX BP SI DI |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADDLcarry", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstcarry", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADCL", |
| argLen: 3, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AADCL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADCLconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AADCL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBLcarry", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBLconstcarry", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SBBL", |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASBBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SBBLconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASBBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MULL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MULLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AIMUL3L, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MULLU", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "HMULL", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "HMULLU", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "MULLQU", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| {1, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "AVGLU", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "DIVL", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "DIVW", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "DIVLU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "DIVWU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "MODL", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "MODW", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "MODLU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "MODWU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 251}, // AX CX BX SP BP SI DI |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "ANDL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ORL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ORLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "XORL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "XORLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPL", |
| argLen: 2, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPW", |
| argLen: 2, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPB", |
| argLen: 2, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CMPLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "UCOMISS", |
| argLen: 2, |
| asm: x86.AUCOMISS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "UCOMISD", |
| argLen: 2, |
| asm: x86.AUCOMISD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "TESTL", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "TESTW", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "TESTB", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "TESTLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ATESTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "TESTWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| asm: x86.ATESTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "TESTBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ATESTB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHLL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHLLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SHRBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SARBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ROLBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADDLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MULLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ANDLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ORLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "XORLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ADDLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SUBLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MULLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ANDLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "ORLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "XORLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {1, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "NEGL", |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ANEGL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "NOTL", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ANOTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "BSFL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSFL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "BSFW", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSFW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "BSRL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "BSRW", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "BSWAPL", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ABSWAPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SQRTSD", |
| argLen: 1, |
| asm: x86.ASQRTSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SQRTSS", |
| argLen: 1, |
| asm: x86.ASQRTSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "SBBLcarrymask", |
| argLen: 1, |
| asm: x86.ASBBL, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETEQ", |
| argLen: 1, |
| asm: x86.ASETEQ, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETNE", |
| argLen: 1, |
| asm: x86.ASETNE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETL", |
| argLen: 1, |
| asm: x86.ASETLT, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETLE", |
| argLen: 1, |
| asm: x86.ASETLE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETG", |
| argLen: 1, |
| asm: x86.ASETGT, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETGE", |
| argLen: 1, |
| asm: x86.ASETGE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETB", |
| argLen: 1, |
| asm: x86.ASETCS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETBE", |
| argLen: 1, |
| asm: x86.ASETLS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETA", |
| argLen: 1, |
| asm: x86.ASETHI, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETAE", |
| argLen: 1, |
| asm: x86.ASETCC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETO", |
| argLen: 1, |
| asm: x86.ASETOS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETEQF", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ASETEQ, |
| reg: regInfo{ |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 238}, // CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETNEF", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ASETNE, |
| reg: regInfo{ |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 238}, // CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETORD", |
| argLen: 1, |
| asm: x86.ASETPC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETNAN", |
| argLen: 1, |
| asm: x86.ASETPS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETGF", |
| argLen: 1, |
| asm: x86.ASETHI, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "SETGEF", |
| argLen: 1, |
| asm: x86.ASETCC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBLSX", |
| argLen: 1, |
| asm: x86.AMOVBLSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBLZX", |
| argLen: 1, |
| asm: x86.AMOVBLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWLSX", |
| argLen: 1, |
| asm: x86.AMOVWLSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWLZX", |
| argLen: 1, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVLconst", |
| auxType: auxInt32, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSD2SL", |
| argLen: 1, |
| asm: x86.ACVTTSD2SL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSS2SL", |
| argLen: 1, |
| asm: x86.ACVTTSS2SL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "CVTSL2SS", |
| argLen: 1, |
| asm: x86.ACVTSL2SS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSL2SD", |
| argLen: 1, |
| asm: x86.ACVTSL2SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSD2SS", |
| argLen: 1, |
| asm: x86.ACVTSD2SS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSS2SD", |
| argLen: 1, |
| asm: x86.ACVTSS2SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "PXOR", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.APXOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LEAL1", |
| auxType: auxSymOff, |
| argLen: 2, |
| commutative: true, |
| symEffect: SymAddr, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LEAL2", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LEAL4", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LEAL8", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBLSXload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBLSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWLSXload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWLSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVLload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx2", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVLloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVLloadidx4", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx2", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {2, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconstidx2", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconstidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 255}, // AX CX DX BX SP BP SI DI |
| {0, 65791}, // AX CX DX BX SP BP SI DI SB |
| }, |
| }, |
| }, |
| { |
| name: "DUFFZERO", |
| auxType: auxInt64, |
| argLen: 3, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 1}, // AX |
| }, |
| clobbers: 130, // CX DI |
| }, |
| }, |
| { |
| name: "REPSTOSL", |
| argLen: 4, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 2}, // CX |
| {2, 1}, // AX |
| }, |
| clobbers: 130, // CX DI |
| }, |
| }, |
| { |
| name: "CALLstatic", |
| auxType: auxCallOff, |
| argLen: 1, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| { |
| name: "CALLtail", |
| auxType: auxCallOff, |
| argLen: 1, |
| clobberFlags: true, |
| call: true, |
| tailCall: true, |
| reg: regInfo{ |
| clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| { |
| name: "CALLclosure", |
| auxType: auxCallOff, |
| argLen: 3, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 4}, // DX |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| { |
| name: "CALLinter", |
| auxType: auxCallOff, |
| argLen: 2, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| { |
| name: "DUFFCOPY", |
| auxType: auxInt64, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 64}, // SI |
| }, |
| clobbers: 194, // CX SI DI |
| }, |
| }, |
| { |
| name: "REPMOVSL", |
| argLen: 4, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 64}, // SI |
| {2, 2}, // CX |
| }, |
| clobbers: 194, // CX SI DI |
| }, |
| }, |
| { |
| name: "InvertFlags", |
| argLen: 1, |
| reg: regInfo{}, |
| }, |
| { |
| name: "LoweredGetG", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetClosurePtr", |
| argLen: 0, |
| zeroWidth: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerPC", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerSP", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LoweredNilCheck", |
| argLen: 2, |
| clobberFlags: true, |
| nilCheck: true, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 255}, // AX CX DX BX SP BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "LoweredWB", |
| auxType: auxSym, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymNone, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 1}, // AX |
| }, |
| clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsA", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // DX |
| {1, 8}, // BX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsB", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // CX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsC", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 2}, // CX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendA", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 64}, // SI |
| {1, 4}, // DX |
| {2, 8}, // BX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendB", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 64}, // SI |
| {1, 2}, // CX |
| {2, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendC", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 64}, // SI |
| {1, 1}, // AX |
| {2, 2}, // CX |
| }, |
| }, |
| }, |
| { |
| name: "FlagEQ", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagLT_ULT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagLT_UGT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagGT_UGT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagGT_ULT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "MOVSSconst1", |
| auxType: auxFloat32, |
| argLen: 0, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDconst1", |
| auxType: auxFloat64, |
| argLen: 0, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSconst2", |
| argLen: 1, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDconst2", |
| argLen: 1, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 239}, // AX CX DX BX BP SI DI |
| }, |
| outputs: []outputInfo{ |
| {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 |
| }, |
| }, |
| }, |
| |
| { |
| name: "ADDSS", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSD", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSS", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSD", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSS", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AMULSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSD", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AMULSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSS", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ADIVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSD", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ADIVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSconst", |
| auxType: auxFloat32, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSSstoreidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVSDstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AMULSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AMULSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSSload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSDload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AADDSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AADDSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AADDSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AADDSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASUBSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMULSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMULSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMULSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MULSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMULSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSSloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSS, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSSloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSS, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSDloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSD, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "DIVSDloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| symEffect: SymRead, |
| asm: x86.ADIVSD, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQ", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDL", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULQ", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AIMULQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AIMUL3Q, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.AIMUL3L, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULLU", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "MULQU", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 4, // DX |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "HMULQ", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIMULQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "HMULL", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "HMULQU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AMULQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "HMULLU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "AVGQU", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "DIVQ", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "DIVL", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "DIVW", |
| auxType: auxBool, |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AIDIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "DIVQU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "DIVLU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "DIVWU", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.ADIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "NEGLflags", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ANEGL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQcarry", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADCQ", |
| argLen: 3, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.AADCQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQconstcarry", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADCQconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.AADCQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQborrow", |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SBBQ", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ASBBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQconstborrow", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SBBQconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| asm: x86.ASBBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MULQU2", |
| argLen: 2, |
| commutative: true, |
| clobberFlags: true, |
| asm: x86.AMULQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| {1, 1}, // AX |
| }, |
| }, |
| }, |
| { |
| name: "DIVQU2", |
| argLen: 3, |
| clobberFlags: true, |
| asm: x86.ADIVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // DX |
| {1, 1}, // AX |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 1}, // AX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "ANDQ", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDQconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQ", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORQconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQ", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORL", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORQconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodify", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQ", |
| argLen: 2, |
| asm: x86.ACMPQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPL", |
| argLen: 2, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPW", |
| argLen: 2, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPB", |
| argLen: 2, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ACMPQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBconstload", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWloadidx2", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQconstloadidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPQconstloadidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconstloadidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPLconstloadidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconstloadidx2", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconstloadidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "CMPBconstloadidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.ACMPB, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "UCOMISS", |
| argLen: 2, |
| asm: x86.AUCOMISS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "UCOMISD", |
| argLen: 2, |
| asm: x86.AUCOMISD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "BTL", |
| argLen: 2, |
| asm: x86.ABTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTQ", |
| argLen: 2, |
| asm: x86.ABTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTCL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTCL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTCQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTCQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTRL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTRQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTSL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTSL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTSQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTSQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ABTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ABTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTCLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTCL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTCQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTCQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTRLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTRQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTSLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTSL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BTSQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ABTSQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTQ", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTL", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTW", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTB", |
| argLen: 2, |
| commutative: true, |
| asm: x86.ATESTB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ATESTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: x86.ATESTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTWconst", |
| auxType: auxInt16, |
| argLen: 1, |
| asm: x86.ATESTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TESTBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.ATESTB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRWconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARWconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASARB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRDQ", |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLDQ", |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ASHLQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "RORQ", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ARORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "RORL", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ARORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "RORW", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ARORW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "RORB", |
| argLen: 2, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ARORB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2}, // CX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLQconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLLconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLWconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ROLBconst", |
| auxType: auxInt8, |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.AROLB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AANDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AXORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AADDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.ASUBQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AANDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ORQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XORQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| resultInArg0: true, |
| clobberFlags: true, |
| symEffect: SymRead, |
| asm: x86.AXORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDQmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBQmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDQmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodify", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDQmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDQmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBQmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBQmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDQmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDQmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SUBLmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.ASUBL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodifyidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodifyidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLmodifyidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDQconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDQconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDQconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDQconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORQconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORQconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ADDLconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AADDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AANDL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodifyidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodifyidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "XORLconstmodifyidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymRead | SymWrite, |
| asm: x86.AXORL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "NEGQ", |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ANEGQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "NEGL", |
| argLen: 1, |
| resultInArg0: true, |
| clobberFlags: true, |
| asm: x86.ANEGL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "NOTQ", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ANOTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "NOTL", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ANOTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSFQ", |
| argLen: 1, |
| asm: x86.ABSFQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSFL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSFL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSRQ", |
| argLen: 1, |
| asm: x86.ABSRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSRL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABSRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQEQ", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQNE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQLT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQLT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQGT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQGT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQLE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQLE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQGE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQGE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQLS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQLS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQHI", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQCC", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQCS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLEQ", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLNE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLLT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLLT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLGT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLGT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLLE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLLE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLGE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLGE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLLS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLLS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLHI", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLCC", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLCS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWEQ", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWNE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWLT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWLT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWGT", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWGT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWLE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWLE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWGE", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWGE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWLS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWLS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWHI", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWCC", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWCS", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQEQF", |
| argLen: 3, |
| resultInArg0: true, |
| needIntTemp: true, |
| asm: x86.ACMOVQNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQNEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQGTF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVQGEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVQCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLEQF", |
| argLen: 3, |
| resultInArg0: true, |
| needIntTemp: true, |
| asm: x86.ACMOVLNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLNEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLGTF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVLGEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVLCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWEQF", |
| argLen: 3, |
| resultInArg0: true, |
| needIntTemp: true, |
| asm: x86.ACMOVWNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWNEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWGTF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWGEF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.ACMOVWCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSWAPQ", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ABSWAPQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BSWAPL", |
| argLen: 1, |
| resultInArg0: true, |
| asm: x86.ABSWAPL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "POPCNTQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.APOPCNTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "POPCNTL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.APOPCNTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SQRTSD", |
| argLen: 1, |
| asm: x86.ASQRTSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SQRTSS", |
| argLen: 1, |
| asm: x86.ASQRTSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "ROUNDSD", |
| auxType: auxInt8, |
| argLen: 1, |
| asm: x86.AROUNDSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "VFMADD231SD", |
| argLen: 3, |
| resultInArg0: true, |
| asm: x86.AVFMADD231SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "SBBQcarrymask", |
| argLen: 1, |
| asm: x86.ASBBQ, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SBBLcarrymask", |
| argLen: 1, |
| asm: x86.ASBBL, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETEQ", |
| argLen: 1, |
| asm: x86.ASETEQ, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETNE", |
| argLen: 1, |
| asm: x86.ASETNE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETL", |
| argLen: 1, |
| asm: x86.ASETLT, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETLE", |
| argLen: 1, |
| asm: x86.ASETLE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETG", |
| argLen: 1, |
| asm: x86.ASETGT, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETGE", |
| argLen: 1, |
| asm: x86.ASETGE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETB", |
| argLen: 1, |
| asm: x86.ASETCS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETBE", |
| argLen: 1, |
| asm: x86.ASETLS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETA", |
| argLen: 1, |
| asm: x86.ASETHI, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETAE", |
| argLen: 1, |
| asm: x86.ASETCC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETO", |
| argLen: 1, |
| asm: x86.ASETOS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETEQstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETNEstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETNE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETLstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETLT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETLEstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETLE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETGstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETGT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETGEstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETGE, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETBstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETBEstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETLS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETAstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETHI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETAEstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.ASETCC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SETEQF", |
| argLen: 1, |
| clobberFlags: true, |
| needIntTemp: true, |
| asm: x86.ASETEQ, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETNEF", |
| argLen: 1, |
| clobberFlags: true, |
| needIntTemp: true, |
| asm: x86.ASETNE, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETORD", |
| argLen: 1, |
| asm: x86.ASETPC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETNAN", |
| argLen: 1, |
| asm: x86.ASETPS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETGF", |
| argLen: 1, |
| asm: x86.ASETHI, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SETGEF", |
| argLen: 1, |
| asm: x86.ASETCC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBQSX", |
| argLen: 1, |
| asm: x86.AMOVBQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBQZX", |
| argLen: 1, |
| asm: x86.AMOVBLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWQSX", |
| argLen: 1, |
| asm: x86.AMOVWQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWQZX", |
| argLen: 1, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLQSX", |
| argLen: 1, |
| asm: x86.AMOVLQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLQZX", |
| argLen: 1, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLconst", |
| auxType: auxInt32, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQconst", |
| auxType: auxInt64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: x86.AMOVQ, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSD2SL", |
| argLen: 1, |
| asm: x86.ACVTTSD2SL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSD2SQ", |
| argLen: 1, |
| asm: x86.ACVTTSD2SQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSS2SL", |
| argLen: 1, |
| asm: x86.ACVTTSS2SL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CVTTSS2SQ", |
| argLen: 1, |
| asm: x86.ACVTTSS2SQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSL2SS", |
| argLen: 1, |
| asm: x86.ACVTSL2SS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSL2SD", |
| argLen: 1, |
| asm: x86.ACVTSL2SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSQ2SS", |
| argLen: 1, |
| asm: x86.ACVTSQ2SS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSQ2SD", |
| argLen: 1, |
| asm: x86.ACVTSQ2SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSD2SS", |
| argLen: 1, |
| asm: x86.ACVTSD2SS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "CVTSS2SD", |
| argLen: 1, |
| asm: x86.ACVTSS2SD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQi2f", |
| argLen: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQf2i", |
| argLen: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLi2f", |
| argLen: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLf2i", |
| argLen: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "PXOR", |
| argLen: 2, |
| commutative: true, |
| resultInArg0: true, |
| asm: x86.APXOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "LEAQ", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAW", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAQ1", |
| auxType: auxSymOff, |
| argLen: 2, |
| commutative: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL1", |
| auxType: auxSymOff, |
| argLen: 2, |
| commutative: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAW1", |
| auxType: auxSymOff, |
| argLen: 2, |
| commutative: true, |
| symEffect: SymAddr, |
| asm: x86.ALEAW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAQ2", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAQ, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL2", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAL, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAW2", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAQ4", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAQ, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL4", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAW4", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAW, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAQ8", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAL8", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LEAW8", |
| auxType: auxSymOff, |
| argLen: 2, |
| symEffect: SymAddr, |
| asm: x86.ALEAW, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBQSXload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWQSXload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLQSXload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVLQSX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVOload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVUPS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVOstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVUPS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBLZX, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx2", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVWLZX, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLloadidx4", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx2", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVOstoreconst", |
| auxType: auxSymValAndOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVUPS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVB, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreconstidx2", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVLstoreconstidx4", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstoreconstidx1", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstoreconstidx8", |
| auxType: auxSymValAndOff, |
| argLen: 3, |
| symEffect: SymWrite, |
| asm: x86.AMOVQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "DUFFZERO", |
| auxType: auxInt64, |
| argLen: 2, |
| faultOnNilArg0: true, |
| unsafePoint: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| }, |
| clobbers: 128, // DI |
| }, |
| }, |
| { |
| name: "REPSTOSQ", |
| argLen: 4, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 2}, // CX |
| {2, 1}, // AX |
| }, |
| clobbers: 130, // CX DI |
| }, |
| }, |
| { |
| name: "CALLstatic", |
| auxType: auxCallOff, |
| argLen: -1, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| { |
| name: "CALLtail", |
| auxType: auxCallOff, |
| argLen: -1, |
| clobberFlags: true, |
| call: true, |
| tailCall: true, |
| reg: regInfo{ |
| clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| { |
| name: "CALLclosure", |
| auxType: auxCallOff, |
| argLen: -1, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 4}, // DX |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| { |
| name: "CALLinter", |
| auxType: auxCallOff, |
| argLen: -1, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| { |
| name: "DUFFCOPY", |
| auxType: auxInt64, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| unsafePoint: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 64}, // SI |
| }, |
| clobbers: 65728, // SI DI X0 |
| }, |
| }, |
| { |
| name: "REPMOVSQ", |
| argLen: 4, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 64}, // SI |
| {2, 2}, // CX |
| }, |
| clobbers: 194, // CX SI DI |
| }, |
| }, |
| { |
| name: "InvertFlags", |
| argLen: 1, |
| reg: regInfo{}, |
| }, |
| { |
| name: "LoweredGetG", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetClosurePtr", |
| argLen: 0, |
| zeroWidth: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerPC", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerSP", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredNilCheck", |
| argLen: 2, |
| clobberFlags: true, |
| nilCheck: true, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredWB", |
| auxType: auxSym, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymNone, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 128}, // DI |
| {1, 879}, // AX CX DX BX BP SI R8 R9 |
| }, |
| clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 |
| }, |
| }, |
| { |
| name: "LoweredHasCPUFeature", |
| auxType: auxSym, |
| argLen: 0, |
| rematerializeable: true, |
| symEffect: SymNone, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsA", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // DX |
| {1, 8}, // BX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsB", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // CX |
| {1, 4}, // DX |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsC", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // AX |
| {1, 2}, // CX |
| }, |
| }, |
| }, |
| { |
| name: "FlagEQ", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagLT_ULT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagLT_UGT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagGT_UGT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "FlagGT_ULT", |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "MOVBatomicload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVLatomicload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVQatomicload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XCHGB", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AXCHGB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XCHGL", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AXCHGL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XCHGQ", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| faultOnNilArg1: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AXCHGQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XADDLlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AXADDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "XADDQlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| resultInArg0: true, |
| clobberFlags: true, |
| faultOnNilArg1: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AXADDQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "AddTupleFirst32", |
| argLen: 2, |
| reg: regInfo{}, |
| }, |
| { |
| name: "AddTupleFirst64", |
| argLen: 2, |
| reg: regInfo{}, |
| }, |
| { |
| name: "CMPXCHGLlock", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.ACMPXCHGL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 1}, // AX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPXCHGQlock", |
| auxType: auxSymOff, |
| argLen: 4, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.ACMPXCHGQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 1}, // AX |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| clobbers: 1, // AX |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDBlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AANDB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDLlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AANDL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORBlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AORB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ORLlock", |
| auxType: auxSymOff, |
| argLen: 3, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| hasSideEffects: true, |
| symEffect: SymRdWr, |
| asm: x86.AORL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "PrefetchT0", |
| argLen: 2, |
| hasSideEffects: true, |
| asm: x86.APREFETCHT0, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "PrefetchNTA", |
| argLen: 2, |
| hasSideEffects: true, |
| asm: x86.APREFETCHNTA, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "ANDNQ", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AANDNQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "ANDNL", |
| argLen: 2, |
| clobberFlags: true, |
| asm: x86.AANDNL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSIQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSIQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSIL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSIL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSMSKQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSMSKQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSMSKL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSMSKL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSRQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSRQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "BLSRL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ABLSRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TZCNTQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ATZCNTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "TZCNTL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ATZCNTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LZCNTQ", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ALZCNTQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "LZCNTL", |
| argLen: 1, |
| clobberFlags: true, |
| asm: x86.ALZCNTL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEWstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBEL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBEL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELloadidx4", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVBEL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVBEL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQloadidx1", |
| auxType: auxSymOff, |
| argLen: 3, |
| commutative: true, |
| symEffect: SymRead, |
| asm: x86.AMOVBEQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQloadidx8", |
| auxType: auxSymOff, |
| argLen: 3, |
| symEffect: SymRead, |
| asm: x86.AMOVBEQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEWstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEW, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEWstoreidx2", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEW, |
| scale: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELstoreidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBELstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQstoreidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| commutative: true, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBEQstoreidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| symEffect: SymWrite, |
| asm: x86.AMOVBEQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| }, |
| }, |
| { |
| name: "SARXQ", |
| argLen: 2, |
| asm: x86.ASARXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXL", |
| argLen: 2, |
| asm: x86.ASARXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXQ", |
| argLen: 2, |
| asm: x86.ASHLXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXL", |
| argLen: 2, |
| asm: x86.ASHLXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXQ", |
| argLen: 2, |
| asm: x86.ASHRXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXL", |
| argLen: 2, |
| asm: x86.ASHRXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXLload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXQload", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SARXQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASARXQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHLXQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHLXQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXLloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXL, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXLloadidx4", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXL, |
| scale: 4, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXLloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXL, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXQloadidx1", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXQ, |
| scale: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| { |
| name: "SHRXQloadidx8", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: x86.ASHRXQ, |
| scale: 8, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 |
| }, |
| }, |
| }, |
| |
| { |
| name: "ADD", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUB", |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSB", |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MUL", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMUL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "HMUL", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "HMULU", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMULLU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CALLudiv", |
| argLen: 2, |
| clobberFlags: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // R1 |
| {1, 1}, // R0 |
| }, |
| clobbers: 20492, // R2 R3 R12 R14 |
| outputs: []outputInfo{ |
| {0, 1}, // R0 |
| {1, 2}, // R1 |
| }, |
| }, |
| }, |
| { |
| name: "ADDS", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADC", |
| argLen: 3, |
| commutative: true, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCconst", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBS", |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBC", |
| argLen: 3, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCconst", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCconst", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MULLU", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMULLU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MULA", |
| argLen: 3, |
| asm: arm.AMULA, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MULS", |
| argLen: 3, |
| asm: arm.AMULS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDF", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AADDF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "ADDD", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AADDD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBF", |
| argLen: 2, |
| asm: arm.ASUBF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "SUBD", |
| argLen: 2, |
| asm: arm.ASUBD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULF", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMULF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULD", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AMULD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "NMULF", |
| argLen: 2, |
| commutative: true, |
| asm: arm.ANMULF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "NMULD", |
| argLen: 2, |
| commutative: true, |
| asm: arm.ANMULD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "DIVF", |
| argLen: 2, |
| asm: arm.ADIVF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "DIVD", |
| argLen: 2, |
| asm: arm.ADIVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULAF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: arm.AMULAF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULAD", |
| argLen: 3, |
| resultInArg0: true, |
| asm: arm.AMULAD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULSF", |
| argLen: 3, |
| resultInArg0: true, |
| asm: arm.AMULSF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MULSD", |
| argLen: 3, |
| resultInArg0: true, |
| asm: arm.AMULSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "FMULAD", |
| argLen: 3, |
| resultInArg0: true, |
| asm: arm.AFMULAD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "AND", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "OR", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XOR", |
| argLen: 2, |
| commutative: true, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BIC", |
| argLen: 2, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BFX", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ABFX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BFXU", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ABFXU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVN", |
| argLen: 1, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "NEGF", |
| argLen: 1, |
| asm: arm.ANEGF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "NEGD", |
| argLen: 1, |
| asm: arm.ANEGD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "SQRTD", |
| argLen: 1, |
| asm: arm.ASQRTD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "SQRTF", |
| argLen: 1, |
| asm: arm.ASQRTF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "ABSD", |
| argLen: 1, |
| asm: arm.AABSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "CLZ", |
| argLen: 1, |
| asm: arm.ACLZ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "REV", |
| argLen: 1, |
| asm: arm.AREV, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "REV16", |
| argLen: 1, |
| asm: arm.AREV16, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RBIT", |
| argLen: 1, |
| asm: arm.ARBIT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SLL", |
| argLen: 2, |
| asm: arm.ASLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SLLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ASLL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRL", |
| argLen: 2, |
| asm: arm.ASRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRLconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ASRL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRA", |
| argLen: 2, |
| asm: arm.ASRA, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRAconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ASRA, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRR", |
| argLen: 2, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRRconst", |
| auxType: auxInt32, |
| argLen: 1, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRR", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftLL", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRL", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRA", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftLL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftRL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftRA", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftLL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftRL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftRA", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftLL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftRL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftRA", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftLLreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRLreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRAreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftLLreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRLreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRAreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftLLreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftRLreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBshiftRAreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftLLreg", |
| argLen: 3, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRLreg", |
| argLen: 3, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRAreg", |
| argLen: 3, |
| asm: arm.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftLLreg", |
| argLen: 3, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRLreg", |
| argLen: 3, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRAreg", |
| argLen: 3, |
| asm: arm.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftLLreg", |
| argLen: 3, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRLreg", |
| argLen: 3, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRAreg", |
| argLen: 3, |
| asm: arm.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftLLreg", |
| argLen: 3, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRLreg", |
| argLen: 3, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRAreg", |
| argLen: 3, |
| asm: arm.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftLLreg", |
| argLen: 2, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRLreg", |
| argLen: 2, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRAreg", |
| argLen: 2, |
| asm: arm.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftLLreg", |
| argLen: 4, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftRLreg", |
| argLen: 4, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADCshiftRAreg", |
| argLen: 4, |
| asm: arm.AADC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftLLreg", |
| argLen: 4, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftRLreg", |
| argLen: 4, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SBCshiftRAreg", |
| argLen: 4, |
| asm: arm.ASBC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftLLreg", |
| argLen: 4, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftRLreg", |
| argLen: 4, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSCshiftRAreg", |
| argLen: 4, |
| asm: arm.ARSC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftLLreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftRLreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSshiftRAreg", |
| argLen: 3, |
| asm: arm.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftLLreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftRLreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSshiftRAreg", |
| argLen: 3, |
| asm: arm.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftLLreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftRLreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "RSBSshiftRAreg", |
| argLen: 3, |
| asm: arm.ARSB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMP", |
| argLen: 2, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMN", |
| argLen: 2, |
| commutative: true, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TST", |
| argLen: 2, |
| commutative: true, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQ", |
| argLen: 2, |
| commutative: true, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPF", |
| argLen: 2, |
| asm: arm.ACMPF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPD", |
| argLen: 2, |
| asm: arm.ACMPD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftLL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftRL", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftRA", |
| auxType: auxInt32, |
| argLen: 2, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftLLreg", |
| argLen: 3, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRLreg", |
| argLen: 3, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRAreg", |
| argLen: 3, |
| asm: arm.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftLLreg", |
| argLen: 3, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRLreg", |
| argLen: 3, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRAreg", |
| argLen: 3, |
| asm: arm.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftLLreg", |
| argLen: 3, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRLreg", |
| argLen: 3, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRAreg", |
| argLen: 3, |
| asm: arm.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftLLreg", |
| argLen: 3, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftRLreg", |
| argLen: 3, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "TEQshiftRAreg", |
| argLen: 3, |
| asm: arm.ATEQ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMPF0", |
| argLen: 1, |
| asm: arm.ACMPF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "CMPD0", |
| argLen: 1, |
| asm: arm.ACMPD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWconst", |
| auxType: auxInt32, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVFconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm.AMOVF, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm.AMOVD, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWaddr", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294975488}, // SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVFload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVFstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm.AMOVF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx", |
| argLen: 3, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadshiftLL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadshiftRL", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadshiftRA", |
| auxType: auxInt32, |
| argLen: 3, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUloadidx", |
| argLen: 3, |
| asm: arm.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBloadidx", |
| argLen: 3, |
| asm: arm.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUloadidx", |
| argLen: 3, |
| asm: arm.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHloadidx", |
| argLen: 3, |
| asm: arm.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx", |
| argLen: 4, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreshiftLL", |
| auxType: auxInt32, |
| argLen: 4, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreshiftRL", |
| auxType: auxInt32, |
| argLen: 4, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreshiftRA", |
| auxType: auxInt32, |
| argLen: 4, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreidx", |
| argLen: 4, |
| asm: arm.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstoreidx", |
| argLen: 4, |
| asm: arm.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBreg", |
| argLen: 1, |
| asm: arm.AMOVBS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUreg", |
| argLen: 1, |
| asm: arm.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHreg", |
| argLen: 1, |
| asm: arm.AMOVHS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUreg", |
| argLen: 1, |
| asm: arm.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWreg", |
| argLen: 1, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWnop", |
| argLen: 1, |
| resultInArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWF", |
| argLen: 1, |
| asm: arm.AMOVWF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWD", |
| argLen: 1, |
| asm: arm.AMOVWD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUF", |
| argLen: 1, |
| asm: arm.AMOVWF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUD", |
| argLen: 1, |
| asm: arm.AMOVWD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVFW", |
| argLen: 1, |
| asm: arm.AMOVFW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDW", |
| argLen: 1, |
| asm: arm.AMOVDW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVFWU", |
| argLen: 1, |
| asm: arm.AMOVFW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDWU", |
| argLen: 1, |
| asm: arm.AMOVDW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| clobbers: 2147483648, // F15 |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "MOVFD", |
| argLen: 1, |
| asm: arm.AMOVFD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDF", |
| argLen: 1, |
| asm: arm.AMOVDF, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| outputs: []outputInfo{ |
| {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWHSconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CMOVWLSconst", |
| auxType: auxInt32, |
| argLen: 2, |
| resultInArg0: true, |
| asm: arm.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "SRAcond", |
| argLen: 3, |
| asm: arm.ASRA, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "CALLstatic", |
| auxType: auxCallOff, |
| argLen: 1, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| { |
| name: "CALLtail", |
| auxType: auxCallOff, |
| argLen: 1, |
| clobberFlags: true, |
| call: true, |
| tailCall: true, |
| reg: regInfo{ |
| clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| { |
| name: "CALLclosure", |
| auxType: auxCallOff, |
| argLen: 3, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 128}, // R7 |
| {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 |
| }, |
| clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| { |
| name: "CALLinter", |
| auxType: auxCallOff, |
| argLen: 2, |
| clobberFlags: true, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| { |
| name: "LoweredNilCheck", |
| argLen: 2, |
| nilCheck: true, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "Equal", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "NotEqual", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LessThan", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LessEqual", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "GreaterThan", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "GreaterEqual", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LessThanU", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LessEqualU", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "GreaterThanU", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "GreaterEqualU", |
| argLen: 1, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "DUFFZERO", |
| auxType: auxInt64, |
| argLen: 3, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // R1 |
| {1, 1}, // R0 |
| }, |
| clobbers: 20482, // R1 R12 R14 |
| }, |
| }, |
| { |
| name: "DUFFCOPY", |
| auxType: auxInt64, |
| argLen: 3, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // R2 |
| {1, 2}, // R1 |
| }, |
| clobbers: 20487, // R0 R1 R2 R12 R14 |
| }, |
| }, |
| { |
| name: "LoweredZero", |
| auxType: auxInt64, |
| argLen: 4, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // R1 |
| {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 2, // R1 |
| }, |
| }, |
| { |
| name: "LoweredMove", |
| auxType: auxInt64, |
| argLen: 4, |
| clobberFlags: true, |
| faultOnNilArg0: true, |
| faultOnNilArg1: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // R2 |
| {1, 2}, // R1 |
| {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| clobbers: 6, // R1 R2 |
| }, |
| }, |
| { |
| name: "LoweredGetClosurePtr", |
| argLen: 0, |
| zeroWidth: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 128}, // R7 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerSP", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredGetCallerPC", |
| argLen: 0, |
| rematerializeable: true, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsA", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // R2 |
| {1, 8}, // R3 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsB", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 2}, // R1 |
| {1, 4}, // R2 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicBoundsC", |
| auxType: auxInt64, |
| argLen: 3, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1}, // R0 |
| {1, 2}, // R1 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendA", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 16}, // R4 |
| {1, 4}, // R2 |
| {2, 8}, // R3 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendB", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 16}, // R4 |
| {1, 2}, // R1 |
| {2, 4}, // R2 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredPanicExtendC", |
| auxType: auxInt64, |
| argLen: 4, |
| call: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 16}, // R4 |
| {1, 1}, // R0 |
| {2, 2}, // R1 |
| }, |
| }, |
| }, |
| { |
| name: "FlagConstant", |
| auxType: auxFlagConstant, |
| argLen: 0, |
| reg: regInfo{}, |
| }, |
| { |
| name: "InvertFlags", |
| argLen: 1, |
| reg: regInfo{}, |
| }, |
| { |
| name: "LoweredWB", |
| auxType: auxSym, |
| argLen: 3, |
| clobberFlags: true, |
| symEffect: SymNone, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 4}, // R2 |
| {1, 8}, // R3 |
| }, |
| clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 |
| }, |
| }, |
| |
| { |
| name: "ADCSflags", |
| argLen: 3, |
| commutative: true, |
| asm: arm64.AADCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADCzerocarry", |
| argLen: 1, |
| asm: arm64.AADC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADD", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSconstflags", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AADDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDSflags", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AADDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUB", |
| argLen: 2, |
| asm: arm64.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUBconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SBCSflags", |
| argLen: 3, |
| asm: arm64.ASBCS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUBSflags", |
| argLen: 2, |
| asm: arm64.ASUBS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MUL", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AMUL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MULW", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AMULW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MNEG", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AMNEG, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MNEGW", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AMNEGW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MULH", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ASMULH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UMULH", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AUMULH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MULL", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ASMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UMULL", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AUMULL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "DIV", |
| argLen: 2, |
| asm: arm64.ASDIV, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UDIV", |
| argLen: 2, |
| asm: arm64.AUDIV, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "DIVW", |
| argLen: 2, |
| asm: arm64.ASDIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UDIVW", |
| argLen: 2, |
| asm: arm64.AUDIVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOD", |
| argLen: 2, |
| asm: arm64.AREM, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UMOD", |
| argLen: 2, |
| asm: arm64.AUREM, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MODW", |
| argLen: 2, |
| asm: arm64.AREMW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UMODW", |
| argLen: 2, |
| asm: arm64.AUREMW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FADDS", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFADDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FADDD", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFADDD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FSUBS", |
| argLen: 2, |
| asm: arm64.AFSUBS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FSUBD", |
| argLen: 2, |
| asm: arm64.AFSUBD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMULS", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFMULS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMULD", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFMULD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMULS", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFNMULS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMULD", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AFNMULD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FDIVS", |
| argLen: 2, |
| asm: arm64.AFDIVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FDIVD", |
| argLen: 2, |
| asm: arm64.AFDIVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "AND", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ANDconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "OR", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XOR", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XORconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BIC", |
| argLen: 2, |
| asm: arm64.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EON", |
| argLen: 2, |
| asm: arm64.AEON, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORN", |
| argLen: 2, |
| asm: arm64.AORN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MVN", |
| argLen: 1, |
| asm: arm64.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NEG", |
| argLen: 1, |
| asm: arm64.ANEG, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NEGSflags", |
| argLen: 1, |
| asm: arm64.ANEGS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {1, 0}, |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NGCzerocarry", |
| argLen: 1, |
| asm: arm64.ANGC, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FABSD", |
| argLen: 1, |
| asm: arm64.AFABSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNEGS", |
| argLen: 1, |
| asm: arm64.AFNEGS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNEGD", |
| argLen: 1, |
| asm: arm64.AFNEGD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FSQRTD", |
| argLen: 1, |
| asm: arm64.AFSQRTD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FSQRTS", |
| argLen: 1, |
| asm: arm64.AFSQRTS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "REV", |
| argLen: 1, |
| asm: arm64.AREV, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "REVW", |
| argLen: 1, |
| asm: arm64.AREVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "REV16", |
| argLen: 1, |
| asm: arm64.AREV16, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "REV16W", |
| argLen: 1, |
| asm: arm64.AREV16W, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "RBIT", |
| argLen: 1, |
| asm: arm64.ARBIT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "RBITW", |
| argLen: 1, |
| asm: arm64.ARBITW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "CLZ", |
| argLen: 1, |
| asm: arm64.ACLZ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "CLZW", |
| argLen: 1, |
| asm: arm64.ACLZW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "VCNT", |
| argLen: 1, |
| asm: arm64.AVCNT, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "VUADDLV", |
| argLen: 1, |
| asm: arm64.AVUADDLV, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredRound32F", |
| argLen: 1, |
| resultInArg0: true, |
| zeroWidth: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "LoweredRound64F", |
| argLen: 1, |
| resultInArg0: true, |
| zeroWidth: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMADDS", |
| argLen: 3, |
| asm: arm64.AFMADDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMADDD", |
| argLen: 3, |
| asm: arm64.AFMADDD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMADDS", |
| argLen: 3, |
| asm: arm64.AFNMADDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMADDD", |
| argLen: 3, |
| asm: arm64.AFNMADDD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMSUBS", |
| argLen: 3, |
| asm: arm64.AFMSUBS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMSUBD", |
| argLen: 3, |
| asm: arm64.AFMSUBD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMSUBS", |
| argLen: 3, |
| asm: arm64.AFNMSUBS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FNMSUBD", |
| argLen: 3, |
| asm: arm64.AFNMSUBD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MADD", |
| argLen: 3, |
| asm: arm64.AMADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MADDW", |
| argLen: 3, |
| asm: arm64.AMADDW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MSUB", |
| argLen: 3, |
| asm: arm64.AMSUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MSUBW", |
| argLen: 3, |
| asm: arm64.AMSUBW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SLL", |
| argLen: 2, |
| asm: arm64.ALSL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SLLconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ALSL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SRL", |
| argLen: 2, |
| asm: arm64.ALSR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SRLconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ALSR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SRA", |
| argLen: 2, |
| asm: arm64.AASR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SRAconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AASR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ROR", |
| argLen: 2, |
| asm: arm64.AROR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "RORW", |
| argLen: 2, |
| asm: arm64.ARORW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "RORconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AROR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "RORWconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ARORW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EXTRconst", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEXTR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EXTRWconst", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEXTRW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMP", |
| argLen: 2, |
| asm: arm64.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPW", |
| argLen: 2, |
| asm: arm64.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPWconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm64.ACMPW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMN", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNW", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ACMNW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNWconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm64.ACMNW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TST", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTconst", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTW", |
| argLen: 2, |
| commutative: true, |
| asm: arm64.ATSTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTWconst", |
| auxType: auxInt32, |
| argLen: 1, |
| asm: arm64.ATSTW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCMPS", |
| argLen: 2, |
| asm: arm64.AFCMPS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FCMPD", |
| argLen: 2, |
| asm: arm64.AFCMPD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FCMPS0", |
| argLen: 1, |
| asm: arm64.AFCMPS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FCMPD0", |
| argLen: 1, |
| asm: arm64.AFCMPD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftLL", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRL", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRA", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MVNshiftRO", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.AMVN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NEGshiftLL", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ANEG, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NEGshiftRL", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ANEG, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "NEGshiftRA", |
| auxType: auxInt64, |
| argLen: 1, |
| asm: arm64.ANEG, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ADDshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AADD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SUBshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ASUB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ANDshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AAND, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "XORshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEOR, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BICshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ABIC, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EONshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEON, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EONshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEON, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EONshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEON, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "EONshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AEON, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORNshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORNshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORNshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "ORNshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.AORN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMPshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "CMNshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ACMN, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftLL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRL", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRA", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "TSTshiftRO", |
| auxType: auxInt64, |
| argLen: 2, |
| asm: arm64.ATST, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "BFI", |
| auxType: auxARM64BitField, |
| argLen: 2, |
| resultInArg0: true, |
| asm: arm64.ABFI, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "BFXIL", |
| auxType: auxARM64BitField, |
| argLen: 2, |
| resultInArg0: true, |
| asm: arm64.ABFXIL, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SBFIZ", |
| auxType: auxARM64BitField, |
| argLen: 1, |
| asm: arm64.ASBFIZ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SBFX", |
| auxType: auxARM64BitField, |
| argLen: 1, |
| asm: arm64.ASBFX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UBFIZ", |
| auxType: auxARM64BitField, |
| argLen: 1, |
| asm: arm64.AUBFIZ, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "UBFX", |
| auxType: auxARM64BitField, |
| argLen: 1, |
| asm: arm64.AUBFX, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDconst", |
| auxType: auxInt64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDconst", |
| auxType: auxFloat64, |
| argLen: 0, |
| rematerializeable: true, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDaddr", |
| auxType: auxSymOff, |
| argLen: 1, |
| rematerializeable: true, |
| symEffect: SymAddr, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372037928517632}, // SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVWU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "LDP", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.ALDP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDload", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymRead, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDloadidx", |
| argLen: 3, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx", |
| argLen: 3, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUloadidx", |
| argLen: 3, |
| asm: arm64.AMOVWU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHloadidx", |
| argLen: 3, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUloadidx", |
| argLen: 3, |
| asm: arm64.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBloadidx", |
| argLen: 3, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUloadidx", |
| argLen: 3, |
| asm: arm64.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSloadidx", |
| argLen: 3, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDloadidx", |
| argLen: 3, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHloadidx2", |
| argLen: 3, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUloadidx2", |
| argLen: 3, |
| asm: arm64.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWloadidx4", |
| argLen: 3, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUloadidx4", |
| argLen: 3, |
| asm: arm64.AMOVWU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDloadidx8", |
| argLen: 3, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSloadidx4", |
| argLen: 3, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDloadidx8", |
| argLen: 3, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "STP", |
| auxType: auxSymOff, |
| argLen: 4, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.ASTP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDstore", |
| auxType: auxSymOff, |
| argLen: 3, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstoreidx", |
| argLen: 4, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstoreidx", |
| argLen: 4, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx", |
| argLen: 4, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstoreidx", |
| argLen: 4, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSstoreidx", |
| argLen: 4, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDstoreidx", |
| argLen: 4, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstoreidx2", |
| argLen: 4, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstoreidx4", |
| argLen: 4, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstoreidx8", |
| argLen: 4, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSstoreidx4", |
| argLen: 4, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDstoreidx8", |
| argLen: 4, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstorezero", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstorezero", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstorezero", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstorezero", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVQstorezero", |
| auxType: auxSymOff, |
| argLen: 2, |
| faultOnNilArg0: true, |
| symEffect: SymWrite, |
| asm: arm64.ASTP, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVBstorezeroidx", |
| argLen: 3, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstorezeroidx", |
| argLen: 3, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstorezeroidx", |
| argLen: 3, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstorezeroidx", |
| argLen: 3, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVHstorezeroidx2", |
| argLen: 3, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVWstorezeroidx4", |
| argLen: 3, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "MOVDstorezeroidx8", |
| argLen: 3, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDgpfp", |
| argLen: 1, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVDfpgp", |
| argLen: 1, |
| asm: arm64.AFMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSgpfp", |
| argLen: 1, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FMOVSfpgp", |
| argLen: 1, |
| asm: arm64.AFMOVS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBreg", |
| argLen: 1, |
| asm: arm64.AMOVB, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVBUreg", |
| argLen: 1, |
| asm: arm64.AMOVBU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHreg", |
| argLen: 1, |
| asm: arm64.AMOVH, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVHUreg", |
| argLen: 1, |
| asm: arm64.AMOVHU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWreg", |
| argLen: 1, |
| asm: arm64.AMOVW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVWUreg", |
| argLen: 1, |
| asm: arm64.AMOVWU, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDreg", |
| argLen: 1, |
| asm: arm64.AMOVD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "MOVDnop", |
| argLen: 1, |
| resultInArg0: true, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "SCVTFWS", |
| argLen: 1, |
| asm: arm64.ASCVTFWS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "SCVTFWD", |
| argLen: 1, |
| asm: arm64.ASCVTFWD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "UCVTFWS", |
| argLen: 1, |
| asm: arm64.AUCVTFWS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "UCVTFWD", |
| argLen: 1, |
| asm: arm64.AUCVTFWD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "SCVTFS", |
| argLen: 1, |
| asm: arm64.ASCVTFS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "SCVTFD", |
| argLen: 1, |
| asm: arm64.ASCVTFD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "UCVTFS", |
| argLen: 1, |
| asm: arm64.AUCVTFS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "UCVTFD", |
| argLen: 1, |
| asm: arm64.AUCVTFD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZSSW", |
| argLen: 1, |
| asm: arm64.AFCVTZSSW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZSDW", |
| argLen: 1, |
| asm: arm64.AFCVTZSDW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZUSW", |
| argLen: 1, |
| asm: arm64.AFCVTZUSW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZUDW", |
| argLen: 1, |
| asm: arm64.AFCVTZUDW, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZSS", |
| argLen: 1, |
| asm: arm64.AFCVTZSS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZSD", |
| argLen: 1, |
| asm: arm64.AFCVTZSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZUS", |
| argLen: 1, |
| asm: arm64.AFCVTZUS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTZUD", |
| argLen: 1, |
| asm: arm64.AFCVTZUD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTSD", |
| argLen: 1, |
| asm: arm64.AFCVTSD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FCVTDS", |
| argLen: 1, |
| asm: arm64.AFCVTDS, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FRINTAD", |
| argLen: 1, |
| asm: arm64.AFRINTAD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FRINTMD", |
| argLen: 1, |
| asm: arm64.AFRINTMD, |
| reg: regInfo{ |
| inputs: []inputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| outputs: []outputInfo{ |
| {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 |
| }, |
| }, |
| }, |
| { |
| name: "FRINTND", |
| argLen: 1, |
| asm: arm64.AFRINTND, |
|
