)]}' { "log": [ { "commit": "c8b62eadd14a2f4dd5dfafd5f0887f9cad1e1b48", "tree": "a8709ea597cd54cafb7d15ebf4138b21b7dbd84a", "parents": [ "c612c331311745ed3c658c75171b48b9981f56e9" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Thu Apr 30 19:06:12 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Apr 30 16:07:31 2026 -0700" }, "message": "Add Cortex-A320 to MIDR decode table (#384)\n\nARM Cortex-A320 (MIDR part 0xD8F) is an ARMv9.2-A efficiency core.\nAdd its uarch enum and MIDR mapping so XNNPACK can select optimized\nkernels when running on this core.\n\nSigned-off-by: Nicolas Pitre \u003cnpitre@baylibre.com\u003e\nGitOrigin-RevId: 3681f0ce1446167d01dfe125d6db96ba2ac31c3c\nChange-Id: I7b587f7f86bdc3923e84f9edea36e17584ea0da3\n" }, { "commit": "c612c331311745ed3c658c75171b48b9981f56e9", "tree": "c1c870241b64c662103872ee91ef4aa0bdb5ef9e", "parents": [ "bc9227363e84c14411eba62e8b167809ab8d358b" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Apr 28 09:00:41 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Apr 28 09:07:45 2026 -0700" }, "message": "Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC (#381)\n\n* Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC.\n\n* style: format src/riscv/linux/riscv-hw.c with clang-format\n\nGitOrigin-RevId: e829e80faba35db623b5e272c867ad72146adcda\nChange-Id: I9ee1cf0ce1623a0dffa09cac0df7183c2550ccb2\n" }, { "commit": "bc9227363e84c14411eba62e8b167809ab8d358b", "tree": "72f9a063eb8e2bd99f55ea3be714f54b1184ceb6", "parents": [ "d09062419e9073d6a199c4ce4d75f488bf939676" ], "author": { "name": "Ken Unger", "email": "108287829+ken-unger@users.noreply.github.com", "time": "Tue Apr 14 22:20:00 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Apr 14 22:25:28 2026 -0700" }, "message": "Add riscv half-precision floating point detection (#375)\n\nAdd cpuinfo_has_riscv_zfh() and cpuinfo_has_riscv_zvfh for fp16 detection.\n\nThe motivation here is to enable this runtime detection support in xnnpack for its rvv fp16 kernels. (xnnpack uses this library)\n\nGitOrigin-RevId: d05fbcd57dc096718c4979e7c054e628f1f3520b\nChange-Id: I6cbab6d7c0fb2eb1a605edfeb22a4df2684c8d20\n" }, { "commit": "d09062419e9073d6a199c4ce4d75f488bf939676", "tree": "896fd531889a2c4150c560aa29ceb4e3faa47f6a", "parents": [ "112233776ed54823b1a7d6153a36873dc08954c2" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Apr 13 13:19:06 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Apr 13 13:24:41 2026 -0700" }, "message": "Add Sapphire Rapids (Golden Cove) microarchitecture detection (#377)\n\n* Add Sapphire Rapids (Golden Cove) microarchitecture detection\n\n* Add Emerald Rapids and Granite Rapids microarchitecture detection\n\nGitOrigin-RevId: bc3c01e230c6974283e4b89421cfb0e232435589\nChange-Id: I3d90838f9fb302636e38b472bf08208429838414\n" }, { "commit": "112233776ed54823b1a7d6153a36873dc08954c2", "tree": "09b08e7abd96983a1757ab86601030efa1a3df07", "parents": [ "0d383615fe4d59f74afbdc775355497c44bcdc69" ], "author": { "name": "Rohanjames1997", "email": "rohan.james4@gmail.com", "time": "Wed Mar 11 20:02:42 2026 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Mar 11 18:08:41 2026 -0700" }, "message": "Report correct L2 cache size on ARM (Neoverse V1/V2) (#372)\n\nBy fetching the values from `/sys/devices/system/cpu/cpuN/cache/indexM/{size,level,type,...}`, that is populate via\nhttps://github.com/torvalds/linux/blob/master/arch/arm64/kernel/cacheinfo.c\nand\nhttps://github.com/torvalds/linux/blob/master/drivers/acpi/pptt.c\n\nFixes #369\n\nTested on Arm Neoverse V1 and V2 EC2 instances. I reused the reproducer in #369\n\n```\n#include \u003ccstddef\u003e\n#include \u003ccstdio\u003e\n#include \u003ccpuinfo.h\u003e\nsize_t l2_bytes() {\n if (!cpuinfo_initialize()) return 0;\n const cpuinfo_processor* p \u003d cpuinfo_get_current_processor();\n if (!p || !p-\u003ecache.l2) return 0;\n return p-\u003ecache.l2-\u003esize; // bytes\n}\nint main() { std::printf(\"%zu\\n\", l2_bytes()); }\n```\n\nThis now returns the expected results on Arm Neoverse V1 and V2\n___\n\nAdditionally, here is the output of `./cache-info`.\n1. On Neoverse-V1:\n```\nMax cache size (upper bound): 4194304 bytes\nL1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL2 data cache: 64 x 1 MB (inclusive), 8-way set associative (2048 sets), 64 byte lines, shared by 1 processors\n```\n2. On Neoverse-V2:\n```\nMax cache size (upper bound): 4194304 bytes\nL1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL2 data cache: 64 x 2 MB (inclusive), 8-way set associative (4096 sets), 64 byte lines, shared by 1 processors\n```\n\nGitOrigin-RevId: 7607ca500436b37ad23fb8d18614bec7796b68a7\nChange-Id: I853103738bff3ff3a1db51cd33f0206fb4c8243e\n" }, { "commit": "0d383615fe4d59f74afbdc775355497c44bcdc69", "tree": "7e3267be3f82a9ce75ffdebf7e93079596814cdf", "parents": [ "432573cd3ecacb9914b6a4eeef812c29c4216f07" ], "author": { "name": "Alexander Shaposhnikov", "email": "alexander.v.shaposhnikov@gmail.com", "time": "Wed Feb 18 13:35:49 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Feb 18 13:38:54 2026 -0800" }, "message": "[cpuinfo] Add linux_ppc64le config (#373)\n\nGitOrigin-RevId: 7364b490b5f78d58efe23ea76e74210fd6c3c76f\nChange-Id: Ie8c68894122c617b2579422f8e00db68aa9aeb47\n" }, { "commit": "432573cd3ecacb9914b6a4eeef812c29c4216f07", "tree": "a33b6644d36f177b9a34c73468c49f4a69daaa3f", "parents": [ "5e89ba92e7f6c03d153bda4da26062a23f71e892" ], "author": { "name": "Redwanul Haque Sourave", "email": "redwanul.sourav@gmail.com", "time": "Fri Jan 30 12:45:09 2026 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jan 30 10:07:49 2026 -0800" }, "message": "Fix buffer size for reading processor core id (#352)\n\nGitOrigin-RevId: 84818a41e074779dbb00521a4731d3e14160ff15\nChange-Id: Ib0c983dac291bb9feb4fc8d17fe636330564b569\n" }, { "commit": "5e89ba92e7f6c03d153bda4da26062a23f71e892", "tree": "c3970bf3a131ce813a1799eb99adacfd8fd91ae6", "parents": [ "7bc55c80db855b11a8c9b4eacb184509d04d4ded" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Jan 27 12:07:08 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 27 12:37:44 2026 -0800" }, "message": "Detect AMD Family 26 extended models for cpuinfo_uarch_zen6 (#371)\n\n* Fix cpuinfo_x86_normalize_brand_string unannotated fall-through warning\n\n* Detect AMD Family 26 extended models for cpuinfo_uarch_zen6\n\nGitOrigin-RevId: f9a03241f8c3d4ed0c9728f5d70bff873d43d4e0\nChange-Id: I00a5dbcb9d3a0539358bf8c37680796aa5542b98\n" }, { "commit": "7bc55c80db855b11a8c9b4eacb184509d04d4ded", "tree": "918083100fe0533be968077741dd5c372a595587", "parents": [ "864fed28d443b7f924e7e4c15e4d044a4ed8f80d" ], "author": { "name": "Edward Chen", "email": "18449977+edgchen1@users.noreply.github.com", "time": "Tue Jan 27 07:36:42 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 27 07:37:50 2026 -0800" }, "message": "Add fallback for ARM Windows fp16 detection. (#348)\n\nBackground: On a Windows ARM system, I observed that `cpuinfo_has_arm_fp16_arith()` started to return false after upgrading to a more recent cpuinfo version.\n\nIn #333, the initialization of `cpuinfo_isa.fp16arith` was updated to use `IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE)`. I suspect that this is not supported on older Windows versions.\n\nThis change adds a fallback path to set `cpuinfo_isa.fp16arith` the old way.\nhttps://github.com/pytorch/cpuinfo/blob/d3a86a813e2bb49d1eb5841ec12e2b135867ab98/src/arm/windows/init.c#L205-L208\n\nGitOrigin-RevId: b8ecd2f4455f593be18326b89af19be3f9959293\nChange-Id: I8330ce734d033306b860140ef1fc77ca58bfeae9\n" }, { "commit": "864fed28d443b7f924e7e4c15e4d044a4ed8f80d", "tree": "9d8cb7a2b9a35736bb90007ce3a85e0c334046c3", "parents": [ "24811ad75e0660e1e70083c8b3bb480ba146fc5a" ], "author": { "name": "Alfredo Tupone", "email": "tupone@gentoo.org", "time": "Mon Jan 26 23:47:25 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 26 14:53:37 2026 -0800" }, "message": "cmake will require at least 3.10 compatibility (#319)\n\nGitOrigin-RevId: e7b796ccd140df3264afd3f032debd51b4a776df\nChange-Id: I4503f83130e41881d743744bef3bb6313bfad241\n" }, { "commit": "24811ad75e0660e1e70083c8b3bb480ba146fc5a", "tree": "7592acfa036477ebf8914b5aeb4fb16e9121b538", "parents": [ "58870cb25ec9d088cb316b32a12c37f1e4ce7a94" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jan 26 14:25:29 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 26 14:32:39 2026 -0800" }, "message": "Add ARM Lumex C1 uarch (#370)\n\n* Add ARM Lumex C1 uarch\n\nSoC name: MediaTek MT6993\nMicroarchitectures:\n\t1x Lumex-C1-Ultra\n\t3x Lumex-C1-Premium\n\t4x Lumex-C1-Pro\nCores:\n\t0: 1 processor (0), ARM Lumex-C1-Ultra\n\t1: 1 processor (1), ARM Lumex-C1-Premium\n\t2: 1 processor (2), ARM Lumex-C1-Premium\n\t3: 1 processor (3), ARM Lumex-C1-Premium\n\t4: 1 processor (4), ARM Lumex-C1-Pro\n\t5: 1 processor (5), ARM Lumex-C1-Pro\n\t6: 1 processor (6), ARM Lumex-C1-Pro\n\t7: 1 processor (7), ARM Lumex-C1-Pro\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Lumex-C1-Ultra\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Lumex-C1-Premium\n\t2: 4 processors (4-7),\t2: 4 cores (4-7), ARM Lumex-C1-Pro\nLogical processors (System ID):\n\t0 (7)\n\t1 (4)\n\t2 (5)\n\t3 (6)\n\t4 (0)\n\t5 (1)\n\t6 (2)\n\t7 (3)\n\nPart numbers documented here:\nhttps://en.wikichip.org/wiki/arm_holdings/cortex\n\n* Add ARM Lumex C1 uarch\n\nSoC name: MediaTek MT6993\nMicroarchitectures:\n\t1x Lumex-C1-Ultra\n\t3x Lumex-C1-Premium\n\t4x Lumex-C1-Pro\nCores:\n\t0: 1 processor (0), ARM Lumex-C1-Ultra\n\t1: 1 processor (1), ARM Lumex-C1-Premium\n\t2: 1 processor (2), ARM Lumex-C1-Premium\n\t3: 1 processor (3), ARM Lumex-C1-Premium\n\t4: 1 processor (4), ARM Lumex-C1-Pro\n\t5: 1 processor (5), ARM Lumex-C1-Pro\n\t6: 1 processor (6), ARM Lumex-C1-Pro\n\t7: 1 processor (7), ARM Lumex-C1-Pro\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Lumex-C1-Ultra\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Lumex-C1-Premium\n\t2: 4 processors (4-7),\t2: 4 cores (4-7), ARM Lumex-C1-Pro\nLogical processors (System ID):\n\t0 (7)\n\t1 (4)\n\t2 (5)\n\t3 (6)\n\t4 (0)\n\t5 (1)\n\t6 (2)\n\t7 (3)\n\nPart numbers documented here:\nhttps://en.wikichip.org/wiki/arm_holdings/cortex\n\n* remove dot and fp16\n\n* fix mock naming\n\nGitOrigin-RevId: 1ce292fdeceb9a4dee168074a84d629a1f57e2fd\nChange-Id: If6416d7a8b4999c51ed5b1f683544faea3f2ed62\n" }, { "commit": "58870cb25ec9d088cb316b32a12c37f1e4ce7a94", "tree": "0587a365d0fb969a8b0921c6a110eb52212b3faa", "parents": [ "fbfe5ddc75d0f8b80491a4a91d40bafb12da1a0b" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Jan 14 09:57:04 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Jan 14 10:09:40 2026 -0800" }, "message": "Add ARM Cortex A520 little core uarch (#367)\n\nExample Samsung S24 sm-s921u\n\nSoC name: Unknown\nMicroarchitectures:\n\t1x Cortex-X4\n\t5x Cortex-A720\n\t2x Cortex-A520\nCores:\n\t0: 1 processor (0), ARM Cortex-X4\n\t1: 1 processor (1), ARM Cortex-A720\n\t2: 1 processor (2), ARM Cortex-A720\n\t3: 1 processor (3), ARM Cortex-A720\n\t4: 1 processor (4), ARM Cortex-A720\n\t5: 1 processor (5), ARM Cortex-A720\n\t6: 1 processor (6), ARM Cortex-A520\n\t7: 1 processor (7), ARM Cortex-A520\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Cortex-X4\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Cortex-A720\n\t2: 2 processors (4-5),\t2: 2 cores (4-5), ARM Cortex-A720\n\t3: 2 processors (6-7),\t3: 2 cores (6-7), ARM Cortex-A520\nLogical processors (System ID):\n\t0 (7)\n\t1 (2)\n\t2 (3)\n\t3 (4)\n\t4 (5)\n\t5 (6)\n\t6 (0)\n\t7 (1)\nGitOrigin-RevId: c4b4f4bf08c0cf486fc3111d0244ebf2a48ad01b\nChange-Id: I63adcc520b0b9d1061eadd706fcdd7f19bcec297\n" }, { "commit": "fbfe5ddc75d0f8b80491a4a91d40bafb12da1a0b", "tree": "d39c41144dde9a2b71585e2c39c9608a9d0a491c", "parents": [ "5338bf120bbff14279944ce72becff7ba7550095" ], "author": { "name": "Alfredo Tupone", "email": "tupone@gentoo.org", "time": "Wed Jan 07 02:51:28 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 06 18:08:14 2026 -0800" }, "message": "Upgrade C++ standard from CXX14 to CXX17 (#355)\n\nIt is required by gtest (newest version)\n\nGitOrigin-RevId: 0fea7f5f88243ee354df0e0082b5f27d13fc9551\nChange-Id: I3ca52fd24273f7614d7b382b029b981d621d25d9\n" }, { "commit": "5338bf120bbff14279944ce72becff7ba7550095", "tree": "bdcb54d78b7bc5cadc928a6a0981a834d80b2e54", "parents": [ "a18d6e6b2a621e076a0697fa0b0930aa5ef700e7" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Jan 06 16:43:55 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 06 16:50:32 2026 -0800" }, "message": "Add Apple M3, M5 and A19 uarch support (#366)\n\n* Fix cpuinfo_x86_normalize_brand_string unannotated fall-through warning\n\n* Add Apple M3, M5 and A19 uarch support\n\n* fix duplicate header uarch\n\nGitOrigin-RevId: 315f594e7f4d4c35f357289ae5304af8d38d9fc3\nChange-Id: I7e97000f5a8581aa163406a6145a1cdadd581d93\n" }, { "commit": "a18d6e6b2a621e076a0697fa0b0930aa5ef700e7", "tree": "de4351dad78afff51e5efc56baf67e7140cac77b", "parents": [ "3ca74de7296a51db117caec1a9b2c249caef25dc" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jan 05 13:38:16 2026 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 05 14:08:03 2026 -0800" }, "message": "Add Apple SME isa and vector length detects (#363)\n\n* Apple SME 2p1 and vector length detect\n\n- similar to windows/init.c but use sysinfo\n hw.optional.arm.FEAT_SME2p1\n hw.optional.arm.sme_max_svl_b\n\nTested on Macbook Pro with M4\n\n* Add Apple SME isa and vector length detects\n\n* clang format applied\n\nGitOrigin-RevId: 2846bafc7c785f274e6e5defb26dabdb05fac148\nChange-Id: I9b2b9ccdc15d240091a776675b7c53f19ca70335\n" }, { "commit": "3ca74de7296a51db117caec1a9b2c249caef25dc", "tree": "d77dbd26ff4b0d738a88062d5b6a26b06175695c", "parents": [ "d44b5ac9d4b9b4c086cd1329c8bbaaa484557fce" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 30 12:40:41 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Dec 30 12:46:37 2025 -0800" }, "message": "Apple M4 uarch detect (#362)\n\n* Apple M4 uarch detect\n\n- Detect M4 and M4 Pro p-core and e-core\n\n* clang-format applied\n\n* fix clang-format\n\nGitOrigin-RevId: b3b25967b5b80406304d575321e572c5f9e5e3c4\nChange-Id: Ibe6516878f3f3bda1912c4477d0986f8b3451946\n" }, { "commit": "d44b5ac9d4b9b4c086cd1329c8bbaaa484557fce", "tree": "af78bff4cf795dc12c83aa797d9e87d3d5542f3d", "parents": [ "ce1636864e4c42601f1a2a901a6266d44b1f120a" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 30 10:13:14 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Dec 30 10:38:55 2025 -0800" }, "message": "Blizzard duplicate return removed (#360)\n\n* Fix duplicate blizzard return\n\n- Fix a copy/paste error in uarch detect for Apple blizzard/avalanche uarch\n- Add comment for A14/M1 and A15/M2 cpufamily\n\n* Fix duplicate return for Apple M2 detect uarch\n\n- Add comments for M1 and M2\n\n* Fix comments for CPUFAMILY to match what the case/return are for\n\nGitOrigin-RevId: e3f82e8f64f81e7a6987485f6795af6bd5f639e4\nChange-Id: I2d004eaea8e9107f7eadb69629b1ba09668f5e3d\n" }, { "commit": "ce1636864e4c42601f1a2a901a6266d44b1f120a", "tree": "b59fcb274ebcdac577afe8f9a10f1190f54ca139", "parents": [ "af44d46f93373f39c8452a1b1dad2d38a8788f40" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Sun Dec 28 17:27:38 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sun Dec 28 17:38:17 2025 -0800" }, "message": "Fix typo cpofreq (#358)\n\n- Replace cpofreq with cpufreq\n\nGitOrigin-RevId: 38b1af9c619b4546bcfa3e66398a8cd8aa94c25a\nChange-Id: I2c1f391c040aa7ccd8ca9c658a956e8abc17a8c4\n" }, { "commit": "af44d46f93373f39c8452a1b1dad2d38a8788f40", "tree": "8740990d7776299a4f866d4346c6835cd9b14675", "parents": [ "08397af4bc893fd2587120259b0c9020a60eecb3" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Sun Dec 28 17:27:30 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sun Dec 28 17:38:11 2025 -0800" }, "message": "Add Oryon V3 uarch detect for pytorch/cpuinfo (#357)\n\nTested with One Plus 15\ndevice:\n - ro.product.device: \"OP611FL1\"\n - ro.product.name: \"CPH2747\"\n - ro.product.brand: \"OnePlus\"\n - ro.product.manufacturer: \"OnePlus\"\n - ro.product.model: \"CPH2747\"\n - ro.soc.manufacturer: \"QTI\"\n - ro.soc.model: \"SM8850\"\nprocessor:\n - chipset: \"Unknown\"\n - core: \"Oryon V3\"\n - MIDR: 0x512F0021\nGitOrigin-RevId: 002c213d16b9dc3ddfb7ab388b13183df0e81c49\nChange-Id: Ie5d7080490c3e688e7b755ee212a2cce86bc777e\n" }, { "commit": "08397af4bc893fd2587120259b0c9020a60eecb3", "tree": "9baa24c8dafd3aeed490453d8fc0cf3f5d2e654a", "parents": [ "8f990f4eb00a25ab8fdf3f49e63fded8e4ea60e4" ], "author": { "name": "Vertexwahn", "email": "julian.amann@tum.de", "time": "Thu Dec 11 23:49:18 2025 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Dec 11 15:07:53 2025 -0800" }, "message": "Bazel support: Sync with current status of BCR and apply fixes for Bazel 9 (#345)\n\nGitOrigin-RevId: e8b4def4e6e67bc78d1882b2d709d6f6e13097ee\nChange-Id: I2058aef24210ad704bb0e1914032816c87908c7f\n" }, { "commit": "8f990f4eb00a25ab8fdf3f49e63fded8e4ea60e4", "tree": "e2f8879b3443434d35620ebe1fbd9cb287befd95", "parents": [ "37720e20ad447a663121e17464cbec8c5943d908" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 09 15:14:26 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Dec 09 15:38:50 2025 -0800" }, "message": "add Cortex A78C midr detect (#354)\n\n* add Cortex A78C midr detect\n\n- Detect ARM part 0xD4B (Cortex-A78C) and return cpuinfo_uarch_cortex_a78\n\n* fix clang format error for tabs\n\nGitOrigin-RevId: ff24ffee8340fbd9001cce6a9ef41cdd16aa2bd3\nChange-Id: I484ebcb65cf7ed288c63a39c753ac7f6561787e4\n" }, { "commit": "37720e20ad447a663121e17464cbec8c5943d908", "tree": "3c626671cb1181035f1aaa756c18ff461f8cd961", "parents": [ "928e96a256b70d8e8df816d64daa17d4c90375cf" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Nov 19 09:38:05 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Nov 19 10:07:45 2025 -0800" }, "message": "Fix ARM build -Wlogical-op-parentheses for unisoc detect (#347)\n\n- Add parentheses around the \u0027\u0026\u0026\u0027 expression\n\nGitOrigin-RevId: 161a9ec374884f4b3e85725cb22e05f9458fdc93\nChange-Id: If786bf8b8b1c960dfff0d767d5c0f718189414f6\n" }, { "commit": "928e96a256b70d8e8df816d64daa17d4c90375cf", "tree": "6d0f462cb479a3bfb35454cba9f32d3372177025", "parents": [ "8c7cd15230490cfa6fd1a8a86bb4cca3ca4ae84a" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Nov 18 11:51:03 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Nov 18 12:07:41 2025 -0800" }, "message": "Fix overread asan error of brand_string (#344)\n\n- Brand string is 3 rows of cpuid which is 48 bytes.\n- Allow for CPUINFO_PACKAGE_NAME_MAX to be 64 bytes for benefit of Oryon\n\nGitOrigin-RevId: 403d652dca4c1046e8145950b1c0997a9f748b57\nChange-Id: I7353fb97c9dfa98ae63cc99db0bd0b15acf52f59\n" }, { "commit": "8c7cd15230490cfa6fd1a8a86bb4cca3ca4ae84a", "tree": "56c633a8b6a0a49ad631a516e0c70e1695bdb7bd", "parents": [ "262f181b79f93e037c5cdbf2ac3f124566d5eded" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Fri Nov 14 12:00:48 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Nov 14 11:07:40 2025 -0800" }, "message": "Improve unisoc vendor detection, re-enable neon dot on unknown chipsets (#342)\n\nGitOrigin-RevId: f858c30bcb16f8effd5ff46996f0514539e17abc\nChange-Id: I3c4ef8f2da21e3cbc6421cfeb19fd5028ddf9299\n" }, { "commit": "262f181b79f93e037c5cdbf2ac3f124566d5eded", "tree": "6491c952681f1df92cf919c7bde1b3c93301e0be", "parents": [ "07df00403a496f0ba982437e8555845e662f5f8b" ], "author": { "name": "Bin Bao", "email": "binbao@meta.com", "time": "Fri Nov 14 10:47:39 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Nov 14 07:54:07 2025 -0800" }, "message": "Fix missing AMD cache info when running on a VM (#338)\n\nSummary: Fix https://github.com/pytorch/pytorch/issues/138718. This PR is verified to fix the issue and will be guarded on the PyTorch CI.\n\nWhen running on a VM, the AMD TopologyExtensions bit can be cleared, but that shouldn\u0027t stop us from reading the cache information.\n\nGitOrigin-RevId: 1d1dbb4cd620d9d0026872da2d85418263179f20\nChange-Id: I093072de27da6a24e0343c12554197fbca387bd7\n" }, { "commit": "07df00403a496f0ba982437e8555845e662f5f8b", "tree": "132b5df688a7351cb1fe99da062453a266ee5581", "parents": [ "aae638e2e80abfc53dd068fc6bdc52d2aa5d6f76" ], "author": { "name": "Jimothy Branson", "email": "jimothy@bouncingsheep.org", "time": "Thu Nov 13 15:46:12 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 13 16:07:59 2025 -0800" }, "message": "Allow for longer CPU names (#320)\n\nIncrease CPUINFO_PACKAGE_NAME_MAX to allow for longer strings,\nsuch as \"Snapdragon® X Elite - X1E78100 - Qualcomm® Oryon™ CPU\",\nwhich is 53 characters and WideCharToMultiByte converts to a\n57 byte string.\n\nGitOrigin-RevId: 952a519883239e086e9a78299a6efb8f6614022f\nChange-Id: I2e5a413cd44b17fadf02d3a48659b388f741a1ca\n" }, { "commit": "aae638e2e80abfc53dd068fc6bdc52d2aa5d6f76", "tree": "fd6f045a8e219459cecf729a38bc27e157cebf34", "parents": [ "c0495526a74b3b05536fa9086fa1c4f6fda46f02" ], "author": { "name": "Byoungchan Lee", "email": "byoungchan.lee@gmx.com", "time": "Fri Nov 14 08:29:49 2025 +0900" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 13 15:35:51 2025 -0800" }, "message": "Fix Unisoc T618 Chipset Detection (#307)\n\nAdd support for uppercase \"UNISOC T\" prefix in `match_t` function to handle\ndevices like Samsung Galaxy Tab A8 (SM-X205N) that report \"UNISOC T618\"\ninstead of the expected mixed-case \"Unisoc T618\".\n\nThe function now explicitly matches both variants:\n- \"Unisoc T\" (mixed case, existing)\n- \"UNISOC T\" (uppercase, new)\n\nThis ensures proper chipset vendor detection on affected Samsung devices\nwhere the uppercase variant caused match failures.\n\nIncludes test case for \"UNISOC T618\" detection.\n\nGitOrigin-RevId: f1f25cbe838f514c6bdbe762574e0e14538bdba8\nChange-Id: I287b38502b37f7c0b8f3f8cdd7e71a9ee0a5c71c\n" }, { "commit": "c0495526a74b3b05536fa9086fa1c4f6fda46f02", "tree": "8664df6e77beabc8f6bb584af068ba278bdfa440", "parents": [ "a73883e3d2ad194e5551ca7ad2124c1a2a138a7a" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Nov 11 19:16:48 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Nov 11 19:37:45 2025 -0800" }, "message": "Rollback Ignore disabled hyperthreads (#340)\n\nFixes #339\n\nGitOrigin-RevId: 735b2ac12f69aaf408784ed251b9bd6319cfc62d\nChange-Id: Ibbe07099e879cafc0f369404fa9dc52f8bf89855\n" }, { "commit": "a73883e3d2ad194e5551ca7ad2124c1a2a138a7a", "tree": "ac1994536fbe85a381d02d8df8822e26f4da8433", "parents": [ "1abf565a1746b22ac88b87f64f4c7e2e171c6041" ], "author": { "name": "Anthony Shaw", "email": "anthony.p.shaw@gmail.com", "time": "Mon Nov 10 11:00:20 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Nov 10 11:08:02 2025 -0800" }, "message": "Implement missing ISA feature flags for ARM64/Windows (#333)\n\n* implement SVE/SVE2 and list out the missing feature flags\n\n* Implement most of the ISA feature flags\n\n* Update notes\n\n* Add more flags to isa info\n\n* Additional flags\n\n* Add conservative values for SVE\n\n* clang formatting\n\n* format headers\n\nGitOrigin-RevId: f7b233b2755235c97ef1c2e650820ece1b2869a4\nChange-Id: Ifcc7082f77bb7f2e21e9f73b13df92ffbc3dc360\n" }, { "commit": "1abf565a1746b22ac88b87f64f4c7e2e171c6041", "tree": "238001231dfefcf08ccf0d3ea192a3f8cfd85bd2", "parents": [ "573d2beb66c72ee14d01203050753be3f22456eb" ], "author": { "name": "davidbienvenu", "email": "bienvenu@davidbienvenu.org", "time": "Fri Nov 07 16:47:29 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Nov 07 17:08:32 2025 -0800" }, "message": "Fix compile warnings in arm/windows (#323)\n\n* Update init-by-logical-sys-info.c\n\nFix compiler warnings\n\n* Update init.c\n\nfix compiler warning\n\n* reformat init.c\n\nattempt to fix clang format errors\n\n* Update init-by-logical-sys-info.c\n\n* Update init-by-logical-sys-info.c\n\nattempt to fix clang format errors\n\nGitOrigin-RevId: d3a86a813e2bb49d1eb5841ec12e2b135867ab98\nChange-Id: I140de0c2989159d90bc47d306675bb8e1f7e4297\n" }, { "commit": "573d2beb66c72ee14d01203050753be3f22456eb", "tree": "52cd45573c3fd38a2438934e969cb80fe445529a", "parents": [ "a3e063d372e3debff475d4c1050908133a3aa76a" ], "author": { "name": "Anthony Shaw", "email": "anthony.p.shaw@gmail.com", "time": "Thu Nov 06 15:01:15 2025 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 06 15:07:22 2025 -0800" }, "message": "Add missing ARM-Cortex uarchs (#335)\n\n* Add A720, 725 and X4 identifiers\n\n* Add the X4 successor as well\n\n* Add enumerators\n\nGitOrigin-RevId: f01ce870215f9e5d4c32006796994469c5334fd7\nChange-Id: I54633b3079ad6653658884ac60d5838adeead802\n" }, { "commit": "a3e063d372e3debff475d4c1050908133a3aa76a", "tree": "2097e74c54b800d3e8548e54ae436bb49628a42f", "parents": [ "df227e18ad38973b43a01a7886baf66b85a59a8d" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Thu Nov 06 15:52:45 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 06 14:58:54 2025 -0800" }, "message": "Update googletest and googlebench deps (#337)\n\nGitOrigin-RevId: 10a95e87a10ae7a7b108bd25ff8a606e53d5af74\nChange-Id: I9f0180e3c81736f5ad737b7eecb2af2d867649a6\n" }, { "commit": "df227e18ad38973b43a01a7886baf66b85a59a8d", "tree": "dc925d48911930c0868787de3b08850d4f8185a5", "parents": [ "7d848c9f2e08ed949785f93ef3f3abac6cffdd31" ], "author": { "name": "Alexander Grund", "email": "Flamefire@users.noreply.github.com", "time": "Wed Nov 05 19:10:34 2025 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Nov 05 10:37:43 2025 -0800" }, "message": "Ignore disabled hyperthreads (#291)\n\nOnly consider processors with an APIC_ID as valid.\n\nFor processors with Hyperthreads but disabled SMT the APIC_ID will never be set and stays zero for the \"disabled\" threads.\nAmong other inconsistencies this causes the first active thread/processor to be considered \"the same\" as all the disabled ones as they share `APIC_ID\u003d0`\n\nIt also doesn\u0027t make sense to make and decisions based on the APIC_ID if we don\u0027t have any information on it.\n\nGitOrigin-RevId: 0d5985d60de2512a2130eede846fc755cb222dc8\nChange-Id: I75a8f4c54c0ade0f8bf0d0dc2b9a1fc507c27751\n" }, { "commit": "7d848c9f2e08ed949785f93ef3f3abac6cffdd31", "tree": "1487014780ae9d5c62e47b1653461b66a71d2766", "parents": [ "6ba2d7a71409c649ee5b17a54f7dda08671e79c2" ], "author": { "name": "Byoungchan Lee", "email": "byoungchan.lee@gmx.com", "time": "Thu Nov 06 02:51:15 2025 +0900" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Nov 05 10:08:05 2025 -0800" }, "message": "Fix Samsung Exynos 2000 series chipset detection (#309)\n\n* Fix Samsung Exynos 2000 series chipset detection\n\nAdd support for \"s5e\" prefix pattern matching in `ro.product.board`\nproperty to correctly identify Samsung Exynos 2000 series chipsets.\nThese chipsets use generic identifiers (e.g., `s5e9925`) instead of\nmarketing names like \"Exynos 2200\", but can still be identified and\nmapped to their corresponding models using external resources.\n\nImplements `match_s5e()` function to parse the s5e\u003c4-digit-model\u003e format.\n\n* Clean up whitespace in chipset.c\n\n---------\n\nCo-authored-by: Byoungchan Lee \u003cdaniel.l@hpcnt.com\u003e\nGitOrigin-RevId: 37b484a5ce3f73f2f37977b86a74698e612936b0\nChange-Id: Iefa45150cebe22ef31b7004d68a399b2d322cb92\n" }, { "commit": "6ba2d7a71409c649ee5b17a54f7dda08671e79c2", "tree": "97803cee305c7084124e9f2ab013fd46430b2c7f", "parents": [ "f8cfd8f2dc6ba91b1b5f1576e31546bff5b2d661" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Fri Sep 05 15:55:09 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Sep 05 16:00:49 2025 -0700" }, "message": "Update CMake minimum requirements to 3.18 (#330)\n\nAs CMake 3.5 support has been removed in cmake-4.x\n\nGitOrigin-RevId: 877328f188a3c7d1fa855871a278eb48d530c4c0\nChange-Id: I63a6a720819a4a385b95afd6b4cbaaeed814bb53\n" }, { "commit": "f8cfd8f2dc6ba91b1b5f1576e31546bff5b2d661", "tree": "e3c4a4a43fbcf8e1afdf6f6b33dc5d0a14a605ea", "parents": [ "f1d3ac47cd4656ac799c3444fcd647f56d056f5e" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Fri Aug 08 07:49:05 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Aug 08 07:54:49 2025 -0700" }, "message": "Add Intel Tremont uarch (#305)\n\nTremont is the e-core (10nm Atom) in Jasperlake,Elkhart Lake, Jacobville and Lakefield\n\nThe family/model are supported by linux\nhttps://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h#L176-L178\nDocumented on wikichip\nhttps://en.wikichip.org/wiki/intel/cpuid#Small_Cores\nSupported by Intel sde -tnt\n\nReordered e-core uarch by generation\ndarkmont is an e-core used in both hybrid laptops and server, so move to ecore\ngracemont model 0xBE is confirmed for Alderlake N, so redocument support\n\nPredecessor Goldmont Plus\nSuccessor Gracemont\n\nGitOrigin-RevId: 8a9210069b5a37dd89ed118a783945502a30a4ae\nChange-Id: I817323bb13bc0039304818bcba5c0d4fbfed4c0d\n" }, { "commit": "f1d3ac47cd4656ac799c3444fcd647f56d056f5e", "tree": "78c9f73990cc3f5b20d32f1af11fbd6a160de470", "parents": [ "8e701558790b2eea8b07e29000c44e929a1245e4" ], "author": { "name": "Yuri Khrustalev", "email": "ykhrustalev@users.noreply.github.com", "time": "Tue Aug 05 13:27:21 2025 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Aug 05 10:33:37 2025 -0700" }, "message": "Add aarch64 to the windows arm list (#311)\n\nGitOrigin-RevId: e414c0446436ed34151de3158d18f8ae32e55d03\nChange-Id: I1798f459e7a8262f1f735c6394a1407bed36f73b\n" }, { "commit": "8e701558790b2eea8b07e29000c44e929a1245e4", "tree": "2c9d01e8e752507c0c986200be3699fc1f624035", "parents": [ "b8bdcfcc98748f1045518f5433abc85dd2141e7a" ], "author": { "name": "Conan Truong", "email": "Conarnar@users.noreply.github.com", "time": "Thu Jul 24 10:36:24 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jul 24 10:37:31 2025 -0700" }, "message": "Added Emscripten to list of supported systems in CMakeLists.txt (#310)\n\nGitOrigin-RevId: 33ed0be77d7767d0e2010e2c3cf972ef36c7c307\nChange-Id: I7eca34d73d29ed0ad1a4a7632298752e5a1bfc51\n" }, { "commit": "b8bdcfcc98748f1045518f5433abc85dd2141e7a", "tree": "5a5239746e2eb116fcf174a14e7a8940c31fab6b", "parents": [ "65cfc6b3e006fc13c18255aabb932279c80fef19" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Jun 25 21:30:09 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Jun 25 21:35:50 2025 -0700" }, "message": "Add Intel Gracemont uarch (#303)\n\nGitOrigin-RevId: e4cadd02a8b386c38b84f0a19eddacec3f433baa\nChange-Id: Ie8456e063fced6a09d1d25b4ed738e58e1f10aaa\n" }, { "commit": "65cfc6b3e006fc13c18255aabb932279c80fef19", "tree": "27e92522e35a8a2d5450ec333970e60fdb3561bf", "parents": [ "1736c1aa3787ac43fc2f95759a1bdc1ba02740e2" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Tue Jun 10 08:00:39 2025 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jun 10 07:07:24 2025 -0700" }, "message": "Added Willow Cove (#301)\n\n* Added Willow Cove\n\n* Update uarch.c\n\nremoved incomplete modification in naming\n\n* Update cpu-info.c\n\nmoved willow_cove up two lines to be next to sunny_cove\n\n* Update cpuinfo.h\n\nmade the enum consistent with uarch naming following sunny_cove\n\n* Update cpuinfo.h\n\nupdated comments to refer to intel microarchitecture per request to keep consistent.\n\nGitOrigin-RevId: d7427551d6531037da216d20cd36feb19ed4905f\nChange-Id: I190034a34df1b9f0c532da8833059b3a10b5a576\n" }, { "commit": "1736c1aa3787ac43fc2f95759a1bdc1ba02740e2", "tree": "38067175a8b69fb69c8f5cb6464521380dd0ae38", "parents": [ "82a59444d247a4ce45f3ba86e2032cbfe2d42938" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jun 09 14:42:28 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jun 09 14:48:09 2025 -0700" }, "message": "Add Intel Darkmont uarch (#298)\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest\n\nGitOrigin-RevId: bac1e85899d8a5663d56a1924aabcaee3de6d8d0\nChange-Id: Ibeb2cd65a9279a8174484ade6efa35c40a9e8178\n" }, { "commit": "82a59444d247a4ce45f3ba86e2032cbfe2d42938", "tree": "60b7d0e59f7f334203f1fca22ef5a41d162b0863", "parents": [ "40395f9a9df4bdecb484dcb1c993d690d3b3977d" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Tue Jun 03 09:50:51 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jun 03 09:56:32 2025 -0700" }, "message": "Disable neon dot on unknown chipsets on aarch32 (#300)\n\nGitOrigin-RevId: 6c9eb84ba310f237cea13c478be50102e1128e9b\nChange-Id: Iebe7f90d79bca6e7a5260feb99ea82bccdc1fc14\n" }, { "commit": "40395f9a9df4bdecb484dcb1c993d690d3b3977d", "tree": "a96b86a2cfd7adc30af469d4e07e95fe2b0effc2", "parents": [ "3dae116858df4616bd364536f9cc7939acda8aa9" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jun 02 09:54:50 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jun 02 10:00:27 2025 -0700" }, "message": "Add Intel Crestmont uarch (#299)\n\nDarkmont is the uarch used in Sierra Forest\nTested:\nmake cpu-info\nsde -srf -- ./cpu-info\nGitOrigin-RevId: 88b498b9d73acd0b8edb1ec1c31a8fc1cefaf2da\nChange-Id: I304d9ebd64e951d97609625bb50568c195c98772\n" }, { "commit": "3dae116858df4616bd364536f9cc7939acda8aa9", "tree": "33bfbf62a9d357c1c8b944abb36bab1f04b7c3b1", "parents": [ "b4239225c1583a97e2089388ff40466dc0324bdc" ], "author": { "name": "Kimish Patel", "email": "kimishpatel@fb.com", "time": "Thu May 29 13:26:30 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 29 13:32:27 2025 -0700" }, "message": "update apple soc info (#290)\n\n* [WIP] update apple soc info\n\nSummary:\nAdded support for A16, A17, A18, A18 pro. Reg values are found from ncnn and needs validation.\n\nAdditional source\nConstants are taken from https://github.com/apple-oss-distributions/xnu/blob/e3723e1f17661b24996789d8afc084c0c3303b26/osfmk/mach/machine.h#L449\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"update apple soc info\"\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\nGitOrigin-RevId: c61fe919607bbc534d7a5a5707bdd7041e72c5ff\nChange-Id: I596d19c1605857d430b17386c051b474621eaea8\n" }, { "commit": "b4239225c1583a97e2089388ff40466dc0324bdc", "tree": "9e73b777636aeb80236e90fe643509bcda65ea02", "parents": [ "e10d4cc77a50faa46abbf680d9df4765fdda1e3c" ], "author": { "name": "enh-google", "email": "enh@google.com", "time": "Thu May 22 20:45:30 2025 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 22 17:52:08 2025 -0700" }, "message": "riscv-hw.c: match kernel type in syscall(). (#292)\n\nsyscall() doesn\u0027t care about these types at all, and the kernel uses cpu_set_t, so we\u0027re better off just removing the cast entirely.\n\nGitOrigin-RevId: de0ce7c7251372892e53ce9bc891750d2c9a4fd8\nChange-Id: Id400ecfe03924e07641e5a55617ea1b2678fda74\n" }, { "commit": "e10d4cc77a50faa46abbf680d9df4765fdda1e3c", "tree": "22d22cf26f580cc7036fa7ac4620ccf8d4dc2296", "parents": [ "a3def0fad97da589c598fb5853562dd15e5b3872" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 16:06:17 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 22 16:07:41 2025 -0700" }, "message": "[CI] Fix riscv64-in-qemu build (#295)\n\nTried a few things, but looks like all one needs to do is to add `--platform linux/riscv64` flag to `docker run` command\n\nGitOrigin-RevId: 957b852c5ca521ecb848527a5dc3cc55274aa496\nChange-Id: I899ddaf55001b52f80909d9b0178ea58d5e019c8\n" }, { "commit": "a3def0fad97da589c598fb5853562dd15e5b3872", "tree": "fc856f7495862fb81c412c494e13975aeaefe226", "parents": [ "2c8b434bcbc924b4343893026a040f547094c73e" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 14:47:34 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 22 14:52:20 2025 -0700" }, "message": "Revert \"cmake: rename duplicate names\" (#296)\n\nReverts pytorch/cpuinfo#284 as it broke Bazel builds\n\nGitOrigin-RevId: 905918fe9c2a335e99a7092dc028dee927a103a0\nChange-Id: Ic4bffbd34e7b5fd51cd05af63104d080f11fda5a\n" }, { "commit": "2c8b434bcbc924b4343893026a040f547094c73e", "tree": "e59222f835b15f954870c25b23cf689e443255b1", "parents": [ "1d68e46648e9071eb1761c28e2b0933e34a458b0" ], "author": { "name": "Nikita Shulga", "email": "nshulga@meta.com", "time": "Thu May 22 14:08:46 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 22 14:15:07 2025 -0700" }, "message": "[CI] Update checkout action to v4\n\nGitOrigin-RevId: 4ab5a589708c6aa9ceb561fb2a6506374107da21\nChange-Id: Ie22b51619003083c1ee5469f209a32f8ee95ba1e\n" }, { "commit": "1d68e46648e9071eb1761c28e2b0933e34a458b0", "tree": "1ac3bfa22e9938bc2cec4bff0275e6b5c3b3f00c", "parents": [ "9a66575f81923231312e0674e5b69a0094b48fea" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 08:27:53 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu May 22 08:33:46 2025 -0700" }, "message": "Fix clang format (#294)\n\nRegressions introduced by https://github.com/pytorch/cpuinfo/pull/275 and https://github.com/pytorch/cpuinfo/pull/287\n\nGitOrigin-RevId: 1961df8470beebffa5d82b99b9b9e430436b8d34\nChange-Id: Ic905191103bc49c1cda783c3f13384a5ef551833\n" }, { "commit": "9a66575f81923231312e0674e5b69a0094b48fea", "tree": "db39ceced06fc219acde1d30b5b90e9262085787", "parents": [ "06e91ad7a5e48c40c6c5aea24dd8bea86fdee5eb" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu May 22 00:18:27 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed May 21 22:24:02 2025 -0700" }, "message": "Merge pull request #284 from 1480c1/xcode\n\nGitOrigin-RevId: 48a5942c92a3d0590873f1fdfbe1ce3a66412afe\nChange-Id: Ifc4e8cae156721ceb349b2cad23700f5d62e0d2e\n" }, { "commit": "06e91ad7a5e48c40c6c5aea24dd8bea86fdee5eb", "tree": "a4352366aebce3c7c486d1733333f41403245cc3", "parents": [ "76e74b9987338af7c59bf36e9d82418ec09cd502" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu May 22 00:17:38 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed May 21 22:23:56 2025 -0700" }, "message": "Merge pull request #287 from fbarchard/smelen\n\nGitOrigin-RevId: b728a23da00ff511275eeaec0122bf28db00fd59\nChange-Id: If5b4110bb6b4f9c02c8e54c89b473874968c5e27\n" }, { "commit": "76e74b9987338af7c59bf36e9d82418ec09cd502", "tree": "1a6a0ea6ffbad28509c06440f6e42cd2dfec3c81", "parents": [ "ceb4ebf2fb2aad9de0a9a88d6822bbc29d17e071" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Mar 27 11:18:57 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Mar 27 09:24:46 2025 -0700" }, "message": "Merge pull request #285 from fbarchard/sme2\n\nisa-tool display SME and SME2 for arm\n\nGitOrigin-RevId: 39ea79a3c132f4e678695c579ea9353d2bd29968\nChange-Id: If44c891b94d93feff733d295d1f4425696e50d38\n" }, { "commit": "ceb4ebf2fb2aad9de0a9a88d6822bbc29d17e071", "tree": "3bfef867252f51b318655b76b81bc02aec356e25", "parents": [ "db43e000e7bca618ffc35407b7e7f752842944f1" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Fri Mar 21 02:07:22 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Mar 21 00:13:06 2025 -0700" }, "message": "Merge pull request #246 from dlenski/main\n\nFor Apple silicon, use machdep.cpu.brand_string in preference to decoding hw.machine\n\nGitOrigin-RevId: 5e3d2445e6a84d9599bee2bf78edbb4d80865e1d\nChange-Id: I8fb92d8cbd4e7e05c5cdd2d82df983b59833ff8e\n" }, { "commit": "db43e000e7bca618ffc35407b7e7f752842944f1", "tree": "103eb5f3a28c711884fb939ebd77c56cc958344f", "parents": [ "776f4b6b1d34a36e67d90afd5093f7f073fd767e" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Fri Mar 21 01:53:40 2025 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Mar 21 00:00:22 2025 -0700" }, "message": "Merge pull request #275 from davidben/func-cast\n\nFix invalid function pointer cast in cpuinfo.c\n\nGitOrigin-RevId: 1a02246bf5af7e9d07c181f995d2a07c07fc6e50\nChange-Id: If79c07bb1e78c2d4c24bcec9b577e7477a0a637f\n" }, { "commit": "776f4b6b1d34a36e67d90afd5093f7f073fd767e", "tree": "023bfea60ea123fc90104de34a8e27fcadf3013e", "parents": [ "6d1339a3d74c5ed9b737b81695ec3680b58244e9" ], "author": { "name": "Eli Uriegas", "email": "1700823+seemethere@users.noreply.github.com", "time": "Thu Mar 20 10:01:21 2025 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Mar 20 10:08:02 2025 -0700" }, "message": "Merge pull request #283 from ozanMSFT/users/ozanMSFT/refactor-chip-detection\n\nRefactor windows arm64 for auto cpu detection\n\nGitOrigin-RevId: d6120c73cb6d02f7dac3f2a85f5690fc91f33dbd\nChange-Id: Id15abbc4d97110d1f1b276e14e48c637d4b33403\n" }, { "commit": "6d1339a3d74c5ed9b737b81695ec3680b58244e9", "tree": "6955bdec88cbfbabfc96d86a3ba05866cf1764ac", "parents": [ "c8b0bf3cbf4f9a02d9f1a439716c51265e78957e" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Tue Feb 18 21:41:25 2025 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Feb 18 19:47:12 2025 -0800" }, "message": "Merge pull request #277 from 1480c1/pkg-config-name\n\npkg-config: use PROJECT_NAME instead of CMAKE_PROJECT_NAME\nGitOrigin-RevId: b73ae6ce38d5dd0b7fe46dbe0a4b5f4bab91c7ea\nChange-Id: I15326d1b69347e0ff0ef1fcd6f99581bbe37906a\n" }, { "commit": "c8b0bf3cbf4f9a02d9f1a439716c51265e78957e", "tree": "1de074e429080f0b4debeea04bc178a17d1304dd", "parents": [ "78a47fd53b147a7d2aa476b45c3f74a901225a2f" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Mon Feb 03 17:30:36 2025 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Feb 03 15:37:53 2025 -0800" }, "message": "Merge pull request #276 from rrwinterton/main\n\nGitOrigin-RevId: aaac07ee499895770c89163ce0920ef8bb41ed23\nChange-Id: I1ad700ac665da588998d7785d3fb1cc8e7343861\n" }, { "commit": "78a47fd53b147a7d2aa476b45c3f74a901225a2f", "tree": "70e274d4ae04d9cbb6654feb01ab75d884c8de6d", "parents": [ "b07f85c69439f3510759c6e2c917f4afa1b79d61" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Jan 09 18:25:44 2025 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jan 09 16:31:31 2025 -0800" }, "message": "Merge pull request #269 from rrwinterton/main\n\nAdded changes to support AVX 10.1 support\n\nGitOrigin-RevId: 8a1772a0c5c447df2d18edf33ec4603a8c9c04a6\nChange-Id: Ia0804377913c5cf94c811d85c34abe4b46736b88\n" }, { "commit": "b07f85c69439f3510759c6e2c917f4afa1b79d61", "tree": "d23a11db8b3df36e7ec29452bee7d77cb3213b84", "parents": [ "c1a66bbcf353974abbaf5df59c3fe9ea377bafa9" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Mon Dec 09 10:55:38 2024 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Dec 09 09:01:43 2024 -0800" }, "message": "Merge pull request #268 from gonnet/ampere_altra\n\nSet the correct L2 size for Ampere Altra (`aarch64`).\n\nGitOrigin-RevId: ca156f7bc9109c552973414a63d310f76ef0cbf8\nChange-Id: I4240dd9ba867e837dee0995ad641be99fff34115\n" }, { "commit": "c1a66bbcf353974abbaf5df59c3fe9ea377bafa9", "tree": "7d11ca9023129472ef690d1d57557f1287121b25", "parents": [ "c2ccbc0c6dcabcd53868b266c5ce15ce53771e94" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Nov 14 09:03:13 2024 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 14 09:09:37 2024 -0800" }, "message": "Merge pull request #266 from fbarchard/zen5\n\nGitOrigin-RevId: cebb0933058d7f181c979afd50601dc311e1bf8c\nChange-Id: I4768168c954aa01ffa1d13283757ce2bf54c1ec6\n" }, { "commit": "c2ccbc0c6dcabcd53868b266c5ce15ce53771e94", "tree": "a959f199181a4c37d7637ed68f9be5aafbe9c6df", "parents": [ "ddc002d8475ab64ff63eebd85bff6159f49bf7ac" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Mon Oct 28 23:44:11 2024 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Oct 28 23:50:07 2024 -0700" }, "message": "Merge pull request #265 from GregoryComer/ums312-dot-disable\n\nDisable neon dot on Unisoc UMS312\n\nGitOrigin-RevId: 8df44962d437a0477f07ba6b8843d0b6a48646a4\nChange-Id: I7d55488c49a262813b87ba10302fb4e66e45ee2d\n" }, { "commit": "ddc002d8475ab64ff63eebd85bff6159f49bf7ac", "tree": "f4090e25ed5c80dba1fd7c966e92178e5a69d087", "parents": [ "b7e98eaae7af37cc4f4eb1c8e21e9d460d3df1b6" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Tue Oct 22 10:13:39 2024 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Oct 22 08:20:02 2024 -0700" }, "message": "Merge pull request #264 from gonnet/sme-for-mach\n\nGitOrigin-RevId: dff2616ddd49122b63abcf44d2c097483b77f861\nChange-Id: I9e59cbdec7b732dcadde00dd1926038030a67b57\n" }, { "commit": "b7e98eaae7af37cc4f4eb1c8e21e9d460d3df1b6", "tree": "fa9fe8f8123cf2adf263a2a7e851a1ddc361aa0b", "parents": [ "f853a805a70d3159f8d18a963ebdfa8f86ad4d7f" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Sep 26 08:43:26 2024 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Sep 26 08:49:03 2024 -0700" }, "message": "Merge pull request #262 from gonnet/main\n\nAdd `sme2` detection for `aarch64`\n\nGitOrigin-RevId: 1e83a2fdd3102f65c6f1fb602c1b320486218a99\nChange-Id: I58c80154c0745ff3b23a67bc2425d58cc5355214\n" }, { "commit": "f853a805a70d3159f8d18a963ebdfa8f86ad4d7f", "tree": "b4135621047e274f9445cb7b9bf0a24713242bc0", "parents": [ "7da24f3126963e2f446a8b0be6bf64f3ecb638b1" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Wed Sep 11 12:04:16 2024 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Sep 11 10:07:54 2024 -0700" }, "message": "Merge pull request #258 from maajidkhann/fix_cpuinfo_sve_bug\n\nFixes the cpuinfo_get_max_arm_sve_length API bug on NON-SVE supported hardware.\n\nGitOrigin-RevId: a5ff6df40ce528721cfc310c7ed43946d77404d5\nChange-Id: I486500ffd2abe18a6af8ced39a3e7daf9e753e97\n" }, { "commit": "7da24f3126963e2f446a8b0be6bf64f3ecb638b1", "tree": "e205177f2b7b6eebf1104eeb8c09ac43814aa773", "parents": [ "3d7dbdd3959a5f5a776b702fa954017c716dffab" ], "author": { "name": "cyyever", "email": "cyyever@outlook.com", "time": "Fri Aug 30 23:56:51 2024 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Aug 30 08:59:49 2024 -0700" }, "message": "More robust FreeBSD topology detection (#249)\n\nPossibly fix #248\n\nGitOrigin-RevId: fa1c679da8d19e1d87f20175ae1ec10995cd3dd3\nChange-Id: I9a922bf98199feca294084b77a03c255f5162724\n" }, { "commit": "3d7dbdd3959a5f5a776b702fa954017c716dffab", "tree": "6bef8aa0a270e1dfb7e38f22005747b86a0459bb", "parents": [ "3e10641c8fa672aab0522e907771eddaa1cd2a32" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Fri Aug 30 08:55:08 2024 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Aug 30 08:59:44 2024 -0700" }, "message": "Add android-riscv64 build to workflows (#256)\n\nThe Android NDK supports building for RISC-V as of version r27. Add it\nto the build workflows here to improve coverage of the RISC-V code.\n\nFixes: #206\nGitOrigin-RevId: 4611eb986ce5c04b8266241bc0b77ff1925636d8\nChange-Id: I899b31c834b8820d4c43795ef3d6f885cb8990e9\n" }, { "commit": "3e10641c8fa672aab0522e907771eddaa1cd2a32", "tree": "e24f949631bed96aa3d4999e7d0f6d3e1e549d45", "parents": [ "ccd85721d67bce0e6a6a421bf6b45b9765ede80b" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Fri Aug 30 17:53:58 2024 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Aug 30 08:59:38 2024 -0700" }, "message": "Add detection for `sme` on `aarch64`. (#257)\n\nThis is based on the ARM ComputeLibrary implementation [here](https://github.com/ARM-software/ComputeLibrary/blob/f1929dc994d8e5afae5c77ca66446344119a8592/src/common/cpuinfo/CpuIsaInfo.cpp#L75).\n\nGitOrigin-RevId: 209b00cba26583cb8271741aa5f3e267ee7167d0\nChange-Id: I135e865baaa958c342a6b5b1c05240313af29f90\n" }, { "commit": "ccd85721d67bce0e6a6a421bf6b45b9765ede80b", "tree": "d61c5e9b5278aadfefadee77d27e36db544345af", "parents": [ "9606f1e4c60bf5430b1d21a654f153c029dfb905" ], "author": { "name": "MaajidKhan", "email": "maajidkhan.n@fujitsu.com", "time": "Wed Aug 07 20:33:44 2024 +0530" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 07 08:07:46 2024 -0700" }, "message": "Add a API to check SVE Length support on ARM CPU. (#255)\n\nThis pull request introduces a new feature to the cpuinfo library that adds an API to return the maximum supported Scalable Vector Extension (SVE) vector length on the given ARM CPU. This enhancement will allow users to query and determine the maximum SVE vector lengths on a given ARM CPU, providing better insights and flexibility for optimizing applications that utilize SVE.\n\n**Key Features:**\n**New API Function:**\n\nIntroduces a single API function - cpuinfo_get_max_arm_sve_length() that returns the maximum SVE Vector Length supported on the given ARM CPU.\n\nThe function is designed to be easy to integrate with existing code in other projects like PyTorch (https://github.com/pytorch/pytorch/pull/119571/) and provides a straightforward interface for querying SVE VL.\n\n**Here\u0027s the sample output on SVE supported instance:**\n\n**Query:**\n![test_cpp_aug7](https://github.com/user-attachments/assets/0f55fa37-cf54-4fbf-b1bc-a34a27139869)\n\n**Output on SVE256 supported Hardware - Graviton3:**\n![test_cpp_output](https://github.com/user-attachments/assets/bef72357-dadd-43e9-8983-33248205782f)\n\nSigned-off-by: maajidkhann \u003cmaajidkhan.n@fujitsu.com\u003e\nGitOrigin-RevId: 16bfc1622c6902d6f91d316ec54894910c620325\nChange-Id: Ic95937c3073af0f03f8476cdc7cdcc9879316cdc\n" }, { "commit": "9606f1e4c60bf5430b1d21a654f153c029dfb905", "tree": "5fc1e4c594a2dbe1a8627530f78cd8a29f8a8371", "parents": [ "34d039b5d46caeb772d5088311740a3c089a3a00" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Tue Jul 09 22:36:59 2024 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jul 09 20:38:10 2024 -0700" }, "message": "Merge pull request #252 from fbarchard/cortex_x4\n\nAdd Cortex X4, A720 and A520\n\nGitOrigin-RevId: ca678952a9a8eaa6de112d154e8e104b22f9ab3f\nChange-Id: I904e0fd738fe02b28ef40f5062e849e972b6e6ea\n" }, { "commit": "34d039b5d46caeb772d5088311740a3c089a3a00", "tree": "e9bfeda231f882e66aa08b4452534ea1ddc78743", "parents": [ "ac7c2ae577ba905f73744f0aa7e61e1ecfc4549f" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Tue Jul 09 22:36:32 2024 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jul 09 20:38:04 2024 -0700" }, "message": "Merge pull request #240 from prashanthswami/use-cluster-cpus\n\nUse cluster_cpus_list to detect clusters for ARM\n\nGitOrigin-RevId: 2ceea8a437b6859bea1372f0b634a88110ba66ba\nChange-Id: I4d668f6c5ee216157062c1cbc4317e4a1a515ada\n" }, { "commit": "ac7c2ae577ba905f73744f0aa7e61e1ecfc4549f", "tree": "eb7375e388dc27c01f988115bd3a98f038398f53", "parents": [ "83c4800c21959581039067d2adacc21b8b35b530" ], "author": { "name": "cyyever", "email": "cyyever@outlook.com", "time": "Mon Jun 03 00:13:58 2024 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sun Jun 02 09:20:03 2024 -0700" }, "message": "add FreeBSD support (#172)\n\nGitOrigin-RevId: 05332fd802d9109a2a151ec32154b107c1e5caf9\nChange-Id: Id33f77815fd4f28565c8346076b426af35429e05\n" }, { "commit": "83c4800c21959581039067d2adacc21b8b35b530", "tree": "148ca8d922151abdab55df1fda200a1e7e5c9a1e", "parents": [ "50d2114fc59949a6848172573f093a70617bfd8a" ], "author": { "name": "Ma Mingfei", "email": "mingfei.ma@intel.com", "time": "Wed Apr 17 23:29:37 2024 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Apr 17 08:35:17 2024 -0700" }, "message": "add detection for intel new isa: avx_ne_convert, avx_vnni_int8, avx_vnni_int16 (#232)\n\nTest Plan:\n```\nbash scripts/local-build.sh\n\nISAS\u003d()\nOPTIONS\u003d()\nPLATFORMS\u003d()\n\nOPTIONS+\u003d(-quark); PLATFORMS+\u003d(\"Quark\")\nOPTIONS+\u003d(-p4); PLATFORMS+\u003d(\"Pentium4\")\nOPTIONS+\u003d(-p4p); PLATFORMS+\u003d(\"Pentium4 Prescott\")\nOPTIONS+\u003d(-mrm); PLATFORMS+\u003d(\"Merom\")\nOPTIONS+\u003d(-pnr); PLATFORMS+\u003d(\"Penryn\")\nOPTIONS+\u003d(-nhm); PLATFORMS+\u003d(\"Nehalem\")\nOPTIONS+\u003d(-wsm); PLATFORMS+\u003d(\"Westmere\")\nOPTIONS+\u003d(-snb); PLATFORMS+\u003d(\"Sandy Bridge\")\nOPTIONS+\u003d(-ivb); PLATFORMS+\u003d(\"Ivy Bridge\")\nOPTIONS+\u003d(-hsw); PLATFORMS+\u003d(\"Haswell\")\nOPTIONS+\u003d(-bdw); PLATFORMS+\u003d(\"Broadwell\")\nOPTIONS+\u003d(-slt); PLATFORMS+\u003d(\"Saltwell\")\nOPTIONS+\u003d(-slm); PLATFORMS+\u003d(\"Silvermont\")\nOPTIONS+\u003d(-glm); PLATFORMS+\u003d(\"Goldmont\")\nOPTIONS+\u003d(-glp); PLATFORMS+\u003d(\"Goldmont Plus\")\nOPTIONS+\u003d(-tnt); PLATFORMS+\u003d(\"Tremont\")\nOPTIONS+\u003d(-snr); PLATFORMS+\u003d(\"Snow Ridge\")\nOPTIONS+\u003d(-skl); PLATFORMS+\u003d(\"Skylake\")\nOPTIONS+\u003d(-cnl); PLATFORMS+\u003d(\"Cannon Lake\")\nOPTIONS+\u003d(-icl); PLATFORMS+\u003d(\"Ice Lake\")\nOPTIONS+\u003d(-skx); PLATFORMS+\u003d(\"Skylake server\")\nOPTIONS+\u003d(-clx); PLATFORMS+\u003d(\"Cascade Lake\")\nOPTIONS+\u003d(-cpx); PLATFORMS+\u003d(\"Cooper Lake\")\nOPTIONS+\u003d(-icx); PLATFORMS+\u003d(\"Ice Lake server\")\nOPTIONS+\u003d(-knl); PLATFORMS+\u003d(\"Knights landing\")\nOPTIONS+\u003d(-knm); PLATFORMS+\u003d(\"Knights mill\")\nOPTIONS+\u003d(-tgl); PLATFORMS+\u003d(\"Tiger Lake\")\nOPTIONS+\u003d(-adl); PLATFORMS+\u003d(\"Alder Lake\")\nOPTIONS+\u003d(-mtl); PLATFORMS+\u003d(\"Meteor Lake\")\nOPTIONS+\u003d(-rpl); PLATFORMS+\u003d(\"Raptor Lake\")\nOPTIONS+\u003d(-spr); PLATFORMS+\u003d(\"Sapphire Rapids\")\nOPTIONS+\u003d(-gnr); PLATFORMS+\u003d(\"Granite Rapids\")\nOPTIONS+\u003d(-gnr256); PLATFORMS+\u003d(\"Granite Rapids (AVX10.1 / 256VL)\")\nOPTIONS+\u003d(-srf); PLATFORMS+\u003d(\"Sierra Forest\")\nOPTIONS+\u003d(-arl); PLATFORMS+\u003d(\"Arrow Lake\")\nOPTIONS+\u003d(-lnl); PLATFORMS+\u003d(\"Lunar Lake\")\nOPTIONS+\u003d(-future); PLATFORMS+\u003d(\"Future chip\")\n\nISAS+\u003d(\"AVX_VNNI_INT8\")\nISAS+\u003d(\"AVX_VNNI_INT16\")\nISAS+\u003d(\"AVX_NE_CONVERT\")\n\nSDE_BIN\u003d\"/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde\"\n\nfor I in \"${!PLATFORMS[@]}\"; do\n echo \"${PLATFORMS[\"${I}\"]}\"\n for J in \"${!ISAS[@]}\"; do\n \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep ${ISAS[$J]}\n done\ndone\n```\n\nResults:\n```\nQuark\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nPentium4\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nPentium4 Prescott\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nMerom\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nPenryn\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nNehalem\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nWestmere\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSandy Bridge\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nIvy Bridge\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nHaswell\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nBroadwell\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSaltwell\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSilvermont\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nGoldmont\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nGoldmont Plus\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nTremont\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSnow Ridge\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSkylake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nCannon Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nIce Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSkylake server\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nCascade Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nCooper Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nIce Lake server\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nKnights landing\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nKnights mill\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nTiger Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nAlder Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nMeteor Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nRaptor Lake\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSapphire Rapids\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nGranite Rapids\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nGranite Rapids (AVX10.1 / 256VL)\n AVX_VNNI_INT8: no\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: no\nSierra Forest\n AVX_VNNI_INT8: yes\n AVX_VNNI_INT16: no\n AVX_NE_CONVERT: yes\nArrow Lake\n AVX_VNNI_INT8: yes\n AVX_VNNI_INT16: yes\n AVX_NE_CONVERT: yes\nLunar Lake\n AVX_VNNI_INT8: yes\n AVX_VNNI_INT16: yes\n AVX_NE_CONVERT: yes\nFuture chip\n AVX_VNNI_INT8: yes\n AVX_VNNI_INT16: yes\n AVX_NE_CONVERT: yes\n```\nGitOrigin-RevId: 3c8b1533ac03dd6531ab6e7b9245d488f13a82a5\nChange-Id: I4bc362f7ddb4837143fbccd3dc93ad1eba056ac9\n" }, { "commit": "50d2114fc59949a6848172573f093a70617bfd8a", "tree": "68072173807a976f9e567b9265e619a075a0ae3c", "parents": [ "53526aa1f57a1b71554343b5a9d080fe6470c9c9" ], "author": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Wed Apr 17 16:16:56 2024 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Apr 17 07:22:38 2024 -0700" }, "message": "Fixing Ampere Altra Processor detection (#237)\n\n**Summary:**\n\nResolves #236\n\nAlso related to [PR 220](https://github.com/pytorch/cpuinfo/pull/220) change.\n\n```\n\"Unknown chip model name \u0027Ampere(R) Altra(R) Processor\u0027.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!\"\n```\n\n---\n\n**Previous error details:**\n\nThe error\u0027s reason was:\n\n`woa_chip_name` (`windows-arm-init.h`) enum had only 4 elements (stored in `woa_chip_name_last`)\n\n```c\nenum woa_chip_name {\n\twoa_chip_name_microsoft_sq_1 \u003d 0,\n\twoa_chip_name_microsoft_sq_2 \u003d 1,\n\twoa_chip_name_microsoft_sq_3 \u003d 2,\n\twoa_chip_name_ampere_altra \u003d 3,\n\twoa_chip_name_unknown \u003d 4,\n\twoa_chip_name_last \u003d woa_chip_name_unknown\n};\n```\n\nHowever, `woa_chips[]` (`init.c`) has a duplicated value for `woa_chip_name_microsoft_sq_3` due to different strings for same target after the [PR 220](https://github.com/pytorch/cpuinfo/pull/220)\n\n\u003e Strings are `Snapdragon (TM) 8cx Gen 3` and `Snapdragon Compute Platform`\n\nAnd this was causing following `for loop` (`init.c`) is not checking for all elements in `woa_chips[]`.\n\n```c\nfor (uint32_t i \u003d 0; i \u003c (uint32_t)woa_chip_name_last; i++) {\n\tsize_t compare_length \u003d wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX);\n\tint compare_result \u003d wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length);\n\tif (compare_result \u003d\u003d 0) {\n\t\tchip_info \u003d woa_chips + i;\n\t\tbreak;\n\t}\n}\n```\n\n---\n\n**Fix Details:**\n\nWe added `woa_chip_name_microsoft_sq_3_devkit` to maintain **one to one** relationship between `woa_chip_name` (`windows-arm-init.h`) and `woa_chips[]` (`init.c`).\n\nAlso, we especially specified indexes with `enums` to prevent future duplications and increase readability of the code and relationship.\n\nGitOrigin-RevId: 5de5c70fedc26e4477d14fdaad0e4eb5f354400b\nChange-Id: I8f72a0b1cd1304d454b49d00498d34ac843de498\n" }, { "commit": "53526aa1f57a1b71554343b5a9d080fe6470c9c9", "tree": "f5cd28e29f01eba08762cc4686aabcfb176d9e54", "parents": [ "101874091278c7ceb1916f525e5ed90fcbe40dd2" ], "author": { "name": "Ma Mingfei", "email": "mingfei.ma@intel.com", "time": "Thu Mar 28 14:03:24 2024 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Mar 27 23:08:11 2024 -0700" }, "message": "Add detection for Intel Advanced Matrix Extensions (AMX) instructions (#231)\n\nTested using intel SDE: https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html\n\nTest scripts:\n```\nbash scripts/local-build.sh\n\nISAS\u003d()\nOPTIONS\u003d()\nPLATFORMS\u003d()\n\nOPTIONS+\u003d(-quark); PLATFORMS+\u003d(\"Quark\")\nOPTIONS+\u003d(-p4); PLATFORMS+\u003d(\"Pentium4\")\nOPTIONS+\u003d(-p4p); PLATFORMS+\u003d(\"Pentium4 Prescott\")\nOPTIONS+\u003d(-mrm); PLATFORMS+\u003d(\"Merom\")\nOPTIONS+\u003d(-pnr); PLATFORMS+\u003d(\"Penryn\")\nOPTIONS+\u003d(-nhm); PLATFORMS+\u003d(\"Nehalem\")\nOPTIONS+\u003d(-wsm); PLATFORMS+\u003d(\"Westmere\")\nOPTIONS+\u003d(-snb); PLATFORMS+\u003d(\"Sandy Bridge\")\nOPTIONS+\u003d(-ivb); PLATFORMS+\u003d(\"Ivy Bridge\")\nOPTIONS+\u003d(-hsw); PLATFORMS+\u003d(\"Haswell\")\nOPTIONS+\u003d(-bdw); PLATFORMS+\u003d(\"Broadwell\")\nOPTIONS+\u003d(-slt); PLATFORMS+\u003d(\"Saltwell\")\nOPTIONS+\u003d(-slm); PLATFORMS+\u003d(\"Silvermont\")\nOPTIONS+\u003d(-glm); PLATFORMS+\u003d(\"Goldmont\")\nOPTIONS+\u003d(-glp); PLATFORMS+\u003d(\"Goldmont Plus\")\nOPTIONS+\u003d(-tnt); PLATFORMS+\u003d(\"Tremont\")\nOPTIONS+\u003d(-snr); PLATFORMS+\u003d(\"Snow Ridge\")\nOPTIONS+\u003d(-skl); PLATFORMS+\u003d(\"Skylake\")\nOPTIONS+\u003d(-cnl); PLATFORMS+\u003d(\"Cannon Lake\")\nOPTIONS+\u003d(-icl); PLATFORMS+\u003d(\"Ice Lake\")\nOPTIONS+\u003d(-skx); PLATFORMS+\u003d(\"Skylake server\")\nOPTIONS+\u003d(-clx); PLATFORMS+\u003d(\"Cascade Lake\")\nOPTIONS+\u003d(-cpx); PLATFORMS+\u003d(\"Cooper Lake\")\nOPTIONS+\u003d(-icx); PLATFORMS+\u003d(\"Ice Lake server\")\nOPTIONS+\u003d(-knl); PLATFORMS+\u003d(\"Knights landing\")\nOPTIONS+\u003d(-knm); PLATFORMS+\u003d(\"Knights mill\")\nOPTIONS+\u003d(-tgl); PLATFORMS+\u003d(\"Tiger Lake\")\nOPTIONS+\u003d(-adl); PLATFORMS+\u003d(\"Alder Lake\")\nOPTIONS+\u003d(-mtl); PLATFORMS+\u003d(\"Meteor Lake\")\nOPTIONS+\u003d(-rpl); PLATFORMS+\u003d(\"Raptor Lake\")\nOPTIONS+\u003d(-spr); PLATFORMS+\u003d(\"Sapphire Rapids\")\nOPTIONS+\u003d(-gnr); PLATFORMS+\u003d(\"Granite Rapids\")\nOPTIONS+\u003d(-gnr256); PLATFORMS+\u003d(\"Granite Rapids (AVX10.1 / 256VL)\")\nOPTIONS+\u003d(-srf); PLATFORMS+\u003d(\"Sierra Forest\")\nOPTIONS+\u003d(-arl); PLATFORMS+\u003d(\"Arrow Lake\")\nOPTIONS+\u003d(-lnl); PLATFORMS+\u003d(\"Lunar Lake\")\nOPTIONS+\u003d(-future); PLATFORMS+\u003d(\"Future chip\")\n\nISAS+\u003d(\"AMXBF16\")\nISAS+\u003d(\"AMXTILE\")\nISAS+\u003d(\"AMXINT8\")\nISAS+\u003d(\"AMXFP16\")\n\nSDE_BIN\u003d\"/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde\"\n\nfor I in \"${!PLATFORMS[@]}\"; do\n echo \"${PLATFORMS[\"${I}\"]}\"\n for J in \"${!ISAS[@]}\"; do\n \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep ${ISAS[$J]}\n done\ndone\n```\n\nResults:\n```\nQuark\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\nPentium4\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\nPentium4 Prescott\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nMerom\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nPenryn\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nNehalem\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nWestmere\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSandy Bridge\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nIvy Bridge\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nHaswell\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nBroadwell\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSaltwell\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSilvermont\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nGoldmont\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nGoldmont Plus\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nTremont\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSnow Ridge\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSkylake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nCannon Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nIce Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSkylake server\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nCascade Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nCooper Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nIce Lake server\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nKnights landing\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nKnights mill\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nTiger Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nAlder Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nMeteor Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nRaptor Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nSapphire Rapids\n AMXBF16: yes\n AMXTILE: yes\n AMXINT8: yes\n AMXFP16: no\nGranite Rapids\n AMXBF16: yes\n AMXTILE: yes\n AMXINT8: yes\n AMXFP16: yes\nGranite Rapids (AVX10.1 / 256VL)\n AMXBF16: yes\n AMXTILE: yes\n AMXINT8: yes\n AMXFP16: yes\nSierra Forest\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nArrow Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nLunar Lake\n AMXBF16: no\n AMXTILE: no\n AMXINT8: no\n AMXFP16: no\nFuture chip\n AMXBF16: yes\n AMXTILE: yes\n AMXINT8: yes\n AMXFP16: yes\n```\nGitOrigin-RevId: f42f5eaf0bbeabd3a1153651cd2a5989faac4f58\nChange-Id: I8dc2881ec66e690f3d49b4d89f23aa604a1a0e0f\n" }, { "commit": "101874091278c7ceb1916f525e5ed90fcbe40dd2", "tree": "88d14cc5f0560f096af9b08a3e51bf3df0cb389a", "parents": [ "96775f8ac60f47fc8c09485a98ae24299b928515" ], "author": { "name": "Everton Constantino", "email": "everton.constantino@linaro.org", "time": "Sat Mar 16 21:45:01 2024 -0300" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Mar 16 17:51:08 2024 -0700" }, "message": "Include support for Windows on Arm on BUILD.bazel along with proper Volterra detection (#220)\n\nThis MR includes support for building with Bazel on cpu `arm64_windows`, I also tried this on my Volterra Windows Dev Kit and noticed that the core string seems different from what the current source code defines. I don\u0027t know if this is because my hardware is a bit different or not.\n\nI ran the tests with the following results\n\n```\n[\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d] Running 132 tests from 28 test suites.\n[----------] Global test environment set-up.\n[----------] 1 test from PROCESSORS_COUNT\n[ RUN ] PROCESSORS_COUNT.non_zero\n[ OK ] PROCESSORS_COUNT.non_zero (0 ms)\n[----------] 1 test from PROCESSORS_COUNT (0 ms total)\n\n[----------] 1 test from PROCESSORS\n[ RUN ] PROCESSORS.non_null\n[ OK ] PROCESSORS.non_null (0 ms)\n[----------] 1 test from PROCESSORS (0 ms total)\n\n[----------] 13 tests from PROCESSOR\n[ RUN ] PROCESSOR.non_null\n[ OK ] PROCESSOR.non_null (0 ms)\n[ RUN ] PROCESSOR.valid_smt_id\n[ OK ] PROCESSOR.valid_smt_id (0 ms)\n[ RUN ] PROCESSOR.valid_core\n[ OK ] PROCESSOR.valid_core (0 ms)\n[ RUN ] PROCESSOR.consistent_core\n[ OK ] PROCESSOR.consistent_core (0 ms)\n[ RUN ] PROCESSOR.valid_cluster\n[ OK ] PROCESSOR.valid_cluster (0 ms)\n[ RUN ] PROCESSOR.consistent_cluster\n[ OK ] PROCESSOR.consistent_cluster (0 ms)\n[ RUN ] PROCESSOR.valid_package\n[ OK ] PROCESSOR.valid_package (0 ms)\n[ RUN ] PROCESSOR.consistent_package\n[ OK ] PROCESSOR.consistent_package (0 ms)\n[ RUN ] PROCESSOR.consistent_l1i\n[ OK ] PROCESSOR.consistent_l1i (0 ms)\n[ RUN ] PROCESSOR.consistent_l1d\n[ OK ] PROCESSOR.consistent_l1d (0 ms)\n[ RUN ] PROCESSOR.consistent_l2\n[ OK ] PROCESSOR.consistent_l2 (0 ms)\n[ RUN ] PROCESSOR.consistent_l3\n[ OK ] PROCESSOR.consistent_l3 (0 ms)\n[ RUN ] PROCESSOR.consistent_l4\n[ OK ] PROCESSOR.consistent_l4 (0 ms)\n[----------] 13 tests from PROCESSOR (7 ms total)\n\n[----------] 1 test from CORES_COUNT\n[ RUN ] CORES_COUNT.within_bounds\n[ OK ] CORES_COUNT.within_bounds (0 ms)\n[----------] 1 test from CORES_COUNT (0 ms total)\n\n[----------] 1 test from CORES\n[ RUN ] CORES.non_null\n[ OK ] CORES.non_null (0 ms)\n[----------] 1 test from CORES (0 ms total)\n\n[----------] 10 tests from CORE\n[ RUN ] CORE.non_null\n[ OK ] CORE.non_null (0 ms)\n[ RUN ] CORE.non_zero_processors\n[ OK ] CORE.non_zero_processors (0 ms)\n[ RUN ] CORE.consistent_processors\n[ OK ] CORE.consistent_processors (0 ms)\n[ RUN ] CORE.valid_core_id\n[ OK ] CORE.valid_core_id (0 ms)\n[ RUN ] CORE.valid_cluster\n[ OK ] CORE.valid_cluster (0 ms)\n[ RUN ] CORE.consistent_cluster\n[ OK ] CORE.consistent_cluster (0 ms)\n[ RUN ] CORE.valid_package\n[ OK ] CORE.valid_package (0 ms)\n[ RUN ] CORE.consistent_package\n[ OK ] CORE.consistent_package (0 ms)\n[ RUN ] CORE.known_vendor\n[ OK ] CORE.known_vendor (0 ms)\n[ RUN ] CORE.known_uarch\n[ OK ] CORE.known_uarch (0 ms)\n[----------] 10 tests from CORE (5 ms total)\n\n[----------] 1 test from CLUSTERS_COUNT\n[ RUN ] CLUSTERS_COUNT.within_bounds\n[ OK ] CLUSTERS_COUNT.within_bounds (0 ms)\n[----------] 1 test from CLUSTERS_COUNT (0 ms total)\n\n[----------] 1 test from CLUSTERS\n[ RUN ] CLUSTERS.non_null\n[ OK ] CLUSTERS.non_null (0 ms)\n[----------] 1 test from CLUSTERS (0 ms total)\n\n[----------] 14 tests from CLUSTER\n[ RUN ] CLUSTER.non_null\n[ OK ] CLUSTER.non_null (0 ms)\n[ RUN ] CLUSTER.non_zero_processors\n[ OK ] CLUSTER.non_zero_processors (0 ms)\n[ RUN ] CLUSTER.valid_processors\n[ OK ] CLUSTER.valid_processors (0 ms)\n[ RUN ] CLUSTER.consistent_processors\n[ OK ] CLUSTER.consistent_processors (0 ms)\n[ RUN ] CLUSTER.non_zero_cores\n[ OK ] CLUSTER.non_zero_cores (0 ms)\n[ RUN ] CLUSTER.valid_cores\n[ OK ] CLUSTER.valid_cores (0 ms)\n[ RUN ] CLUSTER.consistent_cores\n[ OK ] CLUSTER.consistent_cores (0 ms)\n[ RUN ] CLUSTER.valid_cluster_id\n[ OK ] CLUSTER.valid_cluster_id (0 ms)\n[ RUN ] CLUSTER.valid_package\n[ OK ] CLUSTER.valid_package (0 ms)\n[ RUN ] CLUSTER.consistent_package\n[ OK ] CLUSTER.consistent_package (0 ms)\n[ RUN ] CLUSTER.consistent_vendor\n[ OK ] CLUSTER.consistent_vendor (0 ms)\n[ RUN ] CLUSTER.consistent_uarch\n[ OK ] CLUSTER.consistent_uarch (0 ms)\n[ RUN ] CLUSTER.consistent_midr\n[ OK ] CLUSTER.consistent_midr (0 ms)\n[ RUN ] CLUSTER.consistent_frequency\n[ OK ] CLUSTER.consistent_frequency (0 ms)\n[----------] 14 tests from CLUSTER (7 ms total)\n\n[----------] 1 test from PACKAGES_COUNT\n[ RUN ] PACKAGES_COUNT.within_bounds\n[ OK ] PACKAGES_COUNT.within_bounds (0 ms)\n[----------] 1 test from PACKAGES_COUNT (0 ms total)\n\n[----------] 1 test from PACKAGES\n[ RUN ] PACKAGES.non_null\n[ OK ] PACKAGES.non_null (0 ms)\n[----------] 1 test from PACKAGES (0 ms total)\n\n[----------] 10 tests from PACKAGE\n[ RUN ] PACKAGE.non_null\n[ OK ] PACKAGE.non_null (0 ms)\n[ RUN ] PACKAGE.non_zero_processors\n[ OK ] PACKAGE.non_zero_processors (0 ms)\n[ RUN ] PACKAGE.valid_processors\n[ OK ] PACKAGE.valid_processors (0 ms)\n[ RUN ] PACKAGE.consistent_processors\n[ OK ] PACKAGE.consistent_processors (0 ms)\n[ RUN ] PACKAGE.non_zero_cores\n[ OK ] PACKAGE.non_zero_cores (0 ms)\n[ RUN ] PACKAGE.valid_cores\n[ OK ] PACKAGE.valid_cores (0 ms)\n[ RUN ] PACKAGE.consistent_cores\n[ OK ] PACKAGE.consistent_cores (0 ms)\n[ RUN ] PACKAGE.non_zero_clusters\n[ OK ] PACKAGE.non_zero_clusters (0 ms)\n[ RUN ] PACKAGE.valid_clusters\n[ OK ] PACKAGE.valid_clusters (0 ms)\n[ RUN ] PACKAGE.consistent_cluster\n[ OK ] PACKAGE.consistent_cluster (0 ms)\n[----------] 10 tests from PACKAGE (5 ms total)\n\n[----------] 1 test from UARCHS_COUNT\n[ RUN ] UARCHS_COUNT.within_bounds\n[ OK ] UARCHS_COUNT.within_bounds (0 ms)\n[----------] 1 test from UARCHS_COUNT (0 ms total)\n\n[----------] 1 test from UARCHS\n[ RUN ] UARCHS.non_null\n[ OK ] UARCHS.non_null (0 ms)\n[----------] 1 test from UARCHS (0 ms total)\n\n[----------] 5 tests from UARCH\n[ RUN ] UARCH.non_null\n[ OK ] UARCH.non_null (0 ms)\n[ RUN ] UARCH.non_zero_processors\n[ OK ] UARCH.non_zero_processors (0 ms)\n[ RUN ] UARCH.valid_processors\n[ OK ] UARCH.valid_processors (0 ms)\n[ RUN ] UARCH.non_zero_cores\n[ OK ] UARCH.non_zero_cores (0 ms)\n[ RUN ] UARCH.valid_cores\n[ OK ] UARCH.valid_cores (0 ms)\n[----------] 5 tests from UARCH (2 ms total)\n\n[----------] 1 test from L1I_CACHES_COUNT\n[ RUN ] L1I_CACHES_COUNT.within_bounds\n[ OK ] L1I_CACHES_COUNT.within_bounds (0 ms)\n[----------] 1 test from L1I_CACHES_COUNT (0 ms total)\n\n[----------] 1 test from L1I_CACHES\n[ RUN ] L1I_CACHES.non_null\n[ OK ] L1I_CACHES.non_null (0 ms)\n[----------] 1 test from L1I_CACHES (0 ms total)\n\n[----------] 13 tests from L1I_CACHE\n[ RUN ] L1I_CACHE.non_null\n[ OK ] L1I_CACHE.non_null (0 ms)\n[ RUN ] L1I_CACHE.non_zero_size\n[ OK ] L1I_CACHE.non_zero_size (0 ms)\n[ RUN ] L1I_CACHE.valid_size\n[ OK ] L1I_CACHE.valid_size (0 ms)\n[ RUN ] L1I_CACHE.non_zero_associativity\n[ OK ] L1I_CACHE.non_zero_associativity (0 ms)\n[ RUN ] L1I_CACHE.non_zero_partitions\n[ OK ] L1I_CACHE.non_zero_partitions (0 ms)\n[ RUN ] L1I_CACHE.non_zero_line_size\n[ OK ] L1I_CACHE.non_zero_line_size (0 ms)\n[ RUN ] L1I_CACHE.power_of_2_line_size\n[ OK ] L1I_CACHE.power_of_2_line_size (0 ms)\n[ RUN ] L1I_CACHE.reasonable_line_size\n[ OK ] L1I_CACHE.reasonable_line_size (0 ms)\n[ RUN ] L1I_CACHE.valid_flags\n[ OK ] L1I_CACHE.valid_flags (0 ms)\n[ RUN ] L1I_CACHE.non_inclusive\n[ OK ] L1I_CACHE.non_inclusive (0 ms)\n[ RUN ] L1I_CACHE.non_zero_processors\n[ OK ] L1I_CACHE.non_zero_processors (0 ms)\n[ RUN ] L1I_CACHE.valid_processors\n[ OK ] L1I_CACHE.valid_processors (0 ms)\n[ RUN ] L1I_CACHE.consistent_processors\n[ OK ] L1I_CACHE.consistent_processors (0 ms)\n[----------] 13 tests from L1I_CACHE (7 ms total)\n\n[----------] 1 test from L1D_CACHES_COUNT\n[ RUN ] L1D_CACHES_COUNT.within_bounds\n[ OK ] L1D_CACHES_COUNT.within_bounds (0 ms)\n[----------] 1 test from L1D_CACHES_COUNT (0 ms total)\n\n[----------] 1 test from L1D_CACHES\n[ RUN ] L1D_CACHES.non_null\n[ OK ] L1D_CACHES.non_null (0 ms)\n[----------] 1 test from L1D_CACHES (0 ms total)\n\n[----------] 13 tests from L1D_CACHE\n[ RUN ] L1D_CACHE.non_null\n[ OK ] L1D_CACHE.non_null (0 ms)\n[ RUN ] L1D_CACHE.non_zero_size\n[ OK ] L1D_CACHE.non_zero_size (0 ms)\n[ RUN ] L1D_CACHE.valid_size\n[ OK ] L1D_CACHE.valid_size (0 ms)\n[ RUN ] L1D_CACHE.non_zero_associativity\n[ OK ] L1D_CACHE.non_zero_associativity (0 ms)\n[ RUN ] L1D_CACHE.non_zero_partitions\n[ OK ] L1D_CACHE.non_zero_partitions (0 ms)\n[ RUN ] L1D_CACHE.non_zero_line_size\n[ OK ] L1D_CACHE.non_zero_line_size (0 ms)\n[ RUN ] L1D_CACHE.power_of_2_line_size\n[ OK ] L1D_CACHE.power_of_2_line_size (0 ms)\n[ RUN ] L1D_CACHE.reasonable_line_size\n[ OK ] L1D_CACHE.reasonable_line_size (0 ms)\n[ RUN ] L1D_CACHE.valid_flags\n[ OK ] L1D_CACHE.valid_flags (0 ms)\n[ RUN ] L1D_CACHE.non_inclusive\n[ OK ] L1D_CACHE.non_inclusive (0 ms)\n[ RUN ] L1D_CACHE.non_zero_processors\n[ OK ] L1D_CACHE.non_zero_processors (0 ms)\n[ RUN ] L1D_CACHE.valid_processors\n[ OK ] L1D_CACHE.valid_processors (0 ms)\n[ RUN ] L1D_CACHE.consistent_processors\n[ OK ] L1D_CACHE.consistent_processors (0 ms)\n[----------] 13 tests from L1D_CACHE (7 ms total)\n\n[----------] 1 test from L2_CACHES_COUNT\n[ RUN ] L2_CACHES_COUNT.within_bounds\n[ OK ] L2_CACHES_COUNT.within_bounds (0 ms)\n[----------] 1 test from L2_CACHES_COUNT (0 ms total)\n\n[----------] 1 test from L2_CACHES\n[ RUN ] L2_CACHES.non_null\n[ OK ] L2_CACHES.non_null (0 ms)\n[----------] 1 test from L2_CACHES (0 ms total)\n\n[----------] 12 tests from L2_CACHE\n[ RUN ] L2_CACHE.non_null\n[ OK ] L2_CACHE.non_null (0 ms)\n[ RUN ] L2_CACHE.non_zero_size\n[ OK ] L2_CACHE.non_zero_size (0 ms)\n[ RUN ] L2_CACHE.valid_size\n[ OK ] L2_CACHE.valid_size (0 ms)\n[ RUN ] L2_CACHE.non_zero_associativity\n[ OK ] L2_CACHE.non_zero_associativity (0 ms)\n[ RUN ] L2_CACHE.non_zero_partitions\n[ OK ] L2_CACHE.non_zero_partitions (0 ms)\n[ RUN ] L2_CACHE.non_zero_line_size\n[ OK ] L2_CACHE.non_zero_line_size (0 ms)\n[ RUN ] L2_CACHE.power_of_2_line_size\n[ OK ] L2_CACHE.power_of_2_line_size (0 ms)\n[ RUN ] L2_CACHE.reasonable_line_size\n[ OK ] L2_CACHE.reasonable_line_size (0 ms)\n[ RUN ] L2_CACHE.valid_flags\n[ OK ] L2_CACHE.valid_flags (0 ms)\n[ RUN ] L2_CACHE.non_zero_processors\n[ OK ] L2_CACHE.non_zero_processors (0 ms)\n[ RUN ] L2_CACHE.valid_processors\n[ OK ] L2_CACHE.valid_processors (0 ms)\n[ RUN ] L2_CACHE.consistent_processors\n[ OK ] L2_CACHE.consistent_processors (0 ms)\n[----------] 12 tests from L2_CACHE (6 ms total)\n\n[----------] 1 test from L3_CACHES_COUNT\n[ RUN ] L3_CACHES_COUNT.within_bounds\n[ OK ] L3_CACHES_COUNT.within_bounds (0 ms)\n[----------] 1 test from L3_CACHES_COUNT (0 ms total)\n\n[----------] 12 tests from L3_CACHE\n[ RUN ] L3_CACHE.non_null\n[ OK ] L3_CACHE.non_null (0 ms)\n[ RUN ] L3_CACHE.non_zero_size\n[ OK ] L3_CACHE.non_zero_size (0 ms)\n[ RUN ] L3_CACHE.valid_size\n[ OK ] L3_CACHE.valid_size (0 ms)\n[ RUN ] L3_CACHE.non_zero_associativity\n[ OK ] L3_CACHE.non_zero_associativity (0 ms)\n[ RUN ] L3_CACHE.non_zero_partitions\n[ OK ] L3_CACHE.non_zero_partitions (0 ms)\n[ RUN ] L3_CACHE.non_zero_line_size\n[ OK ] L3_CACHE.non_zero_line_size (0 ms)\n[ RUN ] L3_CACHE.power_of_2_line_size\n[ OK ] L3_CACHE.power_of_2_line_size (0 ms)\n[ RUN ] L3_CACHE.reasonable_line_size\n[ OK ] L3_CACHE.reasonable_line_size (0 ms)\n[ RUN ] L3_CACHE.valid_flags\n[ OK ] L3_CACHE.valid_flags (0 ms)\n[ RUN ] L3_CACHE.non_zero_processors\n[ OK ] L3_CACHE.non_zero_processors (0 ms)\n[ RUN ] L3_CACHE.valid_processors\n[ OK ] L3_CACHE.valid_processors (0 ms)\n[ RUN ] L3_CACHE.consistent_processors\n[ OK ] L3_CACHE.consistent_processors (0 ms)\n[----------] 12 tests from L3_CACHE (6 ms total)\n\n[----------] 1 test from L4_CACHES_COUNT\n[ RUN ] L4_CACHES_COUNT.within_bounds\n[ OK ] L4_CACHES_COUNT.within_bounds (0 ms)\n[----------] 1 test from L4_CACHES_COUNT (0 ms total)\n\n[----------] 12 tests from L4_CACHE\n[ RUN ] L4_CACHE.non_null\n[ OK ] L4_CACHE.non_null (0 ms)\n[ RUN ] L4_CACHE.non_zero_size\n[ OK ] L4_CACHE.non_zero_size (0 ms)\n[ RUN ] L4_CACHE.valid_size\n[ OK ] L4_CACHE.valid_size (0 ms)\n[ RUN ] L4_CACHE.non_zero_associativity\n[ OK ] L4_CACHE.non_zero_associativity (0 ms)\n[ RUN ] L4_CACHE.non_zero_partitions\n[ OK ] L4_CACHE.non_zero_partitions (0 ms)\n[ RUN ] L4_CACHE.non_zero_line_size\n[ OK ] L4_CACHE.non_zero_line_size (0 ms)\n[ RUN ] L4_CACHE.power_of_2_line_size\n[ OK ] L4_CACHE.power_of_2_line_size (0 ms)\n[ RUN ] L4_CACHE.reasonable_line_size\n[ OK ] L4_CACHE.reasonable_line_size (0 ms)\n[ RUN ] L4_CACHE.valid_flags\n[ OK ] L4_CACHE.valid_flags (0 ms)\n[ RUN ] L4_CACHE.non_zero_processors\n[ OK ] L4_CACHE.non_zero_processors (0 ms)\n[ RUN ] L4_CACHE.valid_processors\n[ OK ] L4_CACHE.valid_processors (0 ms)\n[ RUN ] L4_CACHE.consistent_processors\n[ OK ] L4_CACHE.consistent_processors (0 ms)\n[----------] 12 tests from L4_CACHE (6 ms total)\n\n[----------] Global test environment tear-down\n[\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d] 132 tests from 28 test suites ran. (93 ms total)\n[ PASSED ] 132 tests.\n```\n\nwith `cpu-info.exe` returning\n\n```\nPackages:\n 0: Snapdragon (TM) 8cx Gen 3\nMicroarchitectures:\n 4x Cortex-A78\n 4x Cortex-X1\nCores:\n 0: 1 processor (0), ARM Cortex-A78\n 1: 1 processor (1), ARM Cortex-A78\n 2: 1 processor (2), ARM Cortex-A78\n 3: 1 processor (3), ARM Cortex-A78\n 4: 1 processor (4), ARM Cortex-X1\n 5: 1 processor (5), ARM Cortex-X1\n 6: 1 processor (6), ARM Cortex-X1\n 7: 1 processor (7), ARM Cortex-X1\nLogical processors:\n 0\n 1\n 2\n 3\n 4\n 5\n 6\n 7\n```\n\nand `isa-info.exe` returning\n\n```\nInstruction sets:\n ARM v8.1 atomics: yes\n ARM v8.1 SQRDMLxH: yes\n ARM v8.2 FP16 arithmetics: yes\n ARM v8.2 FHM: no\n ARM v8.2 BF16: no\n ARM v8.2 Int8 dot product: yes\n ARM v8.2 Int8 matrix multiplication: no\n ARM v8.3 JS conversion: no\n ARM v8.3 complex: no\nSIMD extensions:\n ARM SVE: no\n ARM SVE 2: no\nCryptography extensions:\n AES: yes\n SHA1: yes\n SHA2: yes\n PMULL: yes\n CRC32: yes\n```\n\nGitOrigin-RevId: 6543fec09b2f04ac4a666882998b534afc9c1349\nChange-Id: I2639cc38addfb0dd5ff8bc3a2b19b57e35820ce1\n" }, { "commit": "96775f8ac60f47fc8c09485a98ae24299b928515", "tree": "e5e2102546ee83ab47eb9804d237df696daf3ff2", "parents": [ "a1f56fe59b63ca8fede1bafd4800ae3b29a9b459" ], "author": { "name": "Vertexwahn", "email": "julian.amann@tum.de", "time": "Fri Mar 15 16:43:54 2024 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Mar 15 08:49:50 2024 -0700" }, "message": "Bazel-support: Add MODUEL.bazel to support Bzlmod (#229)\n\nThis PR adds a `MODULE.bazel` file. This is needed for [Bzlmod](https://bazel.build/external/mod-command) support of Bazel. In the long term this will replace the `WORKSPACE.bazel` file. In the meantime, both files are needed.\n\nGitOrigin-RevId: fb08ae018ef8d8f71e3a2960c0982f90b688fe06\nChange-Id: I5fbac1e0c467bc2f5948653790aa486322919be2\n" }, { "commit": "a1f56fe59b63ca8fede1bafd4800ae3b29a9b459", "tree": "d8bae1097d051b5201c655aed8674ac440a6a90a", "parents": [ "b2e2259c99d25717435041ff8f976cab40076a7d" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Mon Feb 26 09:33:39 2024 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Feb 26 07:38:03 2024 -0800" }, "message": "Merge pull request #225 from fbarchard/break\n\ncachebreak\n\nGitOrigin-RevId: aa4b2163b99ac9534194520f70b93eeefb0b3b4e\nChange-Id: I8fb77f6cc1ac9dc1bdd1b2ecf43a1029b6090347\n" }, { "commit": "b2e2259c99d25717435041ff8f976cab40076a7d", "tree": "60b7fd52001479832ca242c3715da0fdc3a9d8fe", "parents": [ "f1abda413f1de0f2c91d3aea371e69487ef1adfb" ], "author": { "name": "Mark Ryan", "email": "markdryan@rivosinc.com", "time": "Tue Jan 23 15:59:49 2024 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 23 07:05:59 2024 -0800" }, "message": "ci: Add an Ubuntu:22.04 builder for RISC-V (#219)\n\ncpuinfo is built for riscv64 using a riscv64 container. binfmt_misc\nallows the riscv64 binaries in the container to be executed with QEMU.\nThis is slower than cross compiling but as there\u0027s not that much code\nthe build times are acceptable. It takes just under 6 minutes for the\nfull riscv64 github action to run. We also have the option of running\nsome of the built RISC-V binaries, e.g., unit tests, in the CI. It\nshould be easy to expand the matrix to add CI for other architectures\nnot natively supported by github actions.\n\nGitOrigin-RevId: 9484a6c590f831a30c1eec1311568b1a967a89dc\nChange-Id: I7bcbae69d76d90441bd981d3087f71b6de3218da\n" }, { "commit": "f1abda413f1de0f2c91d3aea371e69487ef1adfb", "tree": "e4b33246148e3a006d251deb865925cee527baa6", "parents": [ "fd40896e151c45fca61de6b12836ff12ccde06b7" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Tue Jan 23 06:53:09 2024 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Jan 23 06:59:08 2024 -0800" }, "message": "Upgrade to warning when name is truncated (#216)\n\nSignal to users that the name field may not produce the expected string\nif the chipset name and revision exceeds the maximum size of the buffer.\nIn practice, this is unlikely as the buffer size is reasonably high for\na chipset name/revision.\n\nGitOrigin-RevId: 434970b5d072d2f1e5e5fb44009884f278514588\nChange-Id: Id89b8f200f641a2c98278a659a1156c4d3404e68\n" }, { "commit": "fd40896e151c45fca61de6b12836ff12ccde06b7", "tree": "ada546b8fd088fa9e59abd7a90deb4452b8084c6", "parents": [ "523768dc1148ef2bd9dc2b20706aa8a003411d94" ], "author": { "name": "Mark Ryan", "email": "markdryan@rivosinc.com", "time": "Mon Jan 22 18:43:46 2024 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 22 09:49:47 2024 -0800" }, "message": "Fix RISC-V Linux build again (#215)\n\nPR https://github.com/pytorch/cpuinfo/pull/204 broke the RISC-V\nbuild by including for a second time a header file that currently\nonly exists in the RISC-V Android NDK. The header is not yet\navailable in mainstream Linux distributions. The header in question,\n\u003csys/hwprobe.h\u003e, is already included when building for Android\nat the top of riscv-hw.c so the second include is unnecessary and\ncan be safely removed.\n\nGitOrigin-RevId: 9321265af2078e98b91774a53bdccaea0f6665f8\nChange-Id: I4e20f72e3372d9d5016cc007b8ea368125e0aca3\n" }, { "commit": "523768dc1148ef2bd9dc2b20706aa8a003411d94", "tree": "026063807fc24e186d6537adb54d1a1b1c4bb57a", "parents": [ "f7599ebe47ddeefcad4239f5bed725da5742292e" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Mon Jan 08 16:59:57 2024 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 08 17:05:32 2024 -0800" }, "message": "Run Bazel build in Github Actions (#213)\n\nAs some clients rely on the Bazel build, add a workflow to verify at\nleast one Bazel target (linux-x86). Also, perform some minor cleanup to\ncomments and target branches in our workflow files.\n\nGitOrigin-RevId: 76cc10d627add77922dc24521b332a055a4d6d77\nChange-Id: I31384360670c14376c30587a0456a4f1951688f1\n" }, { "commit": "f7599ebe47ddeefcad4239f5bed725da5742292e", "tree": "9152580315803beb1e8bad793c74acd48524c589", "parents": [ "c74555bee64e6c1dcb58d777cc6d115e6ca67151" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Mon Jan 08 13:05:58 2024 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Jan 08 13:07:34 2024 -0800" }, "message": "Adjust log levels of /proc/cpuinfo parsing (#209)\n\nThere are a few steps in our parsing logic where we skip lines that don\u0027t match the expectations of the /proc/cpuinfo node. Reduce the log level of these lines to \u0027debug\u0027, as these are not generally errors and are noisy on systems that have unique cpuinfo key-value pairs.\n\nWhen parsing logic encounters a higher-than-expected processor number, increase the level to warning, to indicate that an error may have occurred in the parsing step.\n\nThis does not fully address #19 but resolves the underlying noise reported.\n\nGitOrigin-RevId: 050273682e78409dd76bdfea2a24e17f63f94977\nChange-Id: I83b7dd0956125d0b3a91d485c0f4696997cb9ce7\n" }, { "commit": "c74555bee64e6c1dcb58d777cc6d115e6ca67151", "tree": "06e2055b04d162b221fcc0f9bd9426070876fade", "parents": [ "d8ad3b0ca02455aadb95ccdce9780c6015d4a4ed" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Fri Jan 05 17:17:27 2024 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jan 05 17:23:31 2024 -0800" }, "message": "Add .clang-format to enforce project style (#204)\n\n* Add .clang-format to enforce project style\n\nThe settings here match the current settings for the pytorch/pytorch\nproject, with the exception that 8-character-width tabs are preferred in\nplace of spaces.\n\n* Mass reformat of all .c and .h files\n\nNow that we have a clang-format file defined, clean up all usages once.\n\n* Enable clang-format-check workflow\n\nEnforce clang-format consistency on all new changes.\n\nGitOrigin-RevId: 42bff7ad39de3eb520cb20ab27f51ed816935edc\nChange-Id: I430a06a353633862913602ddcd964926e11d0b69\n" }, { "commit": "d8ad3b0ca02455aadb95ccdce9780c6015d4a4ed", "tree": "b464cd5327d5fa2a3f0e0066186c626ba3adb5db", "parents": [ "ab2d3bfbc1a956a60de2d91e47183d0016e616df" ], "author": { "name": "Mark Ryan", "email": "desdemonaryan@hotmail.com", "time": "Fri Jan 05 18:26:21 2024 +0000" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jan 05 10:32:40 2024 -0800" }, "message": "Fix RISC-V Linux build (#212)\n\nCpuinfo was failing to build on RISC-V Linux distributions, e.g.,\nUbuntu 23.10, as it includes a header file sys/hwprobe.h that is\nnot yet provided by glibc (although it is provided by bionic). We\nfix the issue by only including sys/hwprobe.h when building for\nAndroid, and invoking the hwprobe syscall directly on other\nLinux distributions. The Android specific check can be removed in\nthe future once sys/hwprobe.h becomes available in glibc.\n\nGitOrigin-RevId: 313524ab20d2041854af8ad07bf726ddd485d258\nChange-Id: I02f3084c188e696e43dc7dbc44cb0e0e2e948244\n" }, { "commit": "ab2d3bfbc1a956a60de2d91e47183d0016e616df", "tree": "f72effa70b75177fc914d580fae577b3a42c5810", "parents": [ "5870f455817bb6896e593dbc39dae74630ff64b6" ], "author": { "name": "Iacopo Colonnelli", "email": "iacopo.c92@gmail.com", "time": "Fri Dec 08 06:34:03 2023 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Dec 07 21:37:55 2023 -0800" }, "message": "Improve smallfile callback (#211)\n\nThis PR improves the smallfile callback error reporting, passing the\nname of the inspected file in the `filename` argument instead of forcing\nit to be `KERNEL_MAX_FILENAME` as before.\n\nGitOrigin-RevId: 2f4c278f7aa3e9a451c14c3e9a02c3e091140d96\nChange-Id: I4df531bda31946a606afb31a4bb4e3573c2af470\n" }, { "commit": "5870f455817bb6896e593dbc39dae74630ff64b6", "tree": "b0f6a7a97f826fd6b9434cff2c84f4dcca80c7d6", "parents": [ "46631b41e82a6f32dd00d7136945de3bf37d12a0" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Thu Nov 30 06:47:12 2023 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 30 07:08:12 2023 -0800" }, "message": "Fix chipset enum name to include \u0027vendor_\u0027 (#210)\n\nThe original change that introduced this should have used a consistent prefix for all enum types, for consistency sake.\n\nGitOrigin-RevId: b8b29a164e7704b75ad66b072aa2db409cc941fd\nChange-Id: Icc608620f67499935e23fc3a4c6b66e1402ec445\n" }, { "commit": "46631b41e82a6f32dd00d7136945de3bf37d12a0", "tree": "d89476769eecd13db511007a022a1b7d6fe5b6d7", "parents": [ "7924d636eb743fc89be5a9d742ff4d0fed4e7180" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Tue Nov 28 08:06:02 2023 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Nov 28 08:09:50 2023 -0800" }, "message": "Fix CPU_SET dynamic allocation and leak (#205)\n\nThe initial implementation had a number of issues:\n- The allocation of the CPU_SET should be checked for a NULL return.\n- The CPU_*_S macros should be used when working with dynamic sets.\n- The CPU_SET needs to be cleared via CPU_ZERO_S before use.\n- Dynamic CPU_SETs need to be freed after use.\n- The __riscv_hwprobe syscall is expecting a set *size* not a *count*.\n\nGitOrigin-RevId: 9d809924011af8ff49dadbda1499dc5193f1659c\nChange-Id: Iba35c119338df14f239141598cafcae105a5e2c3\n" }, { "commit": "7924d636eb743fc89be5a9d742ff4d0fed4e7180", "tree": "bb164abf9a217a8335e94926dbfbc6d3640facc9", "parents": [ "df41a2b6772cce51119138332f6e1a28e2467ddd" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Mon Nov 20 10:46:35 2023 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Mon Nov 20 10:52:24 2023 -0800" }, "message": "Add android_riscv64 to BUILD.bazel (#201)\n\nGitOrigin-RevId: ef634603954d88d2643d5809011288b890ac126e\nChange-Id: I84a580e6836f508eba839c2c58299584e288e826\n" }, { "commit": "df41a2b6772cce51119138332f6e1a28e2467ddd", "tree": "17d29dd12a3f70ab640c67bf4f20289f4eb8cd02", "parents": [ "56ffbeee609a2b7f5d2cc3e12cbb61a0c1c42a8f" ], "author": { "name": "snadampal", "email": "87143774+snadampal@users.noreply.github.com", "time": "Thu Nov 16 16:47:25 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 16 14:53:57 2023 -0800" }, "message": "[arm] fix the logic for identifying the valid processors (#197)\n\nThe current logic for valid processor detection is reporting all cpus irrespective of whether they are online or not. so, it\u0027s causing thread over-subscription for the scenarios where the online cpu count \u003c the actual cpus. This is fixed by publishing only the online cpu count as the valid processors.\n\nGitOrigin-RevId: 20bd32c1b50d8d70f8ddd67e7e8782bf3847ebad\nChange-Id: Iad7de52ba405d34ccebde1e4d7bae4585077b4b9\n" }, { "commit": "56ffbeee609a2b7f5d2cc3e12cbb61a0c1c42a8f", "tree": "3c35d651d61a111f4056bd08d3e9a4daf9e096a7", "parents": [ "3d55e6de3ddb0f4b2831e0fb32a5baa37115bf71" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Thu Nov 16 09:07:26 2023 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Nov 16 09:13:11 2023 -0800" }, "message": "Fix size check of max processor count (#199)\n\nOn 64-bit systems, size_t will not overflow when the function to get max\nprocessors returns UINT32_MAX. Use the appropriate uint32_t type.\n\nGitOrigin-RevId: 9f13d15a88de63cfb516f12cc9ac330ad8b9cadb\nChange-Id: Iacd386d020227fdfe8fd8e188f25893beef19db0\n" }, { "commit": "3d55e6de3ddb0f4b2831e0fb32a5baa37115bf71", "tree": "95472f3012ab062e12282dddde807f24a6925a2e", "parents": [ "33848c045ee1c7cac3111ae4ec11b43b4c187784" ], "author": { "name": "Prashanth Swaminathan", "email": "40780424+prashanthswami@users.noreply.github.com", "time": "Tue Nov 14 11:24:07 2023 -0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Tue Nov 14 11:30:02 2023 -0800" }, "message": "Add limited support for RISC-V initialization (#190)\n\n* Adds header definitions for RISCV32 and RISCV64, and support in Bazel\n files for RISCV64. Adds ISA information for RISC-V and hwcap support.\n\n* Adds support to construct the processor, core, cluster and package\n information reported by the system.\n\n* Remaining support required for:\n - Inferring uarch of each processor (reports unknown for now).\n - Reading cache information (left empty for now).\n\nTest: Build and ran cpu_info and isa_info on RISC-V QEMU instance and\nRISC-V Android emulator. Confirmed that it properly reports the ISA\ninformation as well as processor and cluster counts.\nGitOrigin-RevId: 4e5be9e1c6c5895bc5105a92d587bc9df8d2522b\nChange-Id: I98a439ab2b98762b8a2e26d3a9a7b22eafb3fcb7\n" }, { "commit": "33848c045ee1c7cac3111ae4ec11b43b4c187784", "tree": "6077c049771ce24b207f4bc82e144e8ce49d1ccd", "parents": [ "e0b42b61ae01687a1571040292657b8b28c2c74e" ], "author": { "name": "Quentin Khan", "email": "dev@pelikhan.xyz", "time": "Sat Nov 04 01:50:14 2023 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Nov 03 17:56:39 2023 -0700" }, "message": "Add detection of Intel x86 AVX-VNNI instructions. (#196)\n\nTested using Intel SDE:\n\n```\nbash scripts/local-build.sh\n\nOPTIONS\u003d()\nPLATFORMS\u003d()\n\nOPTIONS+\u003d(-quark); PLATFORMS+\u003d(\"Quark\")\nOPTIONS+\u003d(-p4); PLATFORMS+\u003d(\"Pentium4\")\nOPTIONS+\u003d(-p4p); PLATFORMS+\u003d(\"Pentium4 Prescott\")\nOPTIONS+\u003d(-mrm); PLATFORMS+\u003d(\"Merom\")\nOPTIONS+\u003d(-pnr); PLATFORMS+\u003d(\"Penryn\")\nOPTIONS+\u003d(-nhm); PLATFORMS+\u003d(\"Nehalem\")\nOPTIONS+\u003d(-wsm); PLATFORMS+\u003d(\"Westmere\")\nOPTIONS+\u003d(-snb); PLATFORMS+\u003d(\"Sandy Bridge\")\nOPTIONS+\u003d(-ivb); PLATFORMS+\u003d(\"Ivy Bridge\")\nOPTIONS+\u003d(-hsw); PLATFORMS+\u003d(\"Haswell\")\nOPTIONS+\u003d(-bdw); PLATFORMS+\u003d(\"Broadwell\")\nOPTIONS+\u003d(-slt); PLATFORMS+\u003d(\"Saltwell\")\nOPTIONS+\u003d(-slm); PLATFORMS+\u003d(\"Silvermont\")\nOPTIONS+\u003d(-glm); PLATFORMS+\u003d(\"Goldmont\")\nOPTIONS+\u003d(-glp); PLATFORMS+\u003d(\"Goldmont Plus\")\nOPTIONS+\u003d(-tnt); PLATFORMS+\u003d(\"Tremont\")\nOPTIONS+\u003d(-snr); PLATFORMS+\u003d(\"Snow Ridge\")\nOPTIONS+\u003d(-skl); PLATFORMS+\u003d(\"Skylake\")\nOPTIONS+\u003d(-cnl); PLATFORMS+\u003d(\"Cannon Lake\")\nOPTIONS+\u003d(-icl); PLATFORMS+\u003d(\"Ice Lake\")\nOPTIONS+\u003d(-skx); PLATFORMS+\u003d(\"Skylake server\")\nOPTIONS+\u003d(-clx); PLATFORMS+\u003d(\"Cascade Lake\")\nOPTIONS+\u003d(-cpx); PLATFORMS+\u003d(\"Cooper Lake\")\nOPTIONS+\u003d(-icx); PLATFORMS+\u003d(\"Ice Lake server\")\nOPTIONS+\u003d(-knl); PLATFORMS+\u003d(\"Knights landing\")\nOPTIONS+\u003d(-knm); PLATFORMS+\u003d(\"Knights mill\")\nOPTIONS+\u003d(-tgl); PLATFORMS+\u003d(\"Tiger Lake\")\nOPTIONS+\u003d(-adl); PLATFORMS+\u003d(\"Alder Lake\")\nOPTIONS+\u003d(-mtl); PLATFORMS+\u003d(\"Meteor Lake\")\nOPTIONS+\u003d(-rpl); PLATFORMS+\u003d(\"Raptor Lake\")\nOPTIONS+\u003d(-spr); PLATFORMS+\u003d(\"Sapphire Rapids\")\nOPTIONS+\u003d(-gnr); PLATFORMS+\u003d(\"Granite Rapids\")\nOPTIONS+\u003d(-srf); PLATFORMS+\u003d(\"Sierra Forest\")\nOPTIONS+\u003d(-grr); PLATFORMS+\u003d(\"Grand Ridge\")\nOPTIONS+\u003d(-future); PLATFORMS+\u003d(\"Future chip\")\n\nSDE_BIN\u003d\"path/to/sde\"\n\nfor I in \"${!PLATFORMS[@]}\"; do\n echo \"${PLATFORMS[\"${I}\"]}\"\n \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep \"AVXVNNI\"\ndone\n```\n\nResult:\n\n```\nQuark\n [error]\nMerom\n [error]\nPenryn\n [error]\nNehalem\n [error]\nWestmere\n AVXVNNI: no\nSandy Bridge\n AVXVNNI: no\nIvy Bridge\n AVXVNNI: no\nHaswell\n AVXVNNI: no\nBroadwell\n AVXVNNI: no\nSaltwell\n [error]\nSilvermont\n AVXVNNI: no\nGoldmont\n AVXVNNI: no\nGoldmont Plus\n AVXVNNI: no\nTremont\n AVXVNNI: no\nSnow Ridge\n AVXVNNI: no\nSkylake\n AVXVNNI: no\nCannon Lake\n AVXVNNI: no\nIce Lake\n AVXVNNI: no\nSkylake server\n AVXVNNI: no\nCascade Lake\n AVXVNNI: no\nCooper Lake\n AVXVNNI: no\nIce Lake server\n AVXVNNI: no\nKnights landing\n AVXVNNI: no\nKnights mill\n AVXVNNI: no\nTiger Lake\n AVXVNNI: no\nAlder Lake\n AVXVNNI: yes\nMeteor Lake\n AVXVNNI: yes\nRaptor Lake\n AVXVNNI: yes\nSapphire Rapids\n AVXVNNI: yes\nGranite Rapids\n AVXVNNI: yes\nSierra Forest\n AVXVNNI: yes\nGrand Ridge\n AVXVNNI: yes\nFuture chip\n AVXVNNI: yes\n```\n\nGitOrigin-RevId: d6860c477c99f1fce9e28eb206891af3c0e1a1d7\nChange-Id: Ib36a5a179d92db648319cbdb9b67f6d90a7261b1\n" }, { "commit": "e0b42b61ae01687a1571040292657b8b28c2c74e", "tree": "6c23bc60c85fe90bfb4b00b745ffe045e62e4a2b", "parents": [ "e1762fa70a551ab26f3f7d12b53b0dc0a0c27a32" ], "author": { "name": "Paolo", "email": "142514942+paolotricerri@users.noreply.github.com", "time": "Thu Oct 19 20:37:38 2023 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Oct 19 12:43:41 2023 -0700" }, "message": "Add support for Arm Neoverse V2 (#194)\n\nGitOrigin-RevId: 76d5e8f5b563daa65340a60fce0e9aec73a936df\nChange-Id: I7830e37a66b5e9a4ba50e83f07324c939671b85d\n" }, { "commit": "e1762fa70a551ab26f3f7d12b53b0dc0a0c27a32", "tree": "ca8ee592818c8ff80160d69e5d137caa80920e6b", "parents": [ "4a8b8466666ddf7fe43a4d244b95456faeedb8fc" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 16:30:44 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 15:43:01 2023 -0700" }, "message": "Include intrin.h MSVC header in cpuinfo/utils.h\n\nGitOrigin-RevId: 959002f82d7962a473d8bf301845f2af720e0aa4\nChange-Id: Ie9aa89b412dfd0d4acc0cddc8354119ea8f0325c\n" }, { "commit": "4a8b8466666ddf7fe43a4d244b95456faeedb8fc", "tree": "9b84d64582fcae52de43344c46321e2dd2aec246", "parents": [ "9cdaf5d4f7ea90d0a98ff387d3b9b15a628e0aa7" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 16:03:06 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 15:14:58 2023 -0700" }, "message": "Support building for ARM Linux with GLibC older than 2.16\n\nGitOrigin-RevId: 9df83faa65d4c5db3ad6630cbb944a0b4e5e4a84\nChange-Id: I74f77b5c438f05777ecd07965a19484b04e521fb\n" }, { "commit": "9cdaf5d4f7ea90d0a98ff387d3b9b15a628e0aa7", "tree": "0c279b2144cf39d3f9cedc4419b2fdfaa1f38189", "parents": [ "1bc26ff6cb38b846d8f30fd868d40289759512d3" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 15:46:07 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 15:01:23 2023 -0700" }, "message": "Work around faulty implementations of NEON DOT instructions\n\nPrevent detection of NEON DOT instruction set on Spreadtrum SC9863A and\nUnisoc T310, where these instructions occasionally trigger SIGILL\n\nGitOrigin-RevId: dce131b242c5282e2e5ee254364ff2ea7e1b0999\nChange-Id: I795dc483a6f125788f5fed985bc63a890e81d8df\n" }, { "commit": "1bc26ff6cb38b846d8f30fd868d40289759512d3", "tree": "49b50afef21ecd7d81a1e5620139427b7434aa49", "parents": [ "071fe41f70c736c3e89295ea4f2db4353eeda7f7" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 15:36:09 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 14:49:13 2023 -0700" }, "message": "Don\u0027t consider Cortex-A65 in AArch32 ISA detection\n\nCortex-A65 is AArch64-only and not paired with AArch32-capable cores\n\nGitOrigin-RevId: 3c8583da7fe36c9fe1367cf18907b479c115759d\nChange-Id: Icc66096c2a2f3617e469d955dd7f5507085e9e8e\n" }, { "commit": "071fe41f70c736c3e89295ea4f2db4353eeda7f7", "tree": "d90772c485b67cf6686267bf37a90d649825d3c4", "parents": [ "fe1425a8bf34d020952013e3f7aa9c64ca56cf83" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 15:25:24 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 14:35:45 2023 -0700" }, "message": "Remove redundant newline after match_t\n\nGitOrigin-RevId: c15d537323081f188e4643f31bd93e6732992311\nChange-Id: Ibe8d495df0d490137e55dceccff85854f62fea2f\n" }, { "commit": "fe1425a8bf34d020952013e3f7aa9c64ca56cf83", "tree": "61523daf7559015658386e895b029bc206a55450", "parents": [ "fb3fe1f1ca51c62a95e3a8a4aeaf660082484f1f" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 14:55:57 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 14:26:48 2023 -0700" }, "message": "Detect Unisoc T-series chipsets\n\nGitOrigin-RevId: e00b4854ca4600022c4f942dee1bddf52bafc9cb\nChange-Id: I55055373d794830a5357789a6d74c7b43c6be9ad\n" }, { "commit": "fb3fe1f1ca51c62a95e3a8a4aeaf660082484f1f", "tree": "5eb5e0c375e737de06bbbfc5036015f9fb36c03b", "parents": [ "12ab27315d523bbec3ed546800d431b63cc88ac5" ], "author": { "name": "Marat Dukhan", "email": "maratek@google.com", "time": "Wed Aug 16 15:04:59 2023 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Wed Aug 16 14:17:01 2023 -0700" }, "message": "Remove redundant architecture version check in aarch32-isa.c\n\nGitOrigin-RevId: 8eab20281d2648db5b88c47ace6540396435dbae\nChange-Id: Ieb160426c5b79f0df8e06ea8b29dcc007da908ed\n" } ], "next": "12ab27315d523bbec3ed546800d431b63cc88ac5" }