)]}'
{
  "commit": "c8b62eadd14a2f4dd5dfafd5f0887f9cad1e1b48",
  "tree": "a8709ea597cd54cafb7d15ebf4138b21b7dbd84a",
  "parents": [
    "c612c331311745ed3c658c75171b48b9981f56e9"
  ],
  "author": {
    "name": "Nicolas Pitre",
    "email": "nico@fluxnic.net",
    "time": "Thu Apr 30 19:06:12 2026 -0400"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Thu Apr 30 16:07:31 2026 -0700"
  },
  "message": "Add Cortex-A320 to MIDR decode table (#384)\n\nARM Cortex-A320 (MIDR part 0xD8F) is an ARMv9.2-A efficiency core.\nAdd its uarch enum and MIDR mapping so XNNPACK can select optimized\nkernels when running on this core.\n\nSigned-off-by: Nicolas Pitre \u003cnpitre@baylibre.com\u003e\nGitOrigin-RevId: 3681f0ce1446167d01dfe125d6db96ba2ac31c3c\nChange-Id: I7b587f7f86bdc3923e84f9edea36e17584ea0da3\n",
  "tree_diff": [
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}