)]}'
{
  "commit": "2fa51827e3205bc85db6e170ba373a5398ba3ad9",
  "tree": "580c98c77b88fd10dcb0bb7c135e3fab8f07de23",
  "parents": [
    "d8bee539c4046bdc086d54b18bbb8a8b44d06f73"
  ],
  "author": {
    "name": "wizardengineer",
    "email": "juliuswoosebert@gmail.com",
    "time": "Fri May 22 12:12:54 2026 -0400"
  },
  "committer": {
    "name": "wizardengineer",
    "email": "juliuswoosebert@gmail.com",
    "time": "Fri May 22 20:31:40 2026 -0400"
  },
  "message": "[ARM] Regen ctselect tests for new core legalization\n\nThe core PR moved CT_SELECT lowering into the generic legalizer\n(memory-blend for FP types without a legal same-size integer,\nscalar-mask+splat for vectors). ARM tests\u0027 CHECK lines need to\nreflect the new codegen.\n\nNo functional change in ARM target lowering itself; only test\nexpectations updated to match generated output.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bfc60f1fad42ddf2ebefad407ffacbcdb0db283b",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/ARM/ctselect-half.ll",
      "new_id": "f83a95e62f07fbc8979b2eddfc1e1f4e320a981e",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/ARM/ctselect-half.ll"
    },
    {
      "type": "modify",
      "old_id": "3a03ebccb05acc51e8e29c7ff1e637d315713763",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/ARM/ctselect-vector.ll",
      "new_id": "d720c8990ab691812f1381aff737532d564d9c52",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/ARM/ctselect-vector.ll"
    },
    {
      "type": "modify",
      "old_id": "055e8733cb65c25e69d266dd14dbd4ea1828e4df",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/ARM/ctselect.ll",
      "new_id": "b6d5be4e77257a0db0aec5a4d82031e1a36872f4",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/ARM/ctselect.ll"
    }
  ]
}