)]}'
{
  "commit": "c29c94ac5a5a2aa48712e1a7866867756fb0c1eb",
  "tree": "750feb5fdeec677aa31fed0e6c779cddb5df0fb6",
  "parents": [
    "e0424be5bb143bac25257f42fc2d0e217c5e1895"
  ],
  "author": {
    "name": "Valery Pykhtin",
    "email": "valery.pykhtin@amd.com",
    "time": "Thu Aug 27 10:56:11 2026 +0000"
  },
  "committer": {
    "name": "Valery Pykhtin",
    "email": "valery.pykhtin@amd.com",
    "time": "Tue Sep 01 15:47:53 2026 +0000"
  },
  "message": "[AMDGPU] Restructure VGPR-alignment verifier tests, NFC\n\nRewrite verify-gfx90a-aligned-vgprs.mir and verify-ds-gws-align.mir so each case\ndocuments inline what makes it invalid, and match the verifier\u0027s fuller output -\nthe \"*** Bad machine code ***\" kind and the \"- instruction:\" line - instead of a\nsingle message fragment. Pure test restructure with no functional change, so the\nfollow-up commit that derives alignment from the operand register class shows\nonly the change in diagnostic wording.\n\nCo-Authored-By: Claude \u003cnoreply@anthropic.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "415d7d2cd433d017380de841a431c663aedcc004",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir",
      "new_id": "8a7fc2a3af05789b34d03bfba16f556c067ff124",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir"
    },
    {
      "type": "modify",
      "old_id": "d4459a803418b7487fd99f92e2f4417159c71935",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir",
      "new_id": "f8f8197cbc00525fa5d3933c67677f48a9438450",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir"
    }
  ]
}