)]}'
{
  "commit": "30e5ef52da83cb3705d2c73c2457eeb627f745a6",
  "tree": "110f8d37e4409a06a82b7e8464553da363f5fdf2",
  "parents": [
    "423d6bdbad69ba7927df59cc475134fe14e9fc97"
  ],
  "author": {
    "name": "Valery Pykhtin",
    "email": "valery.pykhtin@amd.com",
    "time": "Mon Aug 31 13:06:03 2026 +0000"
  },
  "committer": {
    "name": "Valery Pykhtin",
    "email": "valery.pykhtin@amd.com",
    "time": "Mon Aug 31 13:47:29 2026 +0000"
  },
  "message": "[AMDGPU] Match the AsmParser\u0027s operand-side check and share its helper\n\nIn the upcoming PR AsmParser performs the same alignment check but differently:\nit tests whether a concrete physreg, which carries no regclass, is in the\nrelaxed operand\u0027s regclass.\n\nChange the verifier to work the same way, reusing\nAMDGPUBaseInfo::getUnalignedEquivalentRC.\n\nCo-Authored-By: Claude \u003cnoreply@anthropic.com\u003e\n",
  "tree_diff": [
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}