[AMDGPU][SILowerSGPRSpills] Correct insertion of IMPLICIT_DEF in cycles (#186348) si-lower-sgpr spills was observed inserting IMPLICIT_DEF for lane VGPR restores in the cycle header. The virtual VGPR is therefore not live-in to the header and wwm regallocfast does not insert a restore. This results in the vgpr being clobbered after each backedge. Correct this by inserting the IMPLICIT_DEF in a block that dominates all entries. Assisted by Claude.
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