)]}'
{
  "commit": "de480cc59fc39991e1fb2eff30b70bffb7aa8227",
  "tree": "0a057e7aba372374436b5162b6c2634ddcb2401b",
  "parents": [
    "e975ae3962a15484dba8df32af8181782f39451b"
  ],
  "author": {
    "name": "Chinmay Deshpande",
    "email": "chdeshpa@amd.com",
    "time": "Sun Sep 27 14:13:31 2026 -0400"
  },
  "committer": {
    "name": "Chinmay Deshpande",
    "email": "chdeshpa@amd.com",
    "time": "Sun Sep 27 14:13:31 2026 -0400"
  },
  "message": "[AMDGPU] Move dynamic VGPR allocation granules to TargetParser\n\nExtend getVGPRAllocGranule with a dynamic block size and preserve the\nfixed gfx90a-family granule. Remove the BaseInfo counterpart and migrate\nits occupancy, scheduler, frame lowering, and register-block callers.\n\nCover dynamic allocation, static mode, and gfx90a-family exceptions.\n\nChange-Id: Id441ddcea2d7a33121ddb4139af4c5f52f273ff3\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b611e5cbcc4fe765a0e8bc7319a53fcc657393cb",
      "old_mode": 33188,
      "old_path": "llvm/include/llvm/TargetParser/AMDGPUTargetParser.h",
      "new_id": "d8ad8dcd415c3db2c37da92421cd385e6ed10f8e",
      "new_mode": 33188,
      "new_path": "llvm/include/llvm/TargetParser/AMDGPUTargetParser.h"
    },
    {
      "type": "modify",
      "old_id": "89105a78c4e808af1168ed3f8f3314c98b8b7f0e",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp",
      "new_id": "cbe54f4d89832f45c37cf55e3783e5cb0a5fe5b8",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp"
    },
    {
      "type": "modify",
      "old_id": "602489ab3a5c14c72f14430244ef4e89c6c75585",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp",
      "new_id": "460c872dc46d6cb239c9c7158c49566d0f78ee57",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp"
    },
    {
      "type": "modify",
      "old_id": "c344367b460f4c3c96529342b212079bcf248ad9",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/GCNSubtarget.h",
      "new_id": "437cc9e942d5ad3e00053ec7d381b757a6a1a61e",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/GCNSubtarget.h"
    },
    {
      "type": "modify",
      "old_id": "364d8f07b6df25e08436dc0326e07790fa6bda74",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIFrameLowering.cpp",
      "new_id": "81a371352afccc0ea504bda0e3684dbc07fc585d",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIFrameLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "baaef6293b9b08151cf0af695a729c3049247409",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp",
      "new_id": "82a960391529172ebc48bbcc3f8a5f3a655f199c",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "564d77b0ad938ea6fc98495e880fafc9f10f5e78",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h",
      "new_id": "a57cfee284738808b792ff50c9f4bd9ffe1ebdd0",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h"
    },
    {
      "type": "modify",
      "old_id": "359b65363f2d196afb8685087598b19f14d88485",
      "old_mode": 33188,
      "old_path": "llvm/lib/TargetParser/AMDGPUTargetParser.cpp",
      "new_id": "bcdf5c356ef98203f9a4125dc896cb09fe8b2798",
      "new_mode": 33188,
      "new_path": "llvm/lib/TargetParser/AMDGPUTargetParser.cpp"
    },
    {
      "type": "modify",
      "old_id": "2c963026a6a453019ec76e7488dbeef3d6315537",
      "old_mode": 33188,
      "old_path": "llvm/unittests/TargetParser/TargetParserTest.cpp",
      "new_id": "7c5f156775bd2d0cf5b7a3ac8cac31b048f43c7a",
      "new_mode": 33188,
      "new_path": "llvm/unittests/TargetParser/TargetParserTest.cpp"
    }
  ]
}
