fixed a comment.

llvm/lib/Target/AMDGPU/SIInstrInfo.h

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1e46fe0..38b40ec5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1392,7 +1392,7 @@
     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
   }
 
-  /// Return the number of registers spilled/reloaded by the spill opcode.
+  /// Return the number of registers spilled/reloaded by the spill instruction.
   unsigned getNumSubRegsForSpillOp(const MachineInstr &MI) const;
 
   /// Legalize the \p OpIndex operand of this instruction by inserting