# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s

---
name: fabs_s32_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0
    ; SI-LABEL: name: fabs_s32_ss
    ; SI: liveins: $sgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; VI-LABEL: name: fabs_s32_ss
    ; VI: liveins: $sgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX9-LABEL: name: fabs_s32_ss
    ; GFX9: liveins: $sgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX10-LABEL: name: fabs_s32_ss
    ; GFX10: liveins: $sgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = G_FABS %0
    $sgpr0 = COPY %1
...

---
name: fabs_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0
    ; SI-LABEL: name: fabs_s32_vv
    ; SI: liveins: $vgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; VI-LABEL: name: fabs_s32_vv
    ; VI: liveins: $vgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX9-LABEL: name: fabs_s32_vv
    ; GFX9: liveins: $vgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX10-LABEL: name: fabs_s32_vv
    ; GFX10: liveins: $vgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = G_FABS %0
    $vgpr0 = COPY %1
...

---
name: fabs_s32_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0
    ; SI-LABEL: name: fabs_s32_vs
    ; SI: liveins: $sgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
    ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
    ;
    ; VI-LABEL: name: fabs_s32_vs
    ; VI: liveins: $sgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
    ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
    ;
    ; GFX9-LABEL: name: fabs_s32_vs
    ; GFX9: liveins: $sgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
    ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32)
    ;
    ; GFX10-LABEL: name: fabs_s32_vs
    ; GFX10: liveins: $sgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
    ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](s32)
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = G_FABS %0
    $vgpr0 = COPY %1
...

---
name: fabs_v2s16_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; SI-LABEL: name: fabs_v2s16_ss
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; VI-LABEL: name: fabs_v2s16_ss
    ; VI: liveins: $sgpr0_sgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX9-LABEL: name: fabs_v2s16_ss
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX10-LABEL: name: fabs_v2s16_ss
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    %0:sgpr(<2 x s16>) = COPY $sgpr0
    %1:sgpr(<2 x s16>) = G_FABS %0
    $sgpr0 = COPY %1
...

---
name: fabs_s16_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0
    ; SI-LABEL: name: fabs_s16_ss
    ; SI: liveins: $sgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; VI-LABEL: name: fabs_s16_ss
    ; VI: liveins: $sgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX9-LABEL: name: fabs_s16_ss
    ; GFX9: liveins: $sgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    ;
    ; GFX10-LABEL: name: fabs_s16_ss
    ; GFX10: liveins: $sgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s16) = G_TRUNC %0
    %2:sgpr(s16) = G_FABS %1
    %3:sgpr(s32) = G_ANYEXT %2
    $sgpr0 = COPY %3
...

---
name: fabs_s16_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0
    ; SI-LABEL: name: fabs_s16_vv
    ; SI: liveins: $vgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; VI-LABEL: name: fabs_s16_vv
    ; VI: liveins: $vgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX9-LABEL: name: fabs_s16_vv
    ; GFX9: liveins: $vgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX10-LABEL: name: fabs_s16_vv
    ; GFX10: liveins: $vgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_FABS %1
    %3:vgpr(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: fabs_s16_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; SI-LABEL: name: fabs_s16_vs
    ; SI: liveins: $sgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
    ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
    ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
    ;
    ; VI-LABEL: name: fabs_s16_vs
    ; VI: liveins: $sgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
    ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
    ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
    ;
    ; GFX9-LABEL: name: fabs_s16_vs
    ; GFX9: liveins: $sgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
    ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
    ;
    ; GFX10-LABEL: name: fabs_s16_vs
    ; GFX10: liveins: $sgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
    ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32)
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_FABS %1
    %3:vgpr(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: fabs_v2s16_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0
    ; SI-LABEL: name: fabs_v2s16_vv
    ; SI: liveins: $vgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; VI-LABEL: name: fabs_v2s16_vv
    ; VI: liveins: $vgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX9-LABEL: name: fabs_v2s16_vv
    ; GFX9: liveins: $vgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    ;
    ; GFX10-LABEL: name: fabs_v2s16_vv
    ; GFX10: liveins: $vgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %1:vgpr(<2 x s16>) = G_FABS %0
    $vgpr0 = COPY %1
...

---
name: fabs_v2s16_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0
    ; SI-LABEL: name: fabs_v2s16_vs
    ; SI: liveins: $sgpr0
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
    ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
    ;
    ; VI-LABEL: name: fabs_v2s16_vs
    ; VI: liveins: $sgpr0
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
    ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
    ;
    ; GFX9-LABEL: name: fabs_v2s16_vs
    ; GFX9: liveins: $sgpr0
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
    ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
    ;
    ; GFX10-LABEL: name: fabs_v2s16_vs
    ; GFX10: liveins: $sgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
    ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
    %0:sgpr(<2 x s16>) = COPY $sgpr0
    %1:vgpr(<2 x s16>) = G_FABS %0
    $vgpr0 = COPY %1
...

---
name: fabs_s64_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; SI-LABEL: name: fabs_s64_ss
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
    ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; SI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
    ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; VI-LABEL: name: fabs_s64_ss
    ; VI: liveins: $sgpr0_sgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
    ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; VI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
    ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX9-LABEL: name: fabs_s64_ss
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
    ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX10-LABEL: name: fabs_s64_ss
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
    ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_FABS %0
    S_ENDPGM 0, implicit %1
...

---
name: fabs_s64_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; SI-LABEL: name: fabs_s64_vv
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
    ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; VI-LABEL: name: fabs_s64_vv
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
    ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX9-LABEL: name: fabs_s64_vv
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX10-LABEL: name: fabs_s64_vv
    ; GFX10: liveins: $vgpr0_vgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
    ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = G_FABS %0
    S_ENDPGM 0, implicit %1
...

---
name: fabs_s64_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; SI-LABEL: name: fabs_s64_vs
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
    ; SI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
    ;
    ; VI-LABEL: name: fabs_s64_vs
    ; VI: liveins: $sgpr0_sgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
    ; VI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
    ;
    ; GFX9-LABEL: name: fabs_s64_vs
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
    ; GFX9-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
    ;
    ; GFX10-LABEL: name: fabs_s64_vs
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:vgpr(s64) = G_FABS %0
    S_ENDPGM 0, implicit %1
...

# Make sure the source register is constrained
---
name: fabs_s64_vv_no_src_constraint
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; SI-LABEL: name: fabs_s64_vv_no_src_constraint
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
    ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; VI-LABEL: name: fabs_s64_vv_no_src_constraint
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
    ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX9-LABEL: name: fabs_s64_vv_no_src_constraint
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
    ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX10-LABEL: name: fabs_s64_vv_no_src_constraint
    ; GFX10: liveins: $vgpr0_vgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
    ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(s64) = IMPLICIT_DEF
    %1:vgpr(s64) = G_FABS %0:vgpr(s64)
    S_ENDPGM 0, implicit %1
...

---
name: fabs_s64_ss_no_src_constraint
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; SI-LABEL: name: fabs_s64_ss_no_src_constraint
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
    ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; VI-LABEL: name: fabs_s64_ss_no_src_constraint
    ; VI: liveins: $sgpr0_sgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
    ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX9-LABEL: name: fabs_s64_ss_no_src_constraint
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9-NEXT: {{  $}}
    ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
    ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    ;
    ; GFX10-LABEL: name: fabs_s64_ss_no_src_constraint
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
    ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
    ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(s64) = IMPLICIT_DEF
    %1:sgpr(s64) = G_FABS %0:sgpr(s64)
    S_ENDPGM 0, implicit %1
...